JP4860219B2 - 基板の処理方法、電子デバイスの製造方法及びプログラム - Google Patents

基板の処理方法、電子デバイスの製造方法及びプログラム Download PDF

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JP4860219B2
JP4860219B2 JP2005278843A JP2005278843A JP4860219B2 JP 4860219 B2 JP4860219 B2 JP 4860219B2 JP 2005278843 A JP2005278843 A JP 2005278843A JP 2005278843 A JP2005278843 A JP 2005278843A JP 4860219 B2 JP4860219 B2 JP 4860219B2
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insulating film
dielectric constant
low dielectric
layer
product
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JP2005278843A
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Japanese (ja)
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JP2006253634A (ja
JP2006253634A5 (enExample
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栄一 西村
賢也 岩▲崎▼
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to JP2005278843A priority Critical patent/JP4860219B2/ja
Priority to KR1020060013738A priority patent/KR100830736B1/ko
Priority to TW095104740A priority patent/TWI456691B/zh
Priority to US11/353,132 priority patent/US7682517B2/en
Priority to EP06002925A priority patent/EP1691408A3/en
Priority to CNB2006100074778A priority patent/CN100517602C/zh
Publication of JP2006253634A publication Critical patent/JP2006253634A/ja
Publication of JP2006253634A5 publication Critical patent/JP2006253634A5/ja
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    • EFIXED CONSTRUCTIONS
    • E04BUILDING
    • E04CSTRUCTURAL ELEMENTS; BUILDING MATERIALS
    • E04C2/00Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels
    • E04C2/30Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by the shape or structure
    • E04C2/32Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by the shape or structure formed of corrugated or otherwise indented sheet-like material; composed of such layers with or without layers of flat sheet-like material
    • E04C2/322Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by the shape or structure formed of corrugated or otherwise indented sheet-like material; composed of such layers with or without layers of flat sheet-like material with parallel corrugations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • EFIXED CONSTRUCTIONS
    • E04BUILDING
    • E04BGENERAL BUILDING CONSTRUCTIONS; WALLS, e.g. PARTITIONS; ROOFS; FLOORS; CEILINGS; INSULATION OR OTHER PROTECTION OF BUILDINGS
    • E04B1/00Constructions in general; Structures which are not restricted either to walls, e.g. partitions, or floors or ceilings or roofs
    • E04B1/38Connections for building structures in general
    • E04B1/61Connections for building structures in general of slab-shaped building elements with each other
    • E04B1/6108Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together
    • E04B1/612Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces
    • E04B1/6125Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces with protrusions on the one frontal surface co-operating with recesses in the other frontal surface
    • E04B1/6137Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces with protrusions on the one frontal surface co-operating with recesses in the other frontal surface the connection made by formlocking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67155Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67201Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the load-lock chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/906Cleaning of wafer as interim step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Architecture (AREA)
  • Chemical & Material Sciences (AREA)
  • Structural Engineering (AREA)
  • Civil Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Electromagnetism (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2005278843A 2005-02-14 2005-09-26 基板の処理方法、電子デバイスの製造方法及びプログラム Expired - Lifetime JP4860219B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2005278843A JP4860219B2 (ja) 2005-02-14 2005-09-26 基板の処理方法、電子デバイスの製造方法及びプログラム
TW095104740A TWI456691B (zh) 2005-02-14 2006-02-13 基板之處理方法,電子裝置之製造方法及程式
KR1020060013738A KR100830736B1 (ko) 2005-02-14 2006-02-13 기판 처리 방법, 전자 디바이스 제조 방법 및 프로그램을기록한 기록 매체
EP06002925A EP1691408A3 (en) 2005-02-14 2006-02-14 Method of and program for manufacturing an electronic device
US11/353,132 US7682517B2 (en) 2005-02-14 2006-02-14 Method of processing substrate, and method of and program for manufacturing electronic device
CNB2006100074778A CN100517602C (zh) 2005-02-14 2006-02-14 基板的处理方法、电子器件的制造方法和程序

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005036716 2005-02-14
JP2005036716 2005-02-14
JP2005278843A JP4860219B2 (ja) 2005-02-14 2005-09-26 基板の処理方法、電子デバイスの製造方法及びプログラム

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JP2006253634A JP2006253634A (ja) 2006-09-21
JP2006253634A5 JP2006253634A5 (enExample) 2008-11-06
JP4860219B2 true JP4860219B2 (ja) 2012-01-25

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US (1) US7682517B2 (enExample)
EP (1) EP1691408A3 (enExample)
JP (1) JP4860219B2 (enExample)
KR (1) KR100830736B1 (enExample)
CN (1) CN100517602C (enExample)
TW (1) TWI456691B (enExample)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7795148B2 (en) * 2006-03-28 2010-09-14 Tokyo Electron Limited Method for removing damaged dielectric material
JP2008034736A (ja) * 2006-07-31 2008-02-14 Tokyo Electron Ltd 熱処理方法および熱処理装置
US7723237B2 (en) * 2006-12-15 2010-05-25 Tokyo Electron Limited Method for selective removal of damaged multi-stack bilayer films
JP2008192835A (ja) * 2007-02-05 2008-08-21 Tokyo Electron Ltd 成膜方法,基板処理装置,および半導体装置
KR20100031681A (ko) 2007-05-18 2010-03-24 브룩스 오토메이션 인코퍼레이티드 빠른 교환 로봇을 가진 컴팩트 기판 운송 시스템
US20100184297A1 (en) * 2007-06-22 2010-07-22 Mikio Takagi Method for protecting semiconductor wafer and process for producing semiconductor device
TWI459851B (zh) * 2007-09-10 2014-11-01 Ngk Insulators Ltd heating equipment
JP5374039B2 (ja) * 2007-12-27 2013-12-25 東京エレクトロン株式会社 基板処理方法、基板処理装置及び記憶媒体
JP5084525B2 (ja) * 2008-01-22 2012-11-28 株式会社アルバック 基板処理装置、及び基板処理方法
JP2010278040A (ja) * 2009-05-26 2010-12-09 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8696815B2 (en) 2009-09-01 2014-04-15 Samsung Display Co., Ltd. Thin film deposition apparatus
KR101732023B1 (ko) * 2010-12-23 2017-05-02 삼성전자주식회사 반도체 장치의 형성 방법
US8569158B2 (en) 2011-03-31 2013-10-29 Tokyo Electron Limited Method for forming ultra-shallow doping regions by solid phase diffusion
US8580664B2 (en) 2011-03-31 2013-11-12 Tokyo Electron Limited Method for forming ultra-shallow boron doping regions by solid phase diffusion
KR20130004830A (ko) * 2011-07-04 2013-01-14 삼성디스플레이 주식회사 유기층 증착 장치 및 이를 이용한 유기 발광 표시 장치의 제조 방법
JP2013048127A (ja) * 2011-07-26 2013-03-07 Applied Materials Inc アッシュ後の側壁の回復
CN102931130A (zh) * 2011-08-11 2013-02-13 应用材料公司 灰化后侧壁修复
JP6110848B2 (ja) * 2012-05-23 2017-04-05 東京エレクトロン株式会社 ガス処理方法
US8871639B2 (en) 2013-01-04 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9543163B2 (en) 2013-08-20 2017-01-10 Applied Materials, Inc. Methods for forming features in a material layer utilizing a combination of a main etching and a cyclical etching process
US9576811B2 (en) 2015-01-12 2017-02-21 Lam Research Corporation Integrating atomic scale processes: ALD (atomic layer deposition) and ALE (atomic layer etch)
US9899224B2 (en) 2015-03-03 2018-02-20 Tokyo Electron Limited Method of controlling solid phase diffusion of boron dopants to form ultra-shallow doping regions
US9806252B2 (en) 2015-04-20 2017-10-31 Lam Research Corporation Dry plasma etch method to pattern MRAM stack
US9870899B2 (en) 2015-04-24 2018-01-16 Lam Research Corporation Cobalt etch back
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US10096487B2 (en) 2015-08-19 2018-10-09 Lam Research Corporation Atomic layer etching of tungsten and other metals
US9984858B2 (en) 2015-09-04 2018-05-29 Lam Research Corporation ALE smoothness: in and outside semiconductor industry
US10727073B2 (en) 2016-02-04 2020-07-28 Lam Research Corporation Atomic layer etching 3D structures: Si and SiGe and Ge smoothness on horizontal and vertical surfaces
US10229837B2 (en) 2016-02-04 2019-03-12 Lam Research Corporation Control of directionality in atomic layer etching
US9991128B2 (en) 2016-02-05 2018-06-05 Lam Research Corporation Atomic layer etching in continuous plasma
US10269566B2 (en) 2016-04-29 2019-04-23 Lam Research Corporation Etching substrates using ale and selective deposition
US9837312B1 (en) 2016-07-22 2017-12-05 Lam Research Corporation Atomic layer etching for enhanced bottom-up feature fill
CN109563617B (zh) * 2016-08-26 2021-06-08 应用材料公司 低压升降杆腔硬件
US10566212B2 (en) 2016-12-19 2020-02-18 Lam Research Corporation Designer atomic layer etching
US10559451B2 (en) * 2017-02-15 2020-02-11 Applied Materials, Inc. Apparatus with concentric pumping for multiple pressure regimes
JP6956551B2 (ja) * 2017-03-08 2021-11-02 東京エレクトロン株式会社 酸化膜除去方法および除去装置、ならびにコンタクト形成方法およびコンタクト形成システム
US20180261464A1 (en) * 2017-03-08 2018-09-13 Tokyo Electron Limited Oxide film removing method, oxide film removing apparatus, contact forming method, and contact forming system
US10559461B2 (en) 2017-04-19 2020-02-11 Lam Research Corporation Selective deposition with atomic layer etch reset
US9997371B1 (en) 2017-04-24 2018-06-12 Lam Research Corporation Atomic layer etch methods and hardware for patterning applications
US10832909B2 (en) 2017-04-24 2020-11-10 Lam Research Corporation Atomic layer etch, reactive precursors and energetic sources for patterning applications
WO2019190781A1 (en) 2018-03-30 2019-10-03 Lam Research Corporation Atomic layer etching and smoothing of refractory metals and other high surface binding energy materials
US11131919B2 (en) * 2018-06-22 2021-09-28 International Business Machines Corporation Extreme ultraviolet (EUV) mask stack processing
JP7349861B2 (ja) * 2019-09-24 2023-09-25 東京エレクトロン株式会社 エッチング方法、ダメージ層の除去方法、および記憶媒体
TWI895472B (zh) * 2020-08-17 2025-09-01 日商東京威力科創股份有限公司 蝕刻方法及蝕刻裝置

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68928402T2 (de) * 1988-12-27 1998-03-12 Toshiba Kawasaki Kk Verfahren zur Entfernung einer Oxidschicht auf einem Substrat
US6562544B1 (en) * 1996-11-04 2003-05-13 Applied Materials, Inc. Method and apparatus for improving accuracy in photolithographic processing of substrates
JP3869089B2 (ja) * 1996-11-14 2007-01-17 株式会社日立製作所 半導体集積回路装置の製造方法
US6074951A (en) * 1997-05-29 2000-06-13 International Business Machines Corporation Vapor phase etching of oxide masked by resist or masking material
JPH1174354A (ja) * 1997-06-30 1999-03-16 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6805139B1 (en) * 1999-10-20 2004-10-19 Mattson Technology, Inc. Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing
US6265320B1 (en) * 1999-12-21 2001-07-24 Novellus Systems, Inc. Method of minimizing reactive ion etch damage of organic insulating layers in semiconductor fabrication
US6677549B2 (en) * 2000-07-24 2004-01-13 Canon Kabushiki Kaisha Plasma processing apparatus having permeable window covered with light shielding film
KR100365641B1 (ko) * 2000-07-29 2002-12-26 삼성전자 주식회사 배선에 의한 기생 용량을 줄일 수 있는 반도체 장치 및 그형성방법
TW461051B (en) * 2000-11-10 2001-10-21 Silicon Based Tech Corp Manufacturing of shrinkable split-gate flash memory with three-sided erase electrodes
US6926843B2 (en) * 2000-11-30 2005-08-09 International Business Machines Corporation Etching of hard masks
JP2002303993A (ja) 2001-04-04 2002-10-18 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2002353308A (ja) * 2001-05-28 2002-12-06 Toshiba Corp 半導体装置及びその製造方法
TW504799B (en) * 2001-12-28 2002-10-01 Shr Min Copper line fabrication method
US6660598B2 (en) 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
JP3606272B2 (ja) * 2002-06-26 2005-01-05 松下電器産業株式会社 配線構造の形成方法
JP3909283B2 (ja) * 2002-10-31 2007-04-25 富士通株式会社 半導体装置の製造方法
US6838300B2 (en) * 2003-02-04 2005-01-04 Texas Instruments Incorporated Chemical treatment of low-k dielectric films
JP2004247417A (ja) * 2003-02-12 2004-09-02 Renesas Technology Corp 半導体装置の製造方法
US6951821B2 (en) 2003-03-17 2005-10-04 Tokyo Electron Limited Processing system and method for chemically treating a substrate
US7029536B2 (en) * 2003-03-17 2006-04-18 Tokyo Electron Limited Processing system and method for treating a substrate
US7079760B2 (en) 2003-03-17 2006-07-18 Tokyo Electron Limited Processing system and method for thermally treating a substrate
US6905941B2 (en) * 2003-06-02 2005-06-14 International Business Machines Corporation Structure and method to fabricate ultra-thin Si channel devices
JP4833512B2 (ja) * 2003-06-24 2011-12-07 東京エレクトロン株式会社 被処理体処理装置、被処理体処理方法及び被処理体搬送方法
US7097779B2 (en) * 2004-07-06 2006-08-29 Tokyo Electron Limited Processing system and method for chemically treating a TERA layer

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Publication number Publication date
US7682517B2 (en) 2010-03-23
TWI456691B (zh) 2014-10-11
JP2006253634A (ja) 2006-09-21
CN1822326A (zh) 2006-08-23
KR20060018918A (ko) 2006-03-02
KR100830736B1 (ko) 2008-05-20
US20060194435A1 (en) 2006-08-31
TW200636914A (en) 2006-10-16
EP1691408A2 (en) 2006-08-16
CN100517602C (zh) 2009-07-22
EP1691408A3 (en) 2010-01-06

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