JP4851755B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4851755B2 JP4851755B2 JP2005259098A JP2005259098A JP4851755B2 JP 4851755 B2 JP4851755 B2 JP 4851755B2 JP 2005259098 A JP2005259098 A JP 2005259098A JP 2005259098 A JP2005259098 A JP 2005259098A JP 4851755 B2 JP4851755 B2 JP 4851755B2
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- fuses
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- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/143—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using laser-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Optics & Photonics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Fuses (AREA)
Description
図1は、本発明による半導体装置の第1実施形態を示す回路図である。半導体装置1は、信号出力部10、および判定部20を備えている。信号出力部10は、m(≧2)個のヒューズ12a,12b、NANDゲート14、抵抗素子16a,16b、および出力端子18を含んでいる。本実施形態においてmは2に等しい。
図2は、本発明による半導体装置の第2実施形態を示す回路図である。半導体装置2は、信号出力部10、および判定部30を備えている。信号出力部10は、m(≧2)個のヒューズ12a,12b,12c、NANDゲート14、抵抗素子16a,16b,16c、および出力端子18を含んでいる。本実施形態においてmは3に等しい。
2 半導体装置
10 信号出力部
12a,12b,12c ヒューズ
13 電源端子
14 NANDゲート
16a,16b,16c 抵抗素子
18 出力端子
20 判定部
22 NORゲート
24 出力端子
30 判定部
32a,32b,32c ANDゲート
34 NORゲート
36 出力端子
42a,42b,42c NANDゲート
44 NANDゲート
52a,52b,52c NORゲート
54 NORゲート
60 信号出力部
62a,62b アンチヒューズ
64 NORゲート
66a,66b 抵抗素子
68 出力端子
70 判定部
72 NANDゲート
74 出力端子
80 判定部
82 NORゲート
84 出力端子
Claims (9)
- 半導体基板の上部に設けられたm個(m≧2)のヒューズと、前記m個のヒューズの切断状態に依存した2値信号を出力する出力端子とを含む信号出力部と、
前記信号出力部に含まれる前記m個のヒューズのうちn個(m≧n≧2)以上が切断されているか否かを判定し、その判定結果を出力する判定部と、
を備えることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記信号出力部の前記出力端子は、前記m個のヒューズのうち少なくとも1つが切断されている場合に第1の大きさの電位信号を出力し、前記m個のヒューズの何れも切断されていない場合に第2の大きさの電位信号を出力する半導体装置。 - 請求項1または2に記載の半導体装置において、
前記判定部は、前記ヒューズの一端の電位を入力信号とする論理ゲートを有し、当該論理ゲートの出力信号として前記判定結果を出力する半導体装置。 - 請求項3に記載の半導体装置において、
前記判定部は、前記各ヒューズの一端に接続された前記m個の入力端子をもつ、NANDゲートまたはNORゲートを有する半導体装置。 - 請求項3に記載の半導体装置において、
前記mは3に等しく、
前記判定部は、
前記3個のヒューズのうち第1および第2のヒューズそれぞれの一端に接続された2個の入力端子をもつ第1のANDゲートと、前記第2および第3のヒューズそれぞれの一端に接続された2個の入力端子をもつ第2のANDゲートと、前記第3および前記第1のヒューズそれぞれの一端に接続された2個の入力端子をもつ第3のANDゲートと、前記第1、第2および第3のANDゲートそれぞれの出力端子に接続された3個の入力端子をもつNORゲートと、を有する半導体装置。 - 請求項3に記載の半導体装置において、
前記mは3に等しく、
前記判定部は、
前記3個のヒューズのうち第1および第2のヒューズそれぞれの一端に接続された2個の入力端子をもつ第1のNANDゲートと、前記第2および第3のヒューズそれぞれの一端に接続された2個の入力端子をもつ第2のNANDゲートと、前記第3および前記第1のヒューズそれぞれの一端に接続された2個の入力端子をもつ第3のNANDゲートと、前記第1、第2および第3のNANDゲートそれぞれの出力端子に接続された3個の入力端子をもつ第4のNANDゲートと、を有する半導体装置。 - 請求項3に記載の半導体装置において、
前記mは3に等しく、
前記判定部は、
前記3個のヒューズのうち第1および第2のヒューズそれぞれの一端に接続された2個の入力端子をもつ第1のNORゲートと、前記第2および第3のヒューズそれぞれの一端に接続された2個の入力端子をもつ第2のNORゲートと、前記第3および前記第1のヒューズそれぞれの一端に接続された2個の入力端子をもつ第3のNORゲートと、前記第1、第2および第3のNORゲートそれぞれの出力端子に接続された3個の入力端子をもつ第4のNORゲートと、を有する半導体装置。 - 請求項1乃至7いずれかに記載の半導体装置において、
前記ヒューズは電気ヒューズである半導体装置。 - 半導体基板の上部に設けられたm個(m≧2)のアンチヒューズと、前記m個のアンチヒューズの接続状態に依存した2値信号を出力する出力端子とを含む信号出力部と、
前記信号出力部に含まれる前記m個のアンチヒューズのうちn個(m≧n≧2)以上が接続されているか否かを判定し、その判定結果を出力する判定部と、
を備えることを特徴とする半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005259098A JP4851755B2 (ja) | 2005-09-07 | 2005-09-07 | 半導体装置 |
US11/510,639 US8217709B2 (en) | 2005-09-07 | 2006-08-28 | Semiconductor device |
CN200610128155.9A CN100470805C (zh) | 2005-09-07 | 2006-09-06 | 半导体器件 |
US13/529,421 US8339182B2 (en) | 2005-09-07 | 2012-06-21 | Semiconductor device |
US13/707,150 US8461907B2 (en) | 2005-09-07 | 2012-12-06 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005259098A JP4851755B2 (ja) | 2005-09-07 | 2005-09-07 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007073735A JP2007073735A (ja) | 2007-03-22 |
JP4851755B2 true JP4851755B2 (ja) | 2012-01-11 |
Family
ID=37859017
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005259098A Active JP4851755B2 (ja) | 2005-09-07 | 2005-09-07 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (3) | US8217709B2 (ja) |
JP (1) | JP4851755B2 (ja) |
CN (1) | CN100470805C (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4855985B2 (ja) | 2007-03-20 | 2012-01-18 | 株式会社エヌ・ティ・ティ・ドコモ | 移動通信システムにおけるセル情報送信方法およびユーザ装置 |
CN115295059B (zh) * | 2022-10-09 | 2023-03-03 | 浙江力积存储科技有限公司 | 半导体器件及其操作方法、装置和计算机可读存储介质 |
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US3533088A (en) * | 1967-10-31 | 1970-10-06 | Rca Corp | Control circuit for memory |
US4714839A (en) * | 1986-03-27 | 1987-12-22 | Advanced Micro Devices, Inc. | Control circuit for disabling or enabling the provision of redundancy |
US4721868A (en) * | 1986-09-23 | 1988-01-26 | Advanced Micro Devices, Inc. | IC input circuitry programmable for realizing multiple functions from a single input |
JPH02146195A (ja) * | 1988-11-28 | 1990-06-05 | Nec Corp | 半導体記憶装置 |
JPH03214500A (ja) * | 1990-01-18 | 1991-09-19 | Sony Corp | メモリ装置 |
JP2575919B2 (ja) * | 1990-03-22 | 1997-01-29 | 株式会社東芝 | 半導体記憶装置の冗長回路 |
US5959445A (en) * | 1995-09-29 | 1999-09-28 | Intel Corporation | Static, high-sensitivity, fuse-based storage cell |
US6037799A (en) * | 1995-12-29 | 2000-03-14 | Stmicroelectronics, Inc. | Circuit and method for selecting a signal |
JPH11121627A (ja) * | 1997-10-16 | 1999-04-30 | Oki Electric Ind Co Ltd | 半導体メモリ |
JPH11297837A (ja) * | 1998-04-08 | 1999-10-29 | Seiko Epson Corp | 半導体装置 |
US6175261B1 (en) * | 1999-01-07 | 2001-01-16 | Texas Instruments Incorporated | Fuse cell for on-chip trimming |
JP2004111990A (ja) * | 1999-07-06 | 2004-04-08 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置及びその製造方法 |
US6275063B1 (en) * | 1999-08-24 | 2001-08-14 | Micron Technology, Inc. | Method and apparatus for limited reprogrammability of fuse options using one-time programmable elements |
KR100376265B1 (ko) * | 1999-12-29 | 2003-03-17 | 주식회사 하이닉스반도체 | 모스 구조의 안티퓨즈를 이용한 메모리 리페어 회로 |
US6353336B1 (en) * | 2000-03-24 | 2002-03-05 | Cypress Semiconductor Corp. | Electrical ID method for output driver |
JP2002076275A (ja) * | 2000-08-25 | 2002-03-15 | Hitachi Ltd | 半導体集積回路 |
JP2002110806A (ja) * | 2000-09-29 | 2002-04-12 | Rohm Co Ltd | Icチップおよび半導体装置 |
KR100481179B1 (ko) * | 2002-09-10 | 2005-04-07 | 삼성전자주식회사 | 퓨즈를 구비한 회로 및 이를 이용한 반도체 장치 |
JP3884374B2 (ja) * | 2002-12-06 | 2007-02-21 | 株式会社東芝 | 半導体装置 |
JP2005039220A (ja) | 2003-06-26 | 2005-02-10 | Nec Electronics Corp | 半導体装置 |
JP4795631B2 (ja) | 2003-08-07 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4545416B2 (ja) * | 2003-11-04 | 2010-09-15 | パナソニック株式会社 | Prom回路 |
KR100569585B1 (ko) * | 2003-12-05 | 2006-04-10 | 주식회사 하이닉스반도체 | 내부 전원 드라이버 제어 회로 |
JP4478980B2 (ja) * | 2004-10-05 | 2010-06-09 | エルピーダメモリ株式会社 | ヒューズ回路及びそれを利用した半導体装置 |
JP4686210B2 (ja) * | 2005-02-24 | 2011-05-25 | ルネサスエレクトロニクス株式会社 | 半導体チップ |
-
2005
- 2005-09-07 JP JP2005259098A patent/JP4851755B2/ja active Active
-
2006
- 2006-08-28 US US11/510,639 patent/US8217709B2/en active Active
- 2006-09-06 CN CN200610128155.9A patent/CN100470805C/zh active Active
-
2012
- 2012-06-21 US US13/529,421 patent/US8339182B2/en active Active
- 2012-12-06 US US13/707,150 patent/US8461907B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1929135A (zh) | 2007-03-14 |
US8217709B2 (en) | 2012-07-10 |
US8461907B2 (en) | 2013-06-11 |
US8339182B2 (en) | 2012-12-25 |
US20070070736A1 (en) | 2007-03-29 |
US20130093044A1 (en) | 2013-04-18 |
CN100470805C (zh) | 2009-03-18 |
US20120262223A1 (en) | 2012-10-18 |
JP2007073735A (ja) | 2007-03-22 |
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