JP4797203B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4797203B2 JP4797203B2 JP2008321391A JP2008321391A JP4797203B2 JP 4797203 B2 JP4797203 B2 JP 4797203B2 JP 2008321391 A JP2008321391 A JP 2008321391A JP 2008321391 A JP2008321391 A JP 2008321391A JP 4797203 B2 JP4797203 B2 JP 4797203B2
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Description
まず、はじめに、本半導体装置が適用される制御駆動回路の一例について説明する。図1に示すように、スイッチング素子として第1IGBT61と第2IGBT62とが直列に接続され、第1IGBT61と第2IGBT62との接続点Eに、誘導電動機等の負荷57が接続されている。第1IGBT61のコレクタが高電圧に接続され、第2IGBT62のエミッタが接地電圧(電位)に接続されている。第1IGBT61と第2IGBT62とは交互にオン、オフされ、第1IGBT61がオンの状態で負荷57に電流が送り込まれ、第2IGBT62がオンの状態で負荷から電流が引出される。
このように、本半導体装置では、センス抵抗9と第1ロジック回路26(高圧側回路52)等が形成された高電位ロジック領域25の周囲を取り囲むように、分離領域30を介在させて、環状のRESURF領域24が配置され、そのRESURF領域に、スパイラル状のポリシリコン抵抗と電界効果トランジスタが形成されている。
高耐圧電位島127には第1RESURF領域124aが必要とされ、高耐圧LDMOS領域121には第2RESURF領域124bが必要とされる。
ここでは、埋め込み拡散領域を備えた半導体装置について説明する。図10に示すように、P型半導体基板1の表面上にはP型エピタキシャル成長層39が形成されている。高電位ロジック領域25では、P型半導体基板1のP型領域の部分とN型拡散領域31との間にN+埋め込み拡散領域37が形成されている。また、RESURF領域24では、P型半導体基板1のP型領域の部分とN型拡散領域2との間のうち、ドレイン電極12直下に位置する部分にN+埋め込み拡散領域37が形成されている。なお、これ以外の構成については、図4に示す構成と同様なので、同一部材には同一符号を付し、その説明を省略する。
上述した半導体装置では、P型半導体基板1のP型の領域の部分とN型拡散領域31との間にN+埋め込み拡散領域37が形成されている。そのN+埋め込み拡散領域37の不純物濃度は1019cm-3程度とされる。これにより、ベース層の不純物濃度NBの値とベース層の幅WBの値が、N+埋め込み拡散領域37が形成されていない場合の値よりも大きくなる。その結果、寄生PNPトランジスタの動作が抑制されて、回路の誤動作やラッチアップによって半導体装置が破壊されるのを防止することができる。
ここでは、分離領域として、P型拡散領域を適用した半導体装置について説明する。図11に示すように、P型半導体基板1の表面上にP型エピタキシャル成長層39が形成されている。RESURF領域24と高電位ロジック領域25との間に位置するP型エピタキシャル成長層39の部分の表面から所定の深さにわたり、電気的に浮遊のP拡散領域36が形成されている。なお、これ以外の構成については、図10に示す構成と同様なので、同一部材には同一符号を付し、その説明を省略する。
ここでは、分離領域として、トレンチ分離構造を適用した半導体装置の一例について説明する。図14に示すように、P型半導体基板1の表面上にP型エピタキシャル成長層39が形成されている。RESURF領域24と高電位ロジック領域25との間に位置するP型エピタキシャル成長層39の部分には、P型エピタキシャル成長層39の表面からP型半導体基板1の領域にまで達するトレンチ分離部38が形成されている。なお、これ以外の構成については、図11に示す構成と同様なので、同一部材には同一符号を付し、その説明を省略する。
ここでは、分離領域として、トレンチ分離構造を適用した半導体装置の他の例について説明する。図15に示すように、RESURF領域24に位置するN型拡散領域2における、高電位ロジック領域25側の端部に、トレンチ分離部38が形成され、高電位ロジック領域25に位置するN型拡散領域31における、RESURF領域24側の端部に、トレンチ分離部38が形成されている。なお、これ以外の構成については、図4に示す構成と同様なので、同一部材には同一符号を付し、その説明を省略する。
ここでは、RESURF領域に、電気的に浮遊なフィールドプレートを備えた半導体装置の一例について説明する。600V程度の高電位が印加される半導体装置では、RESURF領域の距離(幅)としては、約100μm以上必要とされる。また、半導体装置としては、半導体基板の表面はモールド樹脂によって封止される。そのモールド樹脂からは、荷電イオン(不純物イオン)が遊離することがある。そうすると、RESURF領域が、その荷電イオンの影響を受けて電位的に不安定になり、ポリシリコン抵抗の抵抗値が変化することが想定される。
ここでは、RESURF領域に、電気的に浮遊なフィールドプレートを備えた半導体装置の他の例について説明する。ポリシリコン抵抗4は、ドレイン電極12側の高電位領域からソース電極側の低電位領域まで連続的にスパイラル状に形成されており、ポリシリコン抵抗4における各部の電位はオームの法則により連続的に変化している。
本半導体装置では、図18に示すように、環状のRESURF領域24の周方向に断続的にフィールドプレート28が形成され、その周方向に断続的なフィールドプレート28が、環状のRESURF領域24の径方向に3組形成されている。つまり、このフィールドプレート28は、前述した図16に示されるフィールドプレート28において周方向の適当な位置においてスリットが形成された構造とされる。なお、これ以外の構成については、図16に示す構成と同様なので、同一部材には同一符号を付しその説明を省略する。
Claims (8)
- 第1導電型の半導体基板の主表面に形成され、第1駆動電圧で駆動して所定のスイッチング素子の動作を制御する第1ロジック回路および第1抵抗を含み、第1電圧がバイアスとして印加される第1ロジック回路領域と、
前記第1ロジック回路部を周方向から取り囲むように前記半導体基板の主表面に環状に形成され、前記第1抵抗と電気的にそれぞれ接続された電界効果トランジスタおよび第2抵抗を含む環状領域と、
前記第1ロジック回路領域と前記環状領域との間に形成され、前記第1ロジック回路領域と前記環状領域とを電気的に分離する分離領域と、
前記環状領域の外側に位置する前記半導体基板の主表面に形成され、前記電界効果トランジスタと前記第2抵抗にそれぞれ電気的に接続されて第2駆動電圧で駆動する第2ロジック回路を含み、前記第1電圧よりも低い第2電圧がバイアスとして印加される第2ロジック回路領域と
を備え、
前記第1ロジック回路は、前記電界効果トランジスタがオンして前記第1抵抗を前記電界効果トランジスタのドレイン電流が流れることにより生じる所定の電位差に基づいて前記スイッチング素子の動作を制御し、
前記第2ロジック回路は、前記第2抵抗を流れる電流を検知することにより、前記ドレイン電流として一定の電流を流すために前記電界効果トランジスタのゲートに印加すべきゲート電圧を求めて、前記ゲート電圧を前記ゲートに印加し、
前記環状領域では、その内周側に位置する部分に前記電界効果トランジスタのドレイン電極が前記内周に沿って形成され、その外周側に位置する部分に前記電界効果トランジスタのソース電極が前記外周に沿って形成され、その内周側からその外周側に向かって前記第2抵抗がスパイラル状に形成され、
前記環状領域は、前記第2ロジック回路領域に対し、前記第1電圧が印加される前記電界効果トランジスタのドレインを電気的に分離し、
前記分離領域は、前記第1電圧が印加される前記電界効果トランジスタのドレインに対し、前記第1ロジック回路領域を少なくとも前記第1駆動電圧分電気的に分離する、半導体装置。 - 前記第1ロジック回路領域は、前記半導体基板の主表面から第1の深さにわたり形成された第2導電型の第1不純物領域を含み、
前記環状領域は、前記半導体基板の主表面から第2の深さにわたり形成された第2導電型の第2不純物領域を含み、
前記分離領域は、前記第1不純物領域と前記第2不純物領域とによって挟まれた前記半導体基板の第1導電型の領域の部分から形成された、請求項1記載の半導体装置。 - 前記第1ロジック回路領域は、
前記第1不純物領域の表面から所定の深さにわたり形成された、前記第1抵抗としての第1導電型の第3不純物領域と、
前記第3不純物領域の直下に間隔を隔てて形成され、前記第1不純物領域の不純物濃度よりも高い不純物濃度を有する第2導電型の第4不純物領域と
を含む、請求項2記載の半導体装置。 - 前記分離領域は、
前記第1不純物領域と前記第2不純物領域とによって挟まれた前記半導体基板の第1導電型の領域の部分と前記第1不純物領域とを隔てるように形成された第1トレンチ分離部と、
前記第1導電型の領域の部分と前記第2不純物領域とを隔てるように形成された第2トレンチ分離部と
を含む、請求項2または3に記載の半導体装置。 - 前記半導体基板の主表面上に形成された、所定の厚さの第2導電型の第1半導体層を含み、
前記第1ロジック回路領域および前記環状領域は、前記第1半導体層に形成され、
前記分離領域は、前記第1ロジック回路領域に位置する前記第1半導体層の部分と、前記環状領域に位置する前記第1半導体層の部分との間に位置する前記第1半導体層の部分の表面から所定の深さにわたり形成された第1導電型の第1不純物領域を含む、請求項1記載の半導体装置。 - 前記半導体基板の主表面上に形成された、所定の厚さの第2導電型の第1半導体層を含み、
前記第1ロジック回路領域および前記環状領域は、前記第1半導体層に形成され、
前記分離領域は、前記第1ロジック回路領域に位置する前記第1半導体層の部分と前記環状領域に位置する前記第1半導体層の部分との間に位置する前記第1半導体層の部分の表面から、前記半導体基板の前記第1導電型の領域にわたり形成されたトレンチ分離部を含む、請求項1記載の半導体装置。 - 前記環状領域は、
前記第2抵抗として、前記環状領域の内側から外側へ向かってスパイラル状に形成されたポリシリコン抵抗と、
前記ポリシリコン抵抗を覆うように、それぞれ周方向に沿って形成された複数の環状のフィールドプレートと
を含む、請求項1〜6のいずれかに記載の半導体装置。 - 環状の前記フィールドプレートは、周方向に断続的に形成された、請求項7記載の半導体装置。
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JP5610930B2 (ja) | 2010-08-30 | 2014-10-22 | 三菱電機株式会社 | 半導体装置 |
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US9373619B2 (en) * | 2011-08-01 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage resistor with high voltage junction termination |
WO2013039135A1 (ja) * | 2011-09-16 | 2013-03-21 | 富士電機株式会社 | 高耐圧半導体装置 |
WO2013069408A1 (ja) | 2011-11-11 | 2013-05-16 | 富士電機株式会社 | 半導体装置 |
JP5983122B2 (ja) * | 2012-07-17 | 2016-08-31 | 富士通セミコンダクター株式会社 | 半導体装置 |
TWI472035B (zh) * | 2012-07-30 | 2015-02-01 | Macronix Int Co Ltd | 場元件 |
CN103579298B (zh) * | 2012-08-09 | 2016-04-27 | 旺宏电子股份有限公司 | 高压半导体元件的场元件 |
JP6132539B2 (ja) * | 2012-12-13 | 2017-05-24 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6009341B2 (ja) * | 2012-12-13 | 2016-10-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
TWI506762B (zh) * | 2013-03-13 | 2015-11-01 | Macronix Int Co Ltd | 半導體結構及其製造方法 |
CN105247675B (zh) * | 2013-05-29 | 2019-11-15 | 三菱电机株式会社 | 半导体装置 |
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CN109428535B (zh) * | 2017-08-30 | 2023-04-21 | 精工爱普生株式会社 | 电机驱动电路、半导体装置以及电子设备 |
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