TWI795713B - 高壓半導體元件 - Google Patents

高壓半導體元件 Download PDF

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TWI795713B
TWI795713B TW110101789A TW110101789A TWI795713B TW I795713 B TWI795713 B TW I795713B TW 110101789 A TW110101789 A TW 110101789A TW 110101789 A TW110101789 A TW 110101789A TW I795713 B TWI795713 B TW I795713B
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well layer
drain
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黃宗義
黃鐙聖
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通嘉科技股份有限公司
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Abstract

本發明實施例提供一種高壓元件。一半導體基底為一第一導電型。一深井層為一第二導電型，與該第一導電型相反。該深井層形成於該半導體基底上，具有一表面。一場隔絕層形成於該表面，分隔一源主動區以及一汲主動區。一源金屬內連接接觸該源主動區中的該表面，形成一歐姆接觸，作為該高壓元件之一源極。一汲金屬內連接接觸該汲主動區中的該表面，作為該高壓元件之一汲極。一第一井層為該第一導電型，形成於該表面，且位於該源主動區與該場隔絕層之間。一底層為該第一導電型，形成於該深井層之一底部。一控制閘形成於該場隔絕層上，作為該高壓元件之一閘極。該控制閘之一閘電壓可控制該深井層所提供之一導電通道，其電連接該汲極至該源極。

Description

高壓半導體元件
本發明大致係關於高壓半導體元件，尤指汲極可以耐受高電壓的半導體元件。
為了實現速運算跟產品輕巧，半導體產品往往製作的越來越精密，也越來越脆弱。然而，半導體產品往往需要針對不同的應用系統，在其輸出入埠上，必須面對有特別的環境，而產生有一些特別的需求。舉例來說，在高功率的應用下，有些電子產品操作於有開關、電感與電容的連接網路，進而要求電子產品的輸出入埠需要能夠承受電壓電流的瞬間大變化。這些規格上的需求，都會帶給半導體元件設計者新的挑戰。
本發明實施例提供一種高壓元件。一半導體基底為一第一導電型。一深井層為一第二導電型，與該第一導電型相反。該深井層形成於該半導體基底上，具有一表面。一場隔絕層形成於該表面，分隔一源主動區以及一汲主動區。一源金屬內連接接觸該源主動區中的該表面，形成一歐姆接觸，作為該高壓元件之一源極。一汲金屬內連接接觸該汲主動區中的該表面，作為該高壓元件之一汲極。一第一井層為該第一導電型，形成於該表面，且位於該源主動區與該場隔絕層之間。一底層為該第一導電型， 形成於該深井層之一底部。一控制閘形成於該場隔絕層上，作為該高壓元件之一閘極。該控制閘之一閘電壓可控制該深井層所提供之一導電通道，其電連接該汲極至該源極。
100:高壓元件
102:P型基底
104:P型磊晶層
106、206:N型深井層
108a、108b:P型井層
110:N型井層
111a、111b:P型重摻雜層
112a、112b、112c:場隔絕層
113a、113b:N型重摻雜層
114:閘氧化層
116:多晶矽層
118:接觸栓塞
120a、120b、120c、120d:金屬線
200a、200b、200c、200d、200e:高壓元件
202:P型基底
204:P型磊晶層
206:N型深井層
208a、208b:P型井層
210:N型井層
211a、211b:P型重摻雜層
212a、212b、212c:場隔絕層
213a、213b:N型重摻雜層
218:接觸栓塞
220a、220b、220c、220d:金屬線
222、222a、222b、222c:P型底層
226a、226b:P型輕摻雜層
BTP、BBT:邊緣
CR:距離
DRAIN:汲極
DS:蕭基特接觸
FS:表面
GATE:閘極
OD1、OD2、OD3、OD4:主動區
PTH:導電通道
SOURCE:源極
SUB:基底電極
第1圖顯示高壓元件100。
第2A圖顯示依據本發明所實施的高壓元件200a。
第2B圖顯示高壓元件200a中，N型重摻雜層213b到N型井層210之間，由N型深井層206所提供的導電通道PTH。
第2C圖顯示高壓元件200a的符號示意圖。
第3圖與第4圖為依據本發明所實施的二高壓元件。
第5A圖顯示依據本發明所實施的高壓元件200d。
第5B圖顯示高壓元件200d的符號示意圖。
第6圖為依據本發明所實施的高壓元件200e。
在本說明書中，有一些相同的符號，其表示具有相同或是類似之結構、功能、原理的元件，且為業界具有一般知識能力者可以依據本說明書之教導而推知。為說明書之簡潔度考量，相同之符號的元件將不再重述。
第1圖為高壓元件100，等效於形成於P型基底(p-type substrate)102上的N型接面場效電晶體(junction field effect transistor，JFET)。高壓元件100具有汲極DRAIN、源極SOURCE、以及閘極GATE。高 壓元件100的汲極DRAIN可以耐受高電壓的輸入。
P型基底102上形成有P型磊晶層(epitaxy layer)104。P型磊晶層104之表面上形成有許多場隔絕層(field isolation layer)112a、112b、112c。每個場隔絕層用來區隔了不同的主動區。主動區中可以形成金氧半電晶體的閘結構與源汲重摻雜層。場隔絕層112a將隔絕了P型重摻雜層111a與N型重摻雜層113a，兩者分別做為P型井層108b與N型井層110的歐姆接觸。場隔絕層112b介於P型重摻雜層111b與N型重摻雜層113a之間。場隔絕層112c則介於閘氧化層114與N型重摻雜層113b之間。P型重摻雜層111b作為P型井層108a的歐姆接觸，而N型重摻雜層113b作為N型深井層(deep N well)106的歐姆接觸。N型深井層106可以由局部的P型磊晶層104被輕摻雜而形成，N型深井層106的底部可以選擇性地接觸到P型基底102。
閘氧化層114與隔絕層112c上形成有多晶矽層116，透過接觸栓塞(contact plug)118連接到圖案化的金屬線120c與P型重摻雜層111b。金屬線120c與接觸栓塞(contact plug)118作為高壓元件100閘極GATE，也同時作為金屬內連接(metal interconnection)，可以電性連接到其他的電子電路。類似的，金屬線120b與相關的接觸栓塞118作為高壓元件100源極SOURCE，而金屬線120d與相關的接觸栓塞118作為高壓元件100汲極DRAIN。金屬線120a與相關之接觸栓塞118作為基底電極SUB，提供基底102的電性接觸。在一實施例中，基底電極SUB電性連接到一接地電源。
閘極GATE對源極SOURCE的閘源(gate-to-source)電壓，可以控制P型井層108a與N型深井層106之間的PN接面上的空乏區(depletion region)的寬度，進而控制N型重摻雜層113b到N型井層110之間，由N型深 井層106所提供的導電路徑。位於閘氧化層114與隔絕層112c上的多晶矽層116可以做為場板(field plate)，可以微調N型深井層106中的電場分佈，進而增強汲源(drain-to-source)崩潰電壓(breakdown voltage)。
第1圖中的高壓元件100有一個問題：閘極漏電流(gate leakage)。在電路操作時，一旦源極SOURCE瞬間低於閘極GATE的電壓時，P型井層108a與N型深井層106之間的PN接面就呈現順向偏壓，導致閘極GATE流到源極SOURCE的瞬間大電流，這稱為閘極漏電流。閘極漏電流在一些電路應用上，是不被允許的。
第2A圖為依據本發明所實施的高壓元件200a。高壓元件200a具有汲極DRAIN、源極SOURCE、以及閘極GATE，其與第1圖之高壓元件100有相同或是相似之處，可以參考相關於高壓元件100之說明而得知，不再多述。
N型深井層206的表面FS上形成有場隔絕層212a、212b、212c。場隔絕層212a分隔了主動區OD4與OD3，場隔絕層212b分隔了主動區OD3與OD2，場隔絕層212c分隔了主動區OD2與OD1。在第2A圖中，每個主動區中僅有形成一個重摻雜層，但本發明不限於此。在其他實施例中，主動區中可以形成有數個重摻雜層以及/或閘氧化層。
主動區OD4中形成有P型重摻雜層211b，位於P型井層208b中，用來提供P型井層208b、P型磊晶層204與P型基底202，到金屬線220a之間的電性連接。金屬線220a與相關之接觸栓塞218作為基底電極SUB，提供基底202的電性接觸，可以電性連接到一接地電源。
主動區OD3中形成有N型重摻雜層213a，作為N型井層210 與接觸栓塞218之間的一歐姆接觸；主動區OD2形成有P型重摻雜層211a，作為P型井層208a與接觸栓塞218之間的一歐姆接觸。P型井層208a部分與場隔絕層212c重疊，部分位於場隔絕層212c與N型重摻雜層213a(N型井層210的歐姆接觸)之間。N型重摻雜層213a與P型重摻雜層211a，透過相關之接觸栓塞218，彼此短路，且電性連接到金屬線220b。金屬線220b與相關之接觸栓塞218可以視為一源金屬內連接(source metal interconnection)，作為高壓元件200a的源極SOURCE。源金屬內連接等同於接觸了P型井層208a的表面。主動區OD3可以視為一源主動區。在一實施例中，場隔絕層212b可以省略，而P型重摻雜層211a與N型重摻雜層213a位於同一個源主動區之內。
主動區OD1中形成有N型重摻雜層213b，作為N型深井層206的歐姆接觸，透過相關之接觸栓塞218，電性連接到金屬線220d。金屬線220d可以視為一汲金屬內連接，接觸主動區OD1中N型重摻雜層213b的表面，作為高壓元件200a的汲極DRAIN。主動區OD1可以視為一汲主動區。
多晶矽層216作為一控制閘，形成於場隔絕層212c上，透過相關之接觸栓塞218，電性連接到金屬線220c，其可以視為閘金屬內連接，作為高壓元件200a的閘極GATE。在一實施例中，多晶矽層216下方沒有第1圖中薄的閘氧化層114。如此，場隔絕層212c就可以耐受比較大的閘極GATE對源極SOURCE之閘源電壓。
在N型深井層206的底部埋藏而形成有P型底層(P bottom layer)222。如同第2A圖的剖面圖所示，P型底層222可以部份坐落於N型深井層206中，且部分坐落於P型基底202中。如同第2A圖所示，P型底層222至少部分與場隔絕層212c重疊，且與主動區OD1之間維持了距離CR。換言 之，P型底層222不與主動區OD1重疊。P型底層222也部分地與P型井層208a重疊。製作上，舉例來說，可以在P型磊晶層204形成之前，先在P型基底202上之預設區域摻雜P型摻雜物，然後在P型磊晶層204形成後，經過熱處理擴散先前的P型摻雜物，而形成P型底層222。
第2B圖顯示高壓元件200a中，N型重摻雜層213b到N型井層210之間，由N型深井層206所提供的導電通道PTH，電性連接汲極DRAIN至源極SOURCE。第2B圖同時也顯示了兩個空乏區的邊緣BTP與BBT，大致上決定了導電通道PTH的寬度。當邊緣BTP與BBT接觸時，表示通道夾止(pinch off)或是電流截止(cut off)。閘極GATE上的電壓，可以控制邊緣BTP的位置。舉例來說，當閘極GATE對源極SOURCE之閘源電壓越負時，場隔絕層212c下的空乏區就越寬，邊緣BTP越靠近邊緣BBT。P型井層208a可以降低N型深井層206之表面電場(reduce surface field)，提高汲源崩潰電壓。P型底層222的位置、範圍、濃度，也可以用來決定邊緣BBT的位置，調整通道夾止(pinch off)電壓。換言之，P型底層222也可以增加高壓元件200a的汲源崩潰電壓。
第2C圖顯示高壓元件200a的符號示意圖，其表示為一空乏式(depletion mode)金氧半(metal-oxide-semiconductor，MOS)電晶體。閘極GATE位於場隔絕層212c上，可以控制位於N型深井層206的導電通道PTH。當閘源電壓為0V時，導電通道PTH可以導通電流，所以高壓元件200a是一空乏式金氧半電晶體電晶體，只是高壓元件200a採用厚的場隔絕層212c當作閘氧化層。
高壓元件200a不會有第1圖之高壓元件100的閘極漏電流問 題。P型井層208a透過金屬線220b與相關之接觸栓塞218，電性連接到N型井層210。P型井層208a與N型井層210都是電性連接到源極SOURCE。因此，P型井層208a與N型井層210都是等電位。高壓元件200a的閘極GATE位於場隔絕層212c上，沒有短路到P型井層208a，也就是沒有電性連接到P型井層208a。因此，就算高壓元件200a的閘極GATE的電壓高於高壓元件200a的源極SOURCE，只要場隔絕層212c沒有崩潰，就不會有從閘極GATE到源極SOURCE的漏電流發生。
第3圖為依據本發明所實施的高壓元件200b，其與高壓元件100與200a有相同或是相似之處，可以參考先前之說明而得知，不再多述。與第2A圖之高壓元件200a中單一P型底層222不同的，高壓元件200b具有數個P型底層222a、222b、222c，每個P型底層至少部分與場隔絕層212c重疊，且不與主動區OD1重疊。只要妥善設計P型底層的數量、位置，可以增加高壓元件200b的汲源崩潰電壓。
第4圖為依據本發明所實施的高壓元件200c，其與高壓元件100、200a與200b有相同或是相似之處，可以參考先前之說明而得知，不再多述。與第2A圖之高壓元件200a中短路到N型井層210之P型井層208a不同的，第4圖中的P型井層208a是電浮動，P型井層208a沒有電性接觸任何金屬內連接，就算是有電性接觸到金屬內連接，這金屬內連接也沒有提供固定電壓給P型井層208a。雖然第4圖中P型井層208a是電浮動，P型井層208a可能因為P型井層208a與N型深井層206之間非常少的PN接面漏電流，而大約穩定在跟N型深井層206大約相同的電壓。第4圖中電浮動的P型井層208a也可以降低N型深井層206之表面電場。
第5A圖為依據本發明所實施的高壓元件200d，其與高壓元件100、200a、200b與200c有相同或是相似之處，可以參考先前之說明而得知，不再多述。第2A圖之高壓元件200a中汲極DRAIN透過N型重摻雜層213b電性短路到N型深井層206。而與第2A圖不同的，第5A圖中的高壓元件200d中，金屬線220d下方的接觸栓塞218(也就是汲金屬內連接的一部分)直接接觸主動區OD1中N型深井層206的表面，形成蕭基特接觸DS。蕭基特接觸DS被P型輕摻雜層226a與226b所包圍，而P型輕摻雜層226a與226b也電性短路到汲極DRAIN。在一未顯示之上視圖中，P型輕摻雜層226a與226b可以是位於同一P型輕摻雜區。第5B圖顯示高壓元件200d的符號示意圖，其中包含有一空乏式金氧半電晶體以及由蕭基特接面DS所構成的蕭基特二極體。蕭基特接面DS可以防止逆電流從源極SOURCE流到汲極DRAIN，並提供一個比較低的順向電壓。P型輕摻雜層226a與226b可以增加蕭基特二極體的崩潰電壓。
第6圖為依據本發明所實施的高壓元件200e，其具有數個P型底層222a、222b、222c、電浮動之P型井層208a、以及蕭基特接面DS。高壓元件200e與高壓元件100、200a、200b、200c與200d有相同或是相似之處，可以參考先前之說明而得知，不再多述。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
200a:高壓元件
202:P型基底
204:P型磊晶層
206:N型深井層
208a、208b:P型井層
210:N型井層
211a、211b:P型重摻雜層
212a、212b、212c:場隔絕層
213a、213b:N型重摻雜層
218:接觸栓塞
220a、220b、220c、220d:金屬線
222:P型底層
CR:距離
DRAIN:汲極
FS:表面
GATE:閘極
OD1、OD2、OD3、OD4:主動區
SOURCE:源極
SUB:基底電極

Claims (10)

  1. 一種高壓元件，包含有：
    一半導體基底(substrate)，為一第一導電型；
    一深井層(deep well layer)，為一第二導電型，與該第一導電型相反，該深井層形成於該半導體基底上，具有一表面；
    一場隔絕層(field isolation layer)，形成於該表面，分隔一源主動區(source active region)以及一汲主動區；
    一源金屬內連接(source metal interconnection)，接觸該源主動區中的該表面，形成一歐姆接觸，作為該高壓元件之一源極；
    一汲金屬內連接，接觸該汲主動區中的該表面，作為該高壓元件之一汲極；
    一第一井層(first well layer)，為該第一導電型，形成於該表面，且位於該歐姆接觸與該場隔絕層之間；
    一底層(bottom layer)，為該第一導電型，形成於該深井層之一底部；以及
    一控制閘，形成於該場隔絕層上，作為該高壓元件之一閘極；
    其中，該控制閘之一閘電壓可控制該深井層所提供之一導電通道，其電連接該汲極至該源極。
  2. 如申請專利範圍第1項之該高壓元件，其中，該底層至少部分與該場隔絕層重疊，且不與該汲主動區重疊。
  3. 如申請專利範圍第2項之該高壓元件，其中，該底層至少部分與該第一井層重疊。
  4. 如申請專利範圍第1項之該高壓元件，其中，該源金屬內連接接觸該第一井層。
  5. 如申請專利範圍第1項之該高壓元件，其中，該第一井層為電浮動。
  6. 如申請專利範圍第1項之該高壓元件，其中，該高壓元件包含有數個底層，每一底層均至少部分與該場隔絕層重疊，且不與該汲主動區重疊。
  7. 如申請專利範圍第1項之該高壓元件，其中，該汲金屬內連接與該深井層之該表面接觸，形成一蕭基特接觸(schottky contact)。
  8. 如申請專利範圍第1項之該高壓元件，另包含有：
    至少二第一摻雜層，為該第一導電型，形成於該表面，且包圍該蕭基特接觸。
  9. 如申請專利範圍第1項之該高壓元件，另包含有：
    一汲摻雜層(drain doped layer)，為該第二導電型，位於該汲主動區內，形成於該表面，用以提供該汲金屬內連接與該深井層之間的一歐姆接觸(ohmic contact)。
  10. 一種高壓元件，包含有：
    一半導體基底，為一第一導電型；
    一深井層，為一第二導電型，與該第一導電型相反，該深井層形成於該半導體基底上，具有一表面，提供一導電通道，連接該高壓元件之一汲極與一源極；
    一場隔絕層(field isolation layer)，形成於該表面；
    一第一井層(first well layer)，為該第一導電型，形成於該表面，且至少部分重疊於該場隔絕層；
    一底層(bottom layer)，為該第一導電型，形成於該深井層之一底部，且至少部分重疊於該場隔絕層；以及
    一控制閘，形成於該場隔絕層上，作為該高壓元件之一閘極，用以控制該導電通道；
    其中，該控制閘並不電連接至該第一井層。
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Citations (2)

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TWI387106B (zh) * 2008-10-16 2013-02-21 Vanguard Int Semiconduct Corp 閘極絕緣雙接面電晶體（ｉｇｂｔ）靜電放電防護元件
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JP3173268B2 (ja) * 1994-01-06 2001-06-04 富士電機株式会社 Ｍｉｓ電界効果トランジスタを備えた半導体装置
US6489653B2 (en) * 1999-12-27 2002-12-03 Kabushiki Kaisha Toshiba Lateral high-breakdown-voltage transistor
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TWI387106B (zh) * 2008-10-16 2013-02-21 Vanguard Int Semiconduct Corp 閘極絕緣雙接面電晶體（ｉｇｂｔ）靜電放電防護元件
TWI636573B (zh) * 2016-12-16 2018-09-21 通嘉科技股份有限公司 具有高壓啟動單元的垂直雙擴散金氧半功率元件

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