JP4675534B2 - デュアル・ダマシン処理中に下層の配線層を保護する方法 - Google Patents

デュアル・ダマシン処理中に下層の配線層を保護する方法 Download PDF

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Publication number
JP4675534B2
JP4675534B2 JP2001506606A JP2001506606A JP4675534B2 JP 4675534 B2 JP4675534 B2 JP 4675534B2 JP 2001506606 A JP2001506606 A JP 2001506606A JP 2001506606 A JP2001506606 A JP 2001506606A JP 4675534 B2 JP4675534 B2 JP 4675534B2
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Japan
Prior art keywords
photoresist
dielectric
mask
trench
photoresist material
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Expired - Fee Related
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JP2001506606A
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English (en)
Japanese (ja)
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JP2003528442A (ja
JP2003528442A5 (enExample
Inventor
フセイン，マカレム・エイ
マイヤーズ，アラン・エム
レッキア，チャールズ・エイチ
シヴァクマー，サム
カンダス，アンジェロ・ダブリュ
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Intel Corp
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Intel Corp
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Publication date
Priority claimed from US09/345,586 external-priority patent/US6406995B1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of JP2003528442A publication Critical patent/JP2003528442A/ja
Publication of JP2003528442A5 publication Critical patent/JP2003528442A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2001506606A 1999-06-30 2000-06-05 デュアル・ダマシン処理中に下層の配線層を保護する方法 Expired - Fee Related JP4675534B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/345,586 US6406995B1 (en) 1998-09-30 1999-06-30 Pattern-sensitive deposition for damascene processing
US09/345,586 1999-06-30
PCT/US2000/040108 WO2001001480A1 (en) 1999-06-30 2000-06-05 Method of protecting an underlying wiring layer during dual damascene processing

Publications (3)

Publication Number Publication Date
JP2003528442A JP2003528442A (ja) 2003-09-24
JP2003528442A5 JP2003528442A5 (enExample) 2007-07-26
JP4675534B2 true JP4675534B2 (ja) 2011-04-27

Family

ID=23355627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001506606A Expired - Fee Related JP4675534B2 (ja) 1999-06-30 2000-06-05 デュアル・ダマシン処理中に下層の配線層を保護する方法

Country Status (8)

Country Link
EP (1) EP1192656A1 (enExample)
JP (1) JP4675534B2 (enExample)
KR (1) KR100452418B1 (enExample)
AU (1) AU5790800A (enExample)
HK (1) HK1042380A1 (enExample)
IL (2) IL147301A0 (enExample)
TW (1) TW531789B (enExample)
WO (1) WO2001001480A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW519725B (en) * 2000-06-30 2003-02-01 Infineon Technologies Corp Via first dual damascene process for copper metallization
US6576550B1 (en) 2000-06-30 2003-06-10 Infineon, Ag ‘Via first’ dual damascene process for copper metallization
KR100393974B1 (ko) * 2001-01-12 2003-08-06 주식회사 하이닉스반도체 듀얼 다마신 형성 방법
KR100419901B1 (ko) * 2001-06-05 2004-03-04 삼성전자주식회사 듀얼 다마신 배선을 가지는 반도체 소자의 제조방법
JP2002373936A (ja) * 2001-06-14 2002-12-26 Nec Corp デュアルダマシン法による配線形成方法
KR100545220B1 (ko) 2003-12-31 2006-01-24 동부아남반도체 주식회사 반도체 소자의 듀얼 다마신 배선 형성 방법
JP5096669B2 (ja) 2005-07-06 2012-12-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
KR100691105B1 (ko) * 2005-09-28 2007-03-09 동부일렉트로닉스 주식회사 듀얼 다마신 공정을 이용한 구리 배선 형성 방법
JP2009016596A (ja) * 2007-07-05 2009-01-22 Elpida Memory Inc 半導体装置及び半導体装置の製造方法
JP4891296B2 (ja) * 2008-07-03 2012-03-07 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP5641681B2 (ja) * 2008-08-08 2014-12-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置の製造方法
JP6737991B2 (ja) * 2015-04-12 2020-08-12 東京エレクトロン株式会社 オープンフィーチャ内に誘電体分離構造を作成するサブトラクティブ法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0609496B1 (de) * 1993-01-19 1998-04-15 Siemens Aktiengesellschaft Verfahren zur Herstellung einer Kontakte und diese verbindende Leiterbahnen umfassenden Metallisierungsebene
US5705430A (en) * 1995-06-07 1998-01-06 Advanced Micro Devices, Inc. Dual damascene with a sacrificial via fill
JPH08335634A (ja) * 1995-06-08 1996-12-17 Toshiba Corp 半導体装置の製造方法
US5702982A (en) * 1996-03-28 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
JPH10223755A (ja) * 1997-02-03 1998-08-21 Hitachi Ltd 半導体集積回路装置の製造方法
JP3183238B2 (ja) * 1997-11-27 2001-07-09 日本電気株式会社 半導体装置の製造方法
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
US6387819B1 (en) * 1998-04-29 2002-05-14 Applied Materials, Inc. Method for etching low K dielectric layers
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP3734390B2 (ja) * 1998-10-21 2006-01-11 東京応化工業株式会社 埋込材およびこの埋込材を用いた配線形成方法
JP2000150644A (ja) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp 半導体デバイスの製造方法
JP4082812B2 (ja) * 1998-12-21 2008-04-30 富士通株式会社 半導体装置の製造方法および多層配線構造の形成方法

Also Published As

Publication number Publication date
EP1192656A1 (en) 2002-04-03
IL147301A0 (en) 2002-08-14
HK1042380A1 (zh) 2002-08-09
KR100452418B1 (ko) 2004-10-12
IL147301A (en) 2006-07-05
AU5790800A (en) 2001-01-31
JP2003528442A (ja) 2003-09-24
WO2001001480A1 (en) 2001-01-04
TW531789B (en) 2003-05-11
KR20020020921A (ko) 2002-03-16

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