JP2003528442A5 - - Google Patents
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- Publication number
- JP2003528442A5 JP2003528442A5 JP2001506606A JP2001506606A JP2003528442A5 JP 2003528442 A5 JP2003528442 A5 JP 2003528442A5 JP 2001506606 A JP2001506606 A JP 2001506606A JP 2001506606 A JP2001506606 A JP 2001506606A JP 2003528442 A5 JP2003528442 A5 JP 2003528442A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/345,586 US6406995B1 (en) | 1998-09-30 | 1999-06-30 | Pattern-sensitive deposition for damascene processing |
| US09/345,586 | 1999-06-30 | ||
| PCT/US2000/040108 WO2001001480A1 (en) | 1999-06-30 | 2000-06-05 | Method of protecting an underlying wiring layer during dual damascene processing |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003528442A JP2003528442A (ja) | 2003-09-24 |
| JP2003528442A5 true JP2003528442A5 (enExample) | 2007-07-26 |
| JP4675534B2 JP4675534B2 (ja) | 2011-04-27 |
Family
ID=23355627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001506606A Expired - Fee Related JP4675534B2 (ja) | 1999-06-30 | 2000-06-05 | デュアル・ダマシン処理中に下層の配線層を保護する方法 |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP1192656A1 (enExample) |
| JP (1) | JP4675534B2 (enExample) |
| KR (1) | KR100452418B1 (enExample) |
| AU (1) | AU5790800A (enExample) |
| HK (1) | HK1042380A1 (enExample) |
| IL (2) | IL147301A0 (enExample) |
| TW (1) | TW531789B (enExample) |
| WO (1) | WO2001001480A1 (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW519725B (en) * | 2000-06-30 | 2003-02-01 | Infineon Technologies Corp | Via first dual damascene process for copper metallization |
| US6576550B1 (en) | 2000-06-30 | 2003-06-10 | Infineon, Ag | ‘Via first’ dual damascene process for copper metallization |
| KR100393974B1 (ko) * | 2001-01-12 | 2003-08-06 | 주식회사 하이닉스반도체 | 듀얼 다마신 형성 방법 |
| KR100419901B1 (ko) * | 2001-06-05 | 2004-03-04 | 삼성전자주식회사 | 듀얼 다마신 배선을 가지는 반도체 소자의 제조방법 |
| JP2002373936A (ja) * | 2001-06-14 | 2002-12-26 | Nec Corp | デュアルダマシン法による配線形成方法 |
| KR100545220B1 (ko) | 2003-12-31 | 2006-01-24 | 동부아남반도체 주식회사 | 반도체 소자의 듀얼 다마신 배선 형성 방법 |
| JP5096669B2 (ja) | 2005-07-06 | 2012-12-12 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
| KR100691105B1 (ko) * | 2005-09-28 | 2007-03-09 | 동부일렉트로닉스 주식회사 | 듀얼 다마신 공정을 이용한 구리 배선 형성 방법 |
| JP2009016596A (ja) * | 2007-07-05 | 2009-01-22 | Elpida Memory Inc | 半導体装置及び半導体装置の製造方法 |
| JP4891296B2 (ja) * | 2008-07-03 | 2012-03-07 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
| JP5641681B2 (ja) * | 2008-08-08 | 2014-12-17 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | 半導体装置の製造方法 |
| JP6737991B2 (ja) * | 2015-04-12 | 2020-08-12 | 東京エレクトロン株式会社 | オープンフィーチャ内に誘電体分離構造を作成するサブトラクティブ法 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0609496B1 (de) * | 1993-01-19 | 1998-04-15 | Siemens Aktiengesellschaft | Verfahren zur Herstellung einer Kontakte und diese verbindende Leiterbahnen umfassenden Metallisierungsebene |
| US5705430A (en) * | 1995-06-07 | 1998-01-06 | Advanced Micro Devices, Inc. | Dual damascene with a sacrificial via fill |
| JPH08335634A (ja) * | 1995-06-08 | 1996-12-17 | Toshiba Corp | 半導体装置の製造方法 |
| US5702982A (en) * | 1996-03-28 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits |
| JPH10223755A (ja) * | 1997-02-03 | 1998-08-21 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| JP3183238B2 (ja) * | 1997-11-27 | 2001-07-09 | 日本電気株式会社 | 半導体装置の製造方法 |
| US6057239A (en) * | 1997-12-17 | 2000-05-02 | Advanced Micro Devices, Inc. | Dual damascene process using sacrificial spin-on materials |
| US6387819B1 (en) * | 1998-04-29 | 2002-05-14 | Applied Materials, Inc. | Method for etching low K dielectric layers |
| US6245662B1 (en) * | 1998-07-23 | 2001-06-12 | Applied Materials, Inc. | Method of producing an interconnect structure for an integrated circuit |
| JP3734390B2 (ja) * | 1998-10-21 | 2006-01-11 | 東京応化工業株式会社 | 埋込材およびこの埋込材を用いた配線形成方法 |
| JP2000150644A (ja) * | 1998-11-10 | 2000-05-30 | Mitsubishi Electric Corp | 半導体デバイスの製造方法 |
| JP4082812B2 (ja) * | 1998-12-21 | 2008-04-30 | 富士通株式会社 | 半導体装置の製造方法および多層配線構造の形成方法 |
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2000
- 2000-06-05 AU AU57908/00A patent/AU5790800A/en not_active Abandoned
- 2000-06-05 JP JP2001506606A patent/JP4675534B2/ja not_active Expired - Fee Related
- 2000-06-05 KR KR10-2001-7016608A patent/KR100452418B1/ko not_active Expired - Fee Related
- 2000-06-05 HK HK02104146.3A patent/HK1042380A1/zh unknown
- 2000-06-05 EP EP00943434A patent/EP1192656A1/en not_active Ceased
- 2000-06-05 WO PCT/US2000/040108 patent/WO2001001480A1/en not_active Ceased
- 2000-06-05 IL IL14730100A patent/IL147301A0/xx active IP Right Grant
- 2000-08-19 TW TW089112999A patent/TW531789B/zh not_active IP Right Cessation
-
2001
- 2001-12-25 IL IL147301A patent/IL147301A/en not_active IP Right Cessation