IL147301A0 - Method of projecting an underlying wiring layer during dual damascene processing - Google Patents

Method of projecting an underlying wiring layer during dual damascene processing

Info

Publication number
IL147301A0
IL147301A0 IL14730100A IL14730100A IL147301A0 IL 147301 A0 IL147301 A0 IL 147301A0 IL 14730100 A IL14730100 A IL 14730100A IL 14730100 A IL14730100 A IL 14730100A IL 147301 A0 IL147301 A0 IL 147301A0
Authority
IL
Israel
Prior art keywords
projecting
wiring layer
layer during
dual damascene
damascene processing
Prior art date
Application number
IL14730100A
Other languages
English (en)
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/345,586 external-priority patent/US6406995B1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of IL147301A0 publication Critical patent/IL147301A0/xx

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
IL14730100A 1999-06-30 2000-06-05 Method of projecting an underlying wiring layer during dual damascene processing IL147301A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/345,586 US6406995B1 (en) 1998-09-30 1999-06-30 Pattern-sensitive deposition for damascene processing
PCT/US2000/040108 WO2001001480A1 (en) 1999-06-30 2000-06-05 Method of protecting an underlying wiring layer during dual damascene processing

Publications (1)

Publication Number Publication Date
IL147301A0 true IL147301A0 (en) 2002-08-14

Family

ID=23355627

Family Applications (2)

Application Number Title Priority Date Filing Date
IL14730100A IL147301A0 (en) 1999-06-30 2000-06-05 Method of projecting an underlying wiring layer during dual damascene processing
IL147301A IL147301A (en) 1999-06-30 2001-12-25 Method of projecting an underlying wiring layer during dual damascene processing

Family Applications After (1)

Application Number Title Priority Date Filing Date
IL147301A IL147301A (en) 1999-06-30 2001-12-25 Method of projecting an underlying wiring layer during dual damascene processing

Country Status (8)

Country Link
EP (1) EP1192656A1 (enExample)
JP (1) JP4675534B2 (enExample)
KR (1) KR100452418B1 (enExample)
AU (1) AU5790800A (enExample)
HK (1) HK1042380A1 (enExample)
IL (2) IL147301A0 (enExample)
TW (1) TW531789B (enExample)
WO (1) WO2001001480A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6576550B1 (en) 2000-06-30 2003-06-10 Infineon, Ag ‘Via first’ dual damascene process for copper metallization
WO2002003457A2 (en) * 2000-06-30 2002-01-10 Infineon Technologies Ag Via first dual damascene process for copper metallization
KR100393974B1 (ko) * 2001-01-12 2003-08-06 주식회사 하이닉스반도체 듀얼 다마신 형성 방법
KR100419901B1 (ko) * 2001-06-05 2004-03-04 삼성전자주식회사 듀얼 다마신 배선을 가지는 반도체 소자의 제조방법
JP2002373936A (ja) * 2001-06-14 2002-12-26 Nec Corp デュアルダマシン法による配線形成方法
KR100545220B1 (ko) 2003-12-31 2006-01-24 동부아남반도체 주식회사 반도체 소자의 듀얼 다마신 배선 형성 방법
JP5096669B2 (ja) 2005-07-06 2012-12-12 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
KR100691105B1 (ko) * 2005-09-28 2007-03-09 동부일렉트로닉스 주식회사 듀얼 다마신 공정을 이용한 구리 배선 형성 방법
JP2009016596A (ja) * 2007-07-05 2009-01-22 Elpida Memory Inc 半導体装置及び半導体装置の製造方法
JP4891296B2 (ja) * 2008-07-03 2012-03-07 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP5641681B2 (ja) * 2008-08-08 2014-12-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置の製造方法
KR102344900B1 (ko) * 2015-04-12 2021-12-28 도쿄엘렉트론가부시키가이샤 오픈 피처 내에 유전체 절연 구조를 생성하기 위한 차감 방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59308407D1 (de) * 1993-01-19 1998-05-20 Siemens Ag Verfahren zur Herstellung einer Kontakte und diese verbindende Leiterbahnen umfassenden Metallisierungsebene
US5705430A (en) * 1995-06-07 1998-01-06 Advanced Micro Devices, Inc. Dual damascene with a sacrificial via fill
JPH08335634A (ja) * 1995-06-08 1996-12-17 Toshiba Corp 半導体装置の製造方法
US5702982A (en) * 1996-03-28 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
JPH10223755A (ja) * 1997-02-03 1998-08-21 Hitachi Ltd 半導体集積回路装置の製造方法
JP3183238B2 (ja) * 1997-11-27 2001-07-09 日本電気株式会社 半導体装置の製造方法
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
US6387819B1 (en) * 1998-04-29 2002-05-14 Applied Materials, Inc. Method for etching low K dielectric layers
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP3734390B2 (ja) * 1998-10-21 2006-01-11 東京応化工業株式会社 埋込材およびこの埋込材を用いた配線形成方法
JP2000150644A (ja) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp 半導体デバイスの製造方法
JP4082812B2 (ja) * 1998-12-21 2008-04-30 富士通株式会社 半導体装置の製造方法および多層配線構造の形成方法

Also Published As

Publication number Publication date
IL147301A (en) 2006-07-05
TW531789B (en) 2003-05-11
KR100452418B1 (ko) 2004-10-12
HK1042380A1 (zh) 2002-08-09
AU5790800A (en) 2001-01-31
KR20020020921A (ko) 2002-03-16
JP4675534B2 (ja) 2011-04-27
EP1192656A1 (en) 2002-04-03
WO2001001480A1 (en) 2001-01-04
JP2003528442A (ja) 2003-09-24

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KB20 Patent renewed for 20 years