AU5790800A - Method of protecting an underlying wiring layer during dual damascene processing - Google Patents

Method of protecting an underlying wiring layer during dual damascene processing

Info

Publication number
AU5790800A
AU5790800A AU57908/00A AU5790800A AU5790800A AU 5790800 A AU5790800 A AU 5790800A AU 57908/00 A AU57908/00 A AU 57908/00A AU 5790800 A AU5790800 A AU 5790800A AU 5790800 A AU5790800 A AU 5790800A
Authority
AU
Australia
Prior art keywords
protecting
wiring layer
layer during
dual damascene
damascene processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU57908/00A
Inventor
Makarem A. Hussein
Angelo W. Kandas
Alan M Myers
Charles H. Recchia
Sam Sivakumar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/345,586 external-priority patent/US6406995B1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU5790800A publication Critical patent/AU5790800A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AU57908/00A 1999-06-30 2000-06-05 Method of protecting an underlying wiring layer during dual damascene processing Abandoned AU5790800A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/345,586 US6406995B1 (en) 1998-09-30 1999-06-30 Pattern-sensitive deposition for damascene processing
US09345586 1999-06-30
PCT/US2000/040108 WO2001001480A1 (en) 1999-06-30 2000-06-05 Method of protecting an underlying wiring layer during dual damascene processing

Publications (1)

Publication Number Publication Date
AU5790800A true AU5790800A (en) 2001-01-31

Family

ID=23355627

Family Applications (1)

Application Number Title Priority Date Filing Date
AU57908/00A Abandoned AU5790800A (en) 1999-06-30 2000-06-05 Method of protecting an underlying wiring layer during dual damascene processing

Country Status (8)

Country Link
EP (1) EP1192656A1 (en)
JP (1) JP4675534B2 (en)
KR (1) KR100452418B1 (en)
AU (1) AU5790800A (en)
HK (1) HK1042380A1 (en)
IL (2) IL147301A0 (en)
TW (1) TW531789B (en)
WO (1) WO2001001480A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474605B1 (en) * 2000-06-30 2005-03-10 인터내셔널 비지네스 머신즈 코포레이션 Via first dual damascene process for copper metallization
US6576550B1 (en) 2000-06-30 2003-06-10 Infineon, Ag ‘Via first’ dual damascene process for copper metallization
KR100393974B1 (en) * 2001-01-12 2003-08-06 주식회사 하이닉스반도체 Forming Method for Dual Damascene
KR100419901B1 (en) * 2001-06-05 2004-03-04 삼성전자주식회사 Method of fabricating semiconductor device having dual damascene interconnection
JP2002373936A (en) * 2001-06-14 2002-12-26 Nec Corp Wiring formation method by dual damascene method
KR100545220B1 (en) 2003-12-31 2006-01-24 동부아남반도체 주식회사 Method for fabricating the dual damascene interconnection in semiconductor device
JP5096669B2 (en) 2005-07-06 2012-12-12 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
KR100691105B1 (en) * 2005-09-28 2007-03-09 동부일렉트로닉스 주식회사 Method of forming copper interconnection using dual damascene process
JP2009016596A (en) * 2007-07-05 2009-01-22 Elpida Memory Inc Semiconductor device and its manufacturing method
JP4891296B2 (en) * 2008-07-03 2012-03-07 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device
JP5641681B2 (en) * 2008-08-08 2014-12-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Manufacturing method of semiconductor device
US10170354B2 (en) * 2015-04-12 2019-01-01 Tokyo Electron Limited Subtractive methods for creating dielectric isolation structures within open features

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59308407D1 (en) * 1993-01-19 1998-05-20 Siemens Ag Method for producing a contact and a metallization level comprising these interconnects
US5705430A (en) * 1995-06-07 1998-01-06 Advanced Micro Devices, Inc. Dual damascene with a sacrificial via fill
JPH08335634A (en) * 1995-06-08 1996-12-17 Toshiba Corp Manufacturing method for semiconductor device
US5702982A (en) * 1996-03-28 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
JPH10223755A (en) * 1997-02-03 1998-08-21 Hitachi Ltd Manufacture of semiconductor integrated circuit device
JP3183238B2 (en) * 1997-11-27 2001-07-09 日本電気株式会社 Method for manufacturing semiconductor device
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
US6387819B1 (en) * 1998-04-29 2002-05-14 Applied Materials, Inc. Method for etching low K dielectric layers
US6245662B1 (en) * 1998-07-23 2001-06-12 Applied Materials, Inc. Method of producing an interconnect structure for an integrated circuit
JP3734390B2 (en) * 1998-10-21 2006-01-11 東京応化工業株式会社 Embedding material and wiring forming method using the embedding material
JP2000150644A (en) * 1998-11-10 2000-05-30 Mitsubishi Electric Corp Manufacture of semiconductor device
JP4082812B2 (en) * 1998-12-21 2008-04-30 富士通株式会社 Semiconductor device manufacturing method and multilayer wiring structure forming method

Also Published As

Publication number Publication date
IL147301A0 (en) 2002-08-14
WO2001001480A1 (en) 2001-01-04
TW531789B (en) 2003-05-11
HK1042380A1 (en) 2002-08-09
IL147301A (en) 2006-07-05
KR20020020921A (en) 2002-03-16
KR100452418B1 (en) 2004-10-12
JP2003528442A (en) 2003-09-24
JP4675534B2 (en) 2011-04-27
EP1192656A1 (en) 2002-04-03

Similar Documents

Publication Publication Date Title
EP1109208A3 (en) Method for the formation of semiconductor layer
AU4677399A (en) Inhibitors of H+K+-ATPase
SG90747A1 (en) Method of pre-cleaning dielectric layers of substrates
AU2252301A (en) Semiconductor processing equipment
AU7477900A (en) Semiconductor processing equipment having tiled ceramic liner
AU4244000A (en) Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering
AU2814000A (en) A method of processing a polymer layer
AU4003400A (en) Apparatus and method for manufacture of an endocardial lead
AU4846400A (en) Wiring system and method therefor
AU7861800A (en) Method for determining total cost of ownership
AU2915501A (en) Oxide layer method
AU1740900A (en) Method of inhibiting angiogenesis
AU5543600A (en) Method of modifying an integrated circuit
AU1986800A (en) Method for protecting an integrated circuit chip
AU5790800A (en) Method of protecting an underlying wiring layer during dual damascene processing
AU5561999A (en) Methods for reducing atherosclerotic plaques
AU5860200A (en) Method for dp-conversion of an existing semi-submersible rig
AU2027101A (en) Thinner for rinsing photoresist and method of treating photoresist layer
AU2416101A (en) Antenna arrangement and method for side-lobe suppression
AU5118500A (en) Method for determination of surface texture
WO2002059944A8 (en) Optimized liners for dual damascene metal wiring
AU5099598A (en) Method for preparing vias for subsequent metallization
AU2683400A (en) Method of treating an insulating layer
AU2376001A (en) Method for the manufacture of olefins
EP1091396A3 (en) Plasma processing method

Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase