KR20020020921A - Method of protecting an underlying wiring layer during dual damascene processing - Google Patents

Abstract

The present invention provides a method of forming a sacrificial material 160 in a via 150 that penetrates through the dielectric material 130 up to the masking material 120 over the conductive material 110 and has physical properties that generally do not respond to light. A wiring forming method comprising a. The method also includes forming trenches 180 in the dielectric material over vias 150 and removing sacrificial material 160 from the vias.

Description

How to protect the bottom wiring layer during a dual damascene process {METHOD OF PROTECTING AN UNDERLYING WIRING LAYER DURING DUAL DAMASCENE PROCESSING}

The present invention was filed on September 30, 1998 under the name of “A pattern-Sensitive Deposition for Damascens Processing” by Peter K. Moon, Makarem A. Hussein, Alan Myers, Charles Recchia, Sam Sivakumar, and Angelo Kandas. Some ongoing applications of pending application number 09 / 164,508.

Currently, integrated circuits use conductive wires to connect elements on a chip or to transmit and receive signals to and from the chip. Common wiring types include aluminum alloy wiring and copper wiring.

An important difference between this aluminum and copper wiring is the oxidation rate of the metal. Pure aluminum is oxidized to aluminum oxide in the presence of oxygen. However, since aluminum has a very low diffusion coefficient with respect to oxygen present in aluminum oxide, pure metal Al under the aluminum oxide layer does not react with oxygen as long as aluminum oxide is formed. The reaction between aluminum and oxygen is referred to as a self-limiting oxidation reaction.

Copper oxidation, on the other hand, is not a self limiting oxidation reaction. In the presence of oxygen, pure copper continues to oxidize until almost all copper is oxidized to copper oxide. Thus, once the copper wiring is formed and patterned, an additional process of forming a protective film usually made of silicon nitride (Si ₃ N ₄ ) is performed to protect the exposed wiring material from air or moisture.

One of the processes used to form wiring, especially copper wiring, is a damascene process. In this damascene process, trenches are formed in the dielectric and filled with copper to form wiring. In the dielectric under the trench there is a via made of a conductive material, which connects the lower integrated circuit element or the lower interconnects and the wiring.

Photoresists are generally formed over dielectrics and used to pattern wiring vias, trenches, or both in the dielectric. After patterning, this photoresist is removed. This photoresist is generally removed by oxygen plasma (oxygen ashing). Oxygen used in the oxygen ashing method may react with the lower copper interconnect to oxidize the interconnect. Thus, in the damascene process, a thin, hard mask or barrier layer, typically made of Si ₃ N _4, is formed directly on the copper wiring to prevent the copper from oxidizing during the oxygen ashing process that is performed when the subsequent wiring is formed. In general, this rigid mask layer of Si ₃ N ₄ is very thin, for example approximately 10% of the thickness of the dielectric layer. So, for example, when forming vias penetrating the oxide film using an etching process, the etching must be stopped in the lower Si ₃ N ₄ in the prior art. Then, when forming trenches in the dielectric over these vias, the prior art should not etch away the Si ₃ N ₄ exposed by the vias. Etching vias and trenches and protecting Si ₃ N ₄ requires a high selectivity etchant that does not etch thin Si ₃ N ₄ layers.

Thus, there is a need for methods that do not require unrealistic etch selectivity, particularly those useful for damascene processes.

TECHNICAL FIELD The present invention relates to an integrated circuit manufacturing method, and more particularly, to a method for patterning interconnections on an integrated circuit.

1 is a cross-sectional view of an integrated circuit board in accordance with one embodiment of the present invention, showing wiring insulated with a dielectric material, a hard mask directly over the wiring, and a dielectric material over the rigid mask.

2 illustrates the substrate of FIG. 1 after performing an additional process of patterning a photoresist mask over a dielectric material in accordance with one embodiment of the present invention.

3 illustrates the substrate of FIG. 1 after an additional process of forming vias through the dielectric material and stopping in the rigid mask layer in accordance with an embodiment of the present invention.

4 illustrates the substrate of FIG. 1 after performing an additional process of cleaning the substrate to remove the photoresist mask in accordance with an embodiment of the present invention.

FIG. 5 illustrates the substrate of FIG. 1 after laminating sacrificial material and leaving sacrificial material that does not respond to light in accordance with an embodiment of the present invention.

6 illustrates the substrate of FIG. 1 after cleaning the substrate surface and leaving sacrificial material in the vias in accordance with an embodiment of the present invention.

7 illustrates the substrate of FIG. 1 after performing an additional process of patterning a mask material over a dielectric material in accordance with an embodiment of the present invention.

8 illustrates the substrate of FIG. 1 after performing an additional process of opening a trench in a dielectric material in accordance with an embodiment of the present invention.

9 illustrates the substrate of FIG. 1 after an additional process of removing the trench pattern material and sacrificial material in accordance with an embodiment of the present invention.

FIG. 10 illustrates the substrate of FIG. 1 after performing a further process of extending vias through the hard mask material to expose copper interconnects in accordance with an embodiment of the present invention.

FIG. 10 illustrates the substrate of FIG. 1 after an additional process of laminating copper material in the openings of trenches and vias and planarizing the copper and dielectric material in accordance with an embodiment of the present invention.

A method of forming the wiring will be described. As a feature of this method, a sacrificial material of generally non-responsive nature is formed in vias that penetrate through the dielectric material up to the masking material on the conductive material. A trench is formed in the dielectric material over the vias and the sacrificial material of the vias is removed.

The present invention relates to one feature of a method for forming a wiring. The present invention is useful in one embodiment to protect the lower wiring during the formation of subsequent wiring or upper wiring. The present invention also relieves the burden of unrealistic etching characteristics between the dielectric material and the rigid lower mask formed to protect the lower interconnects, such as copper interconnects, which can be used as part of the damascene process. The present invention relieves the aforementioned burden by forming a second mask material or sacrificial material in the vias on the rigid mask. In this way, the photoresist material used to pattern, for example vias or trenches in the dielectric, can be removed without fear of oxidizing the underlying copper interconnects.

1-11 illustrate a dual damascene process for forming wiring over a lower copper interconnect. A typical integrated circuit may have, for example, four or five wiring layers or lines insulated from each other by dielectric material. 1 to 11 show, for example, a method of forming a second wiring layer or wiring formed on and electrically connected to the first wiring layer or wiring. It is apparent that the method of the present invention can be applied to each wiring layer or wiring.

1 is a partial cross-sectional view of an integrated circuit board or wafer having a first copper interconnect 110 formed in dielectric material 100. The copper wiring 110 is connected to, for example, a lower element formed in and on the semiconductor substrate. The dielectric material is, for example, SiO ₂ formed by tetraethyl orthosilicate (TEOS) or plasma enhanced chemical vapor deposition (PECVD). In this embodiment, dielectric layer 100 and copper interconnect 110 are planarized.

The first mask layer 120 is present on the planarized dielectric layer 100 / copper wiring 110. In one aspect, the first mask layer 120 functions as a mask or a barrier that prevents oxidation of the copper wiring 110. In one embodiment of the present invention, the first mask layer 120 is a Si ₃ N ₄ or Si _X N _Y O _Z layer. It is apparent that other dielectric materials such as organic polymers can be used as the first mask layer 120.

In the example where the first mask is Si ₃ N ₄ or Si _X N _Y O _Z , for example, by chemical vapor deposition (CVD), the material is laminated to a suitable thickness of approximately 100 nm, and the copper wiring in the subsequent etching process. Protect 110. Si ₃ N ₄ or Si _X N _Y O _Z generally has chemical properties, including dielectric constants, which tend to increase the capacitance between the wiring and the integrated circuit. Thus, the copper wiring 110 is generally protected by lamination only in a small amount, for example, a thickness of 100 nm or less, but does not unacceptably increase the capacitance between the wirings. In the remainder of the specification, an example in which the first mask layer 120 is a Si ₃ N ₄ material will be described.

The dielectric layer 130 is present on the first mask layer 120. Dielectric layer 130 is, for example, SiO ₂ formed by a thickness of approximately 1,000 nm, for example, by TEOS or PECVD. The thickness of dielectric layer 130 depends in part on the size characteristics and scaling considerations of the device. Once dielectric layer 130 is formed by stacking, this material 130 is planarized, for example by chemical-mechanical polish.

Next, as shown in FIG. 2, the via pattern or the second mask layer 140 is patterned on the dielectric layer 130. The second mask layer 140 is a photo-imageable material, for example a photoresist. For example, a positive photoresist is generally spin coated onto the surface of the dielectric layer 130 of the wafer. The mask or reticle is then used to expose a portion of the photoresist to the light source. In this case, the reticle or mask determines a region corresponding to the vias or openings 145 on the dielectric layer 130. Once the photoresist material of the second mask layer 140 is exposed to light, the exposed material is removed in a conventional manner, for example using a developer, and the substrate is baked to cure the remaining photoresist. . This process leaves a second mask layer 140 of photoresist having an opening 145 over dielectric layer 130.

As shown in FIG. 3, once the second mask layer 140 is patterned, a via 150 penetrating through the dielectric layer 130 is formed using an etchant. The etchant is selected such that it hardly reacts with the lower first mask layer 120 or does not disrupt the first mask layer 120. In the case of Si ₃ N ₄ first mask layer SiO ₂ dielectric layer 130 existing on the (120), for example, Si ₃ to N ₄ without substantially etching an appropriate etchant for selectively etching the SiO ₂ is C ₄ F ₈ chemistry. The purpose of the via etching is to etch the vias through the dielectric layer 130 but stop the etching before the etching through the first mask layer 120 of Si ₃ N ₄ is performed. Since a portion of the Si ₃ N ₄ material constituting the first mask layer 120 may be etched away during the via etching operation, a sufficient amount of Si ₃ N ₄ material may be used to protect the copper interconnect 110. The etching process must be continued to be present on the copper wiring 110.

After the via 150 penetrates through the dielectric layer 130, the via pattern or the second mask layer 140 is removed from the surface of the dielectric layer 130. In this embodiment where via pattern or second mask layer 140 is a photoresist, this material may be removed with conventional oxygen plasma (eg, oxygen ashing). At this time, the remaining particles may be removed using a known wet clean step.

Next, as shown in FIG. 5, sacrificial material 160 is formed in vias 150 of dielectric layer 130. In an embodiment of the invention, the sacrificial material 160 is a material capable of uniformly filling small vias (eg, having a diameter of less than 0.25 μm). In this embodiment, the sacrificial material 160 is also typically made unresponsive or unresponsive to developing processes such as photoreaction. In other words, once this sacrificial material 160 is formed in the via 150, much of this sacrificial material 160 should not alter its chemical properties. For example, this material is a material that does not dissolve in a photoresist developer even when exposed to light, particularly light having a wavelength region of ultraviolet (UV) light.

One suitable material for the sacrificial material 160 is a heat-treated positive photoresist. FIG. 5 shows an example in which a photoresist, such as a conventional positive photoresist, is spin coated on the surface of the dielectric layer 130 and fills the via 150. Positive photoresists are generally sensitive to light exposure, as already described with reference to FIG. 2. After coating the photoresist material, the substrate is heated to cure this photoresist material. Heat treatment is performed at about 150-200 degreeC, for example. In addition to curing the photoresist, the heat treatment in this embodiment generally performs a second function of preventing the photoresist material from reacting to light, even when exposed to light, for example ultraviolet light.

Instead of the thermally treated photoresist, other suitable materials that can be used as the sacrificial material 160 include photoresist materials that do not include pigmented photoresistors or photo-active compounds, ie photoresist resins. Can be mentioned. One of the dye-containing photoresists is a dye material having absorbance. When exposed to light, such as ultraviolet light, the pigments in the dye-containing photoresist (most of the dielectric layer 100 / copper interconnect 110) are mostly in the region above or near the top of the sacrificial material 160 in the vias 150. By absorbing light, the physical properties of most of the dye-containing photoresist are prevented from changing in response to light, leaving a plug of photoresist material in the via 150 even after the exposure process. One type of dye-containing photoresist can usually be purchased from Tokyo Ohka Kogyo, Japan. After spin-coating this material on the surface of the dielectric layer 130, it can be cured by conventional heat treatment. Similar processes can be applied to photoresist resins (ie, resins that do not contain photoactive compounds) such as DP-resin, which are usually available from Tokyo Ohka Kogyo. If the photoactive compound is not present, the physical properties of the compound, which is an etch-resistant plug material of the via 150, do not change even after exposure to light such as ultraviolet rays.

FIG. 6 shows a substrate after a process of controlling and removing the sacrificial material 160 from the surface of the dielectric layer 130. In embodiments of the invention where the sacrificial material 160 is a photoresist, controlling and removing the photoresist material from the surface of the dielectric layer 130 may be realized using known oxygen plasma (eg, oxygen ashing). have. The end point in the removal process is the surface of the dielectric layer 130. Thereafter, a known selective wet cleaning process may be performed to remove any remaining fine particles.

In an embodiment of the present invention, the sacrificial material 160 is used to protect the first mask layer 120 in a subsequent etching process, for example, to form a subsequent trench trench pattern. Thus there is no need to completely fill the via 150 with sacrificial material 160. In addition, sacrificial material 160 should not interfere with subsequent etching, such as subsequent trench etching, which etches dielectric layer 130 around via 150. Thus, in some cases, it may be desirable to remove some of the sacrificial material 160 in the vias 150.

In this embodiment where the sacrificial material 160 is a photoresist, after reaching the end point of the surface of the dielectric layer 130, the portion of the photoresist material in the via 150 is continuously etched (ie, over ashed) with oxygen plasma. Can be removed. FIG. 6 is a diagram illustrating steps incorporating the method of the present invention, showing a portion of sacrificial material 160 has been removed from via 150. It is also apparent in other embodiments that the sacrificial material 160 may be patterned to not completely fill the vias 150. In this embodiment, there is no need to remove a portion of the sacrificial material 160, for example in an over ashing process.

FIG. 12 graphically depicts a controlled height from the surface of dielectric layer 130 in vias having a depth of 1300 nm. The height of the sacrificial material 160 relative to the surface of the dielectric layer 130 is proportional to the ashing time in seconds after passing through the endpoint (ie, past the surface of the dielectric layer 130). In this embodiment, photoresist is used as photoresist material 160 and the substrate is exposed to mixed oxygen / nitrogen plasma at low temperature conditions (about 200 ° C.) in photoresist removal equipment. Low temperatures during ashing help to control the photoresist removal process. Thus, in accordance with an embodiment of the present invention, sacrificial material 160 is formed to have a controlled height (eg, a predetermined height above first mask layer 120) within via 150 based on over ashing. Can be. In this way, for example, compared to the results obtained when the developing process is made longer, the height change of the sacrificial material 160 in the vias 150 can be greatly reduced within and between wafers.

A sacrificial material 160 is formed in the via 150 as desired, and then a pattern mask or third mask layer 170 is patterned on the dielectric layer 130 to pattern the trench in the oxide 130. FIG. 7 shows a patterned mask or third mask layer 170 over dielectric layer 130 except for exposed region 175 to pattern trenches. Suitable pattern or third mask layer 170 is, for example, a photoresist formed as described above with respect to second mask layer 140. In this embodiment, the third mask layer 170 is a positive photoresist, which is coated on the dielectric layer 130. The mask or reticle is then used to expose a portion of the photoresist to the light source. The exposed portion defines a trench over the via 150. This exposed portion includes an area over the sacrificial material 160. Since the sacrificial material 160 generally does not respond to light, the sacrificial material 160 is, for example, unaffected by exposure to a UV light source. The sacrificial material 160 does not react because it does not contain any photoactive compound or removes photoreactivity through heat treatment or the like. Alternatively, a photoresist (eg, a dye containing photoresist) containing a light absorbing dye may be used as the sacrificial material 160. In this embodiment, when the sacrificial material 160 is exposed to light to define an etch pattern for forming subsequent trenches in the dielectric layer 130, the light absorbing dye absorbs all UV light that strikes the sacrificial material 160. Absorb. Thus, a trench patterning process for patterning a photoresist mask over dielectric layer 130 does not significantly affect sacrificial material 160.

After forming the third mask layer 170, the trench 180 is formed in the dielectric layer 130. The trench 180 is patterned to a depth suitable for conductive wiring. In an embodiment of the invention, for example, trench 180 has a depth of approximately 500 nm. In addition, the exact dimensions of the trench 180 vary depending on the size of the integrated circuit to be formed. In the case where the dielectric layer 130 is made of SiO ₂ , an etchant suitable for forming the trench 180 is, for example, a C ₄ F ₈ / O ₂ / Ar etchant.

By forming the sacrificial material 160 in the via 150, the underlying first mask layer 120 is protected during etching the trench as previously described. Consideration of the selectivity between the dielectric layer 130 and the first mask layer 120 if there is no risk of removing the underlying first mask layer 120 (such as, for example, the Si ₃ N ₄ layer). An appropriate etchant may be selected for trench etching without. Thus, an appropriate etchant may be selected based on other parameters such as, for example, etching speed, verticality of etching.

9 shows the substrate after a subsequent process of removing the third mask layer 170 is performed. 9 also shows the substrate after the process of removing the sacrificial material 160 and exposing the underlying first mask layer 120.

As the sacrificial material 160 is formed in the via 150, the conventional concern that the lower first mask layer 120 is removed during the trench etching process is alleviated. Thus, in an embodiment of the present invention, sacrificial material 160 having a low etch rate during the trench is selected. In the embodiment of the present invention, the sacrificial material 160 and the third mask layer 170 are both photoresists and may be removed at the same time. Similarly, since the third mask layer 170 is also a photoresist, both the third mask layer 170 and the sacrificial material 160 can be removed by, for example, oxygen ashing. Since the first mask layer 120 is present over the copper wiring in the via 150, the copper wiring 110 is not oxidized by the oxygen present when performing the oxygen ashing process.

After removing the sacrificial material 160 from the via 150, a subsequent etching process may be performed to remove the exposed Si ₃ N ₄ material, which is the first mask layer 120. When the first mask layer 120 exposed in the via 150 is removed, the lower copper wiring 110 is exposed as shown in FIG. 10. Suitable etchant for removing the first mask layer 120 of Si ₃ N ₄ is, for example, a CF ₄ / O ₂ etchant.

FIG. 11 shows the substrate after exposing the underlying copper interconnect 110 and following a subsequent process of laminating copper material 190 in trench 180 and via 150. Lamination precedes conventional damascene processes. After laminating the copper material 190 to the vias 150, the substrate can be planarized and conventional wiring formed using conventional damascene processing techniques. The process described with reference to FIGS. 1-11 can then be repeated to form subsequent wiring layers.

In the foregoing detailed description, the invention has been described with reference to specific embodiments. However, it will be apparent that various modifications and changes can be made without departing from the broad spirit and scope of the invention as set forth in the claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (20)

Forming a sacrificial material in the via that penetrates the dielectric material up to the masking material over the conductive material, the chemical material having a chemical property that generally does not respond to light, Forming a trench in the dielectric material over the via, and Removing the sacrificial material from the vias How to include. In claim 1, The sacrificial material forming step, Laminating a sacrificial material comprising a photosensitive material, and Leaving a portion of the sacrificial material that does not respond to light Containing Way. In claim 2, The sacrificial material comprises a photoresist, and leaving the sacrificial material comprises exposing the photoresist to heat. In claim 2, The sacrificial material is a photoresist, The sacrificial material forming step, Coating the photoresist on a surface of the dielectric material, Exposing the substrate to a temperature capable of leaving a portion of the photoresist that is not responsive to light, and Removing the photoresist from the surface of the dielectric material Containing Way. In claim 4, The substrate exposing step has a temperature that is capable of curing a portion of the photoresist material. In claim 5, Removing the photoresist material from the surface of the dielectric, Exposing the photoresist material to a plasma or gas of one of oxygen, hydrogen, oxygen / nitrogen, and hydrogen / nitrogen. In claim 1, The sacrificial material is a photoresist comprising a light absorbing material, The method, Depositing a photosensitive masking material on the surface of the dielectric material prior to forming the trench, and Exposing the photoresist masking material to a light source to expose a trench region of the photomasking material. Containing additional Way. In claim 1, The sacrificial material forming step, Coating the sacrificial material over the surface of the dielectric material, and Removing a portion of the sacrificial material from the via such that the sacrificial material present in the via on the masking material has a predetermined height Containing Way. In claim 8, And removing the sacrificial material comprises etching for a predetermined time after elapse of time to remove the sacrificial material from the surface of the dielectric material. As a method of forming a second wiring in an integrated circuit device including a first wiring, Forming a sacrificial material having physical properties that generally do not respond to light in vias through the dielectric material up to the masking material over the first interconnect, Forming a trench in the dielectric material over the vias, Removing the sacrificial material from the vias, Extending the via to penetrate the masking material, and Depositing a conductive material on the vias How to include. In claim 10, And forming the sacrificial material comprises leaving a portion of the sacrificial material that does not respond to light. In claim 11, The sacrificial material comprises a photoresist, and leaving the sacrificial material comprises exposing the photoresist to heat. In claim 10, The sacrificial material is a photoresist, The sacrificial material forming step, Coating the photoresist on a surface of the dielectric material, Exposing the substrate to a temperature capable of leaving a portion of the photoresist that is not responsive to light, and Removing the photoresist from the surface of the dielectric material Containing Way. In claim 13, The substrate exposing step has a temperature that is capable of curing a portion of the photoresist material. The method of claim 14, Removing the photoresist material from the surface of the dielectric comprises exposing the photoresist material to a plasma or gas of one of oxygen, hydrogen, oxygen / nitrogen, and hydrogen / nitrogen. In claim 10, The sacrificial material is a photoresist comprising a light absorbing material, The method, Depositing a photosensitive masking material on the surface of the dielectric material prior to forming the trench, and Exposing the photoresist masking material to a light source to expose a trench region of the photomasking material. Containing additional Way. In claim 10, The sacrificial material forming step, Coating the sacrificial material over the surface of the dielectric material, and Removing a portion of the sacrificial material from the via such that the sacrificial material present in the via on the masking material has a predetermined height Containing Way. The method of claim 17, And removing the sacrificial material comprises etching for a predetermined time after elapse of time to remove the sacrificial material from the surface of the dielectric material. Forming vias through the dielectric material to expose the masking material over the wiring on the substrate, Forming a sacrificial material in the via, the sacrificial material having a physical property that generally does not respond to light, Forming a trench in the dielectric material over a portion of the via, Removing the sacrificial material from the vias, Extending the via to penetrate the masking material, and Depositing a conductive material in the via and the trench The damascene method comprising a. The method of claim 19, The sacrificial material forming step, Laminating the sacrificial material comprising the photosensitive material, and Leaving a portion of the sacrificial material that does not respond to light Containing Way.