KR100708422B1 - Method of in-situ etching a hard mask and a metal layer in a single etcher - Google Patents

Abstract

A method of fabricating a semiconductor wafer is disclosed, wherein an interlayer dielectric layer is formed over a semiconductor substrate, a metal layer is formed over the interlayer dielectric layer, and a hardmask material layer is formed on the surface of the metal layer, and on and within the semiconductor substrate. The active element is formed. A photoresist layer is formed, patterned, and developed on the surface of the hardmask material layer to expose portions of the layer underneath the hardmask material. The semiconductor wafer is disposed in an etching apparatus, the hardmask material layer is etched in a first process using a combination of fluorine and chlorine chemicals, and the metal layer is etched in a second process using a combination of fluorine and chlorine chemicals.

Description

METHOD OF IN-SITU ETCHING A HARD MASK AND A METAL LAYER IN A SINGLE ETCHER}

FIELD OF THE INVENTION The present invention generally relates to a method of fabricating a high density, high performance semiconductor device in which a hardmask is formed on metal layers to prevent deep-UV resist footing. More specifically, the present invention relates to a method of fabricating a high density, high performance semiconductor device using a single etching device to etch hardmask and metal layers.

US-A-5 772 906 discloses a method for manufacturing metallization on a semiconductor substrate. The method utilizes a stack of layers on a substrate, including an oxide layer on the substrate, a barrier layer over the oxide layer, a metal layer over the barrier layer, and an antireflective coating layer. A photoresist layer is then formed over the ARC and the stack is etched using two different etching chemistries. One chemical includes reverse etch rate loading inducing chemistry and the other uses natural etch rate loading inducing chemistry. By using these two etching process chemicals, it becomes possible to perform uniform etching in the same etching apparatus.
The increased demand for high performance semiconductor devices requires an increase in the density of metallization lines. One of the main needs of end users of high performance semiconductors is the increase in raw processing speed. As more transistors are mounted on the same semiconductor chip, such as a microprocessor, the speed and functionality of the semiconductor chip has the potential to increase significantly. However, by increasing the number of transistors, more silicon area is required and the transistors need to be close to each other in order to reduce the distance that electrons have to travel via metal lines from one transistor to another. However, since the metal lines are arranged closer to each other, the problem caused by the reactance between the metal wires increases. One reactance problem is crosstalk caused by the effect of induction between wires. Another reactance problem concerns RC delays that are proportional to the operating frequency of the system. Because of the criticality of dimensional control of the structural components of the semiconductor device, any factor that increases or decreases any dimension may lower the performance of the semiconductor device below the design specification. The criticality of control is becoming more and more important and will become even more important as the dimensions decrease to the sub-0.25 μm area.

Accelerated control of critical dimensions in the sub-0.5 μm region for semiconductor manufacturing has increased the semiconductor industry's interest in antireflective coatings that minimize the reflectivity of the substrate and prevent DUV resist putting. IITC 1998 Bulletin (proc. IITC 1998) IITC 98-84 to 98-86, W. W. Wei W. Lee, Qizhi He, Guoqiang Xing, Abha Singh, Eden Zielinski, Ken Brennan, Kirish Dixit Presented by Girish Dixit, Kelly Taylor, Chien-sung Iian, JD Luttmer and Bob Havemann, named "0.18µm and Sub Inorganic ARC for 0.18 μm and Sub-0.19 μm Multilevel Metal Interconnect (ARC) for Multi-Level Metallization of -0.19 μm ”describes the use of Si _x O _y N _z as an antireflective coating and also as a hardmask layer Is starting. This paper reports that Si _x O _y N _z minimizes the reflectivity of the substrate and reduces DVU resist putting.

However, the use of a hard mask material layer such as Si _x O _y N _z allows the wafer to perform two separate etching processes, one etching process for etching the hard mask material and the other etching process for etching the metal stack. I need to receive. Each individual etching process requires a different etching device. The use of separate etching devices and individual etching processes reduces throughput and adds process costs.

1A-1D show a method of manufacturing a semiconductor device that does not use a Si _x O _y N _z layer. 1A shows a partially completed portion 100 of a semiconductor device. The partially completed portion 100 of the semiconductor device represents an oxide layer 102 that can be an interlayer dielectric layer. Barrier layer 104 is formed over oxide layer 102. The barrier layer can be a layer of Ti / TiN. Metallization layer 106 is formed over barrier layer 104. The metallization layer 106 is formed of a conductive material such as aluminum. An antireflective coating material layer 108 is formed over the metallization layer 106. The antireflective coating material layer 108 is formed from a material such as Ti / TiN.

FIG. 1B illustrates a partially completed prior art semiconductor device 100 shown in FIG. 1A, wherein a photoresist layer 110 is formed on the antireflective coating material layer 108.

FIG. 1C shows the partially completed prior art semiconductor device 100 shown in FIG. 1B, wherein the photoresist layer 110 is patterned and etched down to the antireflective coating material layer 108. As indicated at 112, structures known as resist putting are formed at the interface between the photoresist layer 110 and the antireflective coating material layer 108. It is hypothesized that nitrogen in the antireflective coating material layer 108 that reacts with the photoresist layer 110 causes the formation of resist putting 112.

FIG. 1D shows the partially completed prior art semiconductor device 100 shown in FIG. 1C, with antireflective coating material layer 108, metallization layer 106, and barrier layer 104 up to oxide layer 102. Etching is shown after a series of etching processes. Note that, once the etching process is complete, such resist putting 112 prevents the formation of a vertical profile in the etched portion. Dimension 114 represents the desired dimension, dimension 116 represents the resulting dimension, and indicates that resist putting results in a relatively large reduction from desired dimension 114. From the fact that the metal line width designed for a typical process is about 0.35 μm and the spacing between metal lines is designed to be less than 0.30 μm, the criticality of dimension reduction can be recognized. Other processes will have similar dimensions and further processes will have smaller dimensions.

3 is a flow chart illustrating a prior art method of manufacturing a wafer. The manufacturing process starts at 300. The manufacturing process includes a series of processes 302 for forming active elements on a substrate in a wafer. After the active device is formed on and within the substrate, the first interlayer dielectric layer is formed on the surface of the substrate, and a metal layer (stack) including a hardmask layer is formed over the interlayer dielectric layer, as indicated by 304. As shown by 306, a photoresist layer is formed over the hard mask layer, patterned and developed to expose a portion of the hard mark layer, and as shown by 308, the wafer is placed in the first etching apparatus to be placed in the hard mask layer. Etch After the hard mask layer is etched, as indicated by 310, the wafer is placed in a second etching device to etch the metal layer. After the process in the second etching apparatus is finished, as indicated by 312, it is determined whether the just-etched metal layer is the last metal layer. If not the last metal layer, as indicated by 314, the wafer is further processed, and as shown by 304, the next metal layer is formed. This process continues at 312 until it is determined that the just completed metal layer is the last layer. Once the last layer is complete, the processing of the wafer is complete, as indicated at 316. The requirement to use two etching devices reduces throughput and increases process costs.

Accordingly, there is a need for a method of fabricating a semiconductor device that provides a method of etching both a hardmask layer and a metal layer using one etching apparatus without forming resist putting in the etched structure causing a non-vertical profile.

According to the present invention, the above and other objects and advantages are achieved by a method of manufacturing a semiconductor device which prevents the formation of resist putting.

According to an aspect of the present invention, an interlayer dielectric layer is formed over a semiconductor substrate, a metal layer is formed over the interlayer dielectric layer, and a hard mask material layer is formed on a surface of the metal layer, and active elements are formed on and in the semiconductor substrate. Is formed. A photoresist layer is formed, patterned, and developed on the surface of the hardmask material layer to expose portions of the layer underneath the hardmask material. The semiconductor wafer is disposed in an etching apparatus, the hardmask material layer is etched in the first process, and the metal layer is etched in the second process.

According to another aspect of the invention, the hardmask material layer and the metal layer are etched using a process using a combination of fluorine and chlorine chemicals.

The disclosed method provides a method of fabricating a semiconductor wafer that results in a reduction in resist putting and a method that enables etching of the hardmask material and metal layer without changing the etching apparatus.

The invention is better understood by considering the following detailed description in conjunction with the accompanying drawings. As will be readily apparent to those skilled in the art from the following description, embodiments of the present invention are presented by way of illustration only for purposes of illustration of the best mode for carrying out the invention. As will be appreciated, the invention is capable of other embodiments and its several details are capable of modification in various obvious respects, all without departing from the scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.

New features which are regarded as features of the invention are set forth in the appended claims. However, the invention itself, the preferred mode of use, further objects and advantages will be best understood by reference to the following detailed description of exemplary embodiments when read in conjunction with the accompanying drawings.

1A-1D show a prior art method of manufacturing a semiconductor device to form resist putting.

1A shows a partially completed portion of a semiconductor device manufactured according to the prior art.

1B shows a partially completed portion of the semiconductor device shown in FIG. 1A, in which a photoresist layer is formed on the surface of the semiconductor device.

FIG. 1C shows a partially completed portion of the semiconductor device shown in FIG. 1B, showing that the photoresist layer is patterned and developed to form resist putting.

FIG. 1D shows a partially completed portion of the semiconductor device shown in FIG. 1C, which shows a non-vertical etch profile and reduced diameter caused by resist putting after a series of etching processes.

2A-2D illustrate a method of fabricating a semiconductor device in accordance with the present invention that prevents the formation of resist putting.
2A shows a partially completed portion of a semiconductor device made in accordance with the present invention.

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FIG. 2B shows a partially completed portion of the semiconductor device shown in FIG. 2A, in which a photoresist layer is formed on the surface of the semiconductor device.

FIG. 2C shows a partially completed portion of the semiconductor device shown in FIG. 2B, showing that the photoresist layer is patterned and developed, and no resist putting is formed.

FIG. 2D shows a partially completed portion of the semiconductor device shown in FIG. 2C, showing the vertical etch profile provided by the present invention after a series of etching processes.

3 is a flow chart illustrating a method of manufacturing a wafer in accordance with the prior art.

4 is a flow chart illustrating a method of manufacturing a wafer in accordance with the present invention.

Now, certain embodiments of the present invention are described in detail which illustrate the best mode for carrying out the present invention currently contemplated by the inventor.

2A-2D illustrate a method of manufacturing a semiconductor device in accordance with the present invention that prevents the formation of resist putting. 2A shows a partially completed portion of semiconductor device 200. The partially completed portion 200 of this semiconductor device represents an oxide layer 202 that can be an interlayer dielectric layer. The oxide layer is typically formed from silicon dioxide (SiO ₂ ). Barrier layer 204 is formed over oxide layer 202. The barrier layer is formed from a material such as Ti / TiN. A metallization layer 206 is formed over the barrier layer 204. The metallization layer 206 is formed from a conductive material such as aluminum. Other materials that can form the metallization layer can be tungsten or doped polysilicon. An antireflective coating material layer 208 is formed over the metallization layer 206. The antireflective coating material layer 208 is formed from a material such as Ti / TiN. A hard mask layer 210 is formed over the antireflective coating material layer 208. The hard mask layer 210 is formed from a material such as TEOS (tetra-ethyl-ortho-silicate) or treated silicon oxynitride (Si _x O _y N _z ).

2B shows a partially completed semiconductor device 200 as in FIG. 2A, wherein a photoresist layer is formed over hard mask layer 210.

FIG. 2C shows a partially completed semiconductor device 200 as in FIG. 2B where photoresist layer 212 is patterned and developed to hardmask layer 210. As indicated by 214, no structure (resist putting) is formed at the interface between the photoresist layer 212 and the hard mask layer 210.

FIG. 2D shows a partially completed semiconductor device 200 as in FIG. 2C, wherein the hardmask layer 210, antireflective coating material layer 208, metallization layer 206 and barrier are formed by a series of etching processes. After etching layer 204 down to oxide layer 202. Note that, when the etching process is completed, the desired width of the etched portion indicated at 216 is not reduced. By etching the hardmask layer 210 and the metallization layer 206 in the same etching apparatus using similar chemicals, process steps and process time are saved. The hard mask layer 210 and the metallization layer 206 comprising a conductive material such as aluminum are etched using a combination of fluorine and chlorine etching chemicals.

4 is a flowchart illustrating a wafer manufacturing method according to the present invention. The manufacturing process starts at 400. This manufacturing process includes a series of processes for forming an active element on a substrate in a wafer, as shown at 402. After the active elements are formed on and within the substrate, the first interlayer dielectric layer is formed on the surface of the substrate, and a metal layer (stack) is formed over the interlayer dielectric layer, including a hardmask layer, as indicated by 404. As shown at 406, a photoresist layer is formed over the hard mask layer, patterned and developed to expose a portion of the hard mask layer, and as shown at 408, by placing the wafer in the etching apparatus, the hard mask layer and the metal layer. Etch The hard mask layer and the metal layer are etched using a combination of etching chemicals of fluorine and chlorine.

In summary, the results and advantages of the method of the present invention can be more fully understood. The method described above provides a semiconductor device manufacturing method that prevents the formation of DVU resist putting that undesirably reduces critical dimensions during subsequent etching processes in prior art semiconductor devices. In addition, the method described above provides a method of manufacturing a semiconductor device capable of etching the hard mask layer and the metal layer by a single etching device.

The description of the embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious changes or modifications are possible in light of the above teachings. The embodiments have been chosen and described in order to provide a best illustration of the principles of the invention and its practical application, to enable one skilled in the art to use the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such changes and modifications are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally and equitably entitled.

Claims (6)

As a method of manufacturing a semiconductor wafer, Forming active elements in and on a substrate of the semiconductor wafer; Forming an interlayer dielectric layer (202) on the surface of the substrate; Forming a metal layer (204, 206) on the surface of the interlayer dielectric layer (202); Forming an antireflective coating (ARC) layer (208) on the surface of the metal layer (204, 206); Forming a hardmask material layer 210 over the ARC layer 208, wherein the hardmask material comprises TEOS or silicon oxynitride; Forming a photoresist layer (212) on the hard mask material layer (210); Patterning and developing the photoresist layer (212) to expose a portion of the hardmask material layer (210) under the photoresist layer (212); Disposing the semiconductor wafer in an etching apparatus; Etching the exposed portions of the hardmask material layer (210) and the ARC (208) to expose portions of the metal layer (204, 206) under the hardmask material layer (210); And Etching the exposed portion of the metal layer (204, 206) without moving the semiconductor wafer from the etching apparatus. The method of claim 1, Etching the exposed portions of the hardmask material layer (210) by an etching process using a combination of a fluorine chemical and a chlorine chemical. The method of claim 2, Etching the exposed portion of the metal layer (204, 206) by an etching process using a combination of a fluorine chemical and a chlorine chemical. The method of claim 3, wherein Determining whether the etched metal layer is the last metal layer. The method of claim 4, wherein If the metal layer is not the last metal layer, further comprising the step of further processing the wafer. The method of claim 4, wherein If the metal layer is the last metal layer, further comprising completing the processing of the wafer.

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