KR100549272B1 - Submicron semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device using a hard mask, and more particularly, to a method of manufacturing a semiconductor device having a fine line width in a light source of the same wavelength using a hard mask.

The present invention is a method of depositing and patterning oxide, poly, and hard mask on a substrate to implement a semiconductor device having a finer line width in the same light source by using a hard mask as a mask, to expand the process, expand the versatility and increase the productivity of the line It is for maximization.

Hard Mask, KrF, ArF, Gate Electrode, Plasma Etching

Description

Submicron semiconductor device and method for manufacturing the same             

1 is a cross-sectional view of a semiconductor device patterned by depositing an oxide, poly, hard mask, and photoresist on a semiconductor substrate.

2 is a cross-sectional view of a process performed by performing an isotropic etching process on the above-described pattern.

3 is a cross-sectional view of the process after removing the photoresist.

4 is a cross-sectional view of a process after etching a poly layer using a pattern implemented on a hard mask.

5 is a cross-sectional view of a process of depositing a nitride film and forming a partition on the implemented device.

6 is a cross-sectional view of the process after removing the hard mask.

The present invention relates to a method of manufacturing a semiconductor device using a hard mask, and more particularly, to a method of manufacturing a semiconductor device having a fine line width in a light source of the same wavelength using a hard mask.

The microfabrication technology that has supported the progress of semiconductor devices is a photo lithography technique. In other words, it is no exaggeration to say that the resolution improvement of this technology is facing the future of high integration of semiconductor devices.

In general, a lithography is a patterning process, and may be divided into an optical process and an engraving process. However, in recent years, the meaning of the transfer method generally refers only to an optical process, and is further divided into optical and non-optical transfer methods according to light sources. The transfer method in the semiconductor process transmits light using a mask, or mask, serving as an original plate of a P substrate after applying a polymer material called a resistor on a substrate for the purpose of forming a circuit board on various materials on the substrate. It is a technology to form a resist pattern by developing a photoreaction after developing a photoreaction, and then imprinting a substrate by using this register as a barrier to finally implement a desired pattern.

The density of semiconductor chips has increased four times every three years.

The photoelectric method develops materials such as chemically amplified resist type (CAR) type resistors as well as advances in exposure equipment itself such as high aperture lens and hardware, namely aperture and marshall, and TLR (Tri Layer) in terms of process. Resist, Bi-Layer Resist (BLR), Top Surface Imaging (TSI), Anti Reflective Coating (ARC), and PSM (Phase Shift Mask) and OPC (Optical Proximity Correction) have been developed on the mask side.

Early exposure equipment was a contact printer where a mask was placed directly on a substrate, followed by eye contact. This technology has been further developed to increase the resolution by reducing the gap between the mask and the substrate, which is then exposed to proximity printers such as soft contact and hard contact (10 μm or less).

After that, in the early 1970s, the development of a projection type exposure apparatus using an optical system using reflection or refraction could start to apply to the development of the product of not only the resolution but also the life extension of the mask and the large size of the substrate. Later, in the mid-1970s, the era of stepper using projection optics, which made significant contributions to mass production of semiconductors and provided electricity for the development of the photoelectric method, began.

Stepper is an abbreviation of 'step and repeat' and the use of this type of exposure equipment improves not only the resolution but also the accuracy of the fitting. Initially steppers were designed with a reduced-projection exposure method with a pattern ratio of 5: 1 or 10: 1 on a substrate to a mask pattern, but the 5: 1 reduction projection method became the mainstream due to the limitation of the mask pattern and size.

Again, the 'step and scan' type scanner developed in the early 1990s was a 4: 1 reduction method, but it was an exposure device that responded to increasing chip size and increased productivity. The resolution is closely related to the wavelength of the light source. The initial exposure equipment using g-rays (λ = 436nm) was capable of a pattern of about 0.5 μm, and about 0.3 using i-rays (λ = 365nm). A pattern at the μm level was possible.

In recent years, the development of exposure equipment using KrF laser (λ = 248 nm) as a light source, the development of resistors, and the improvement of other subsidiary technologies have allowed patterns of 150 nm or less.

Currently, an ArF laser (λ = 193 nm) is used to develop a pattern of 110 nm or less. The DUV transfer method is excellent in performance such as resolution and DOF compared to i-ray, but process control is not easy. These problems can be divided into optical causes due to short wavelengths and chemical causes due to the use of chemically amplified resists. If the wavelength is shortened, the CD shake phenomenon due to the stationary wave effect and the reflection of reflected light due to the substrate phase become worse.

In implementing a semiconductor device having a fine line width that cannot be realized using existing equipment, the easiest way to solve the limitation of the photo process is to use a bias (critical dimension of the photoresist pattern during etching (DI CD). ), And the difference between the critical dimension (FI CD) value after the etch) can be referred to as a control, but even with this method, it is difficult to overcome the margin of line width gradually decreasing.

Accordingly, the present invention solves this problem by using a hard mask, and implements a method of manufacturing a semiconductor device that realizes a fine line width that cannot be realized by a light source having the same wavelength.

Although the present invention can be realized in various ways, the present invention will be described in more detail in one embodiment.

For example, in implementing a gate device having a line width of 90 nm using existing KrF equipment, the limit line width of the photo process that can be patterned is about 125 nm, which causes a problem of reducing 35 nm through an etch process.

This value is almost impossible considering the DUV photoresist PR height, and special measures (such as using an ArF scanner) should be made. That is, in the KrF process, the photoresist height must be 3000 GPa or less in consideration of DOF (depth of focus) margin, even with photoresist patterning of 125 nm.

As a result, in order to obtain a gate CD (channel length) of 90 nm, 35 nm must be reduced in the etch process. Even if it is calculated arithmetic, both sides should be cut by 17.5nm by using photoresist, which leads to selectivity problem with photoresist and thus it is impossible to obtain uniform gate device.

In order to solve this phenomenon, a hard mask is formed on the etched layer and a PR pattern is formed on the upper part of the etched layer, and a thinner than the conventional method is used to form a hard mask pattern having the same size as that of the PR pattern. Form.

In the subsequent process, the etching target layer may be etched using the hard mask pattern as a mask to form an etching target layer pattern having a predetermined size.

The hard mask process is widely used in the conventional DRAM manufacturing technology, but in a logic product employing a self aligned silicide process, a hard mask cannot be used for the salicide process on a gate device. .

Accordingly, an object of the present invention is to solve the problems of the prior art as described above, and to implement a fine line width that cannot be realized in a conventional light source by applying a hard mask process to a logic product.

The object of the present invention is to deposit and pattern the oxide (11), poly (12), hard mask (13) and photoresist (15) on the substrate (10) using a pattern embodied in the hard mask (13) A method of manufacturing a semiconductor device, characterized by etching the poly 12, is characterized in that a semiconductor device having a desired fine line width is implemented.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

1 to 6 are manufacturing process diagrams of a semiconductor device according to the present invention.

1 is a cross-sectional view patterned using a photoresist mask.

First, an oxide 11, a poly 12, a hard mask 13, and a photoresist 15 are deposited on the semiconductor substrate 10, and the photoresist 15 is patterned using a mask as shown in FIG. 1. Form.

When the photoresist 15 is patterned, the pattern is patterned to have a width of 120 nm (A) using a KrF light source.

The hard mask 13 uses PE-oxide.

An anti-reflection coating (ARC) 14 may be further deposited on the hard mask to lower the reflectance. The antireflective layer is made of an organic or inorganic arc.

2 is a process diagram in which a hard mask is etched using plasma etching.

The anti-reflective coating layer 14 and the hard mask 13 are etched using the photoresist pattern 15 as an etching mask using plasma.

The plasma etching uses SF ₆ gas, and sequentially etch the antireflective coating layer 14 and the hard mask 13 by isotropic etching.

3 is a process diagram of removing a photoresist and an antireflective coating layer by an ashing / strip process.

After plasma etching, an ashing / strip process is performed to remove the photoresist and the antireflective coating layer.

4 is a flowchart illustrating etching a gate poly using plasma etching to form a gate electrode.

In order to form the gate electrode, the poly 12 is etched through plasma etching using a hard mask film obtained after the ashing / strip process as an etch mask.

The plasma etching uses a etching gas of Cl ₂ / HBr, Cl ₂ / O _2, or HBr / O ₂ so that the selectivity with oxide is 10: 1.

The width of the gate electrode obtained by the above process is 80 nm.

FIG. 5 is a process diagram in which the barrier layer 17 is formed by etching the nitride layer by an etch back process after sequentially depositing the oxide layer 16 and the nitride layer on the substrate on which the gate electrode is formed by plasma etching.

The nitride film is SiN.

6 is a process chart with the hard mask 13 removed.

After the partition 17 is formed, the hard mask 13 and the oxide layer 16 are removed by wet etching.

The process may form a gate electrode having a line width of 90 nm using a conventional KrF light source by using a hard mask instead of a photoresist mask in implementing a gate electrode of a logic product.

It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.

Therefore, the method of manufacturing a semiconductor device using the hard mask of the present invention implements a product having a line width that can be implemented using existing equipment without additional investment by using a hard mask instead of the photoresist mask in implementing the gate electrode. In addition, the line width required for each product can be adjusted by using an etching process, which is a great advantage in the process scalability, expansion of versatility and maximization of line productivity.

Claims (12)

Forming a oxide (11) on the substrate (10); Forming a poly (12) on the oxide (11); A third process of forming a hard mask 13 on the poly 12; A fourth process of depositing and patterning a photoresist 15 on the hard mask 13; And A fifth process of forming a pattern using the patterned photoresist as an etching mask by isotropic etching using plasma and etching the poly 12 using the hard mask 13 on which the pattern is formed Method of manufacturing a semiconductor device comprising a. The method of claim 1, And depositing an anti-reflection layer to lower the reflectance on the hard mask. The method of claim 2, The antireflection layer is a method of manufacturing a semiconductor device, characterized in that consisting of an organic or inorganic arc. The method of claim 1, Patterning of the photoresist in the fourth step is a method of manufacturing a semiconductor device, characterized in that for patterning using a KrF light source. The method of claim 1, The hard mask is a manufacturing method of a semiconductor device, characterized in that the PE-oxide. delete delete delete The method of claim 8, The plasma etching is a method of manufacturing a semiconductor device, characterized in that for etching using SF ₆ gas. The method of claim 1, The etching of the poly in the fifth step is a method of manufacturing a semiconductor device, characterized in that the plasma etching. The method of claim 10, The plasma etching is a method of manufacturing a semiconductor device, characterized in that the selectivity with the oxide 10: 1 using an etching gas of Cl ₂ / HBr, Cl ₂ / O ₂ or HBr / O ₂ . delete

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