Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
  • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

Definitions

• the invention relates to integrated circuit processing and, more particularly, to the patterning of interconnections on an integrated circuit.
• Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send or receive signals external to the chip.
• Popular types of interconnection include aluminum alloy interconnections and copper interconnections.
• One process used to form interconnections, particularly copper interconnections is a damascene process.
• a trench is cut in a dielectric and filled with copper to form the interconnection.
• a via may be in the dielectric beneath the trench with a conductive material in the via to couple the interconnection to underlying integrated circuit devices or underlying interconnections .
• a photoresist is typically used over the dielectric to pattern a via or a trench or both in the dielectric for the interconnection. After patterning, the photoresist is removed. The photoresist is typically removed by an oxygen plasma (oxygen ashing) . The oxygen used in the oxygen ashing step can react with an underlying copper interconnection and oxidize the interconnection. Accordingly, damascene processes typically employ a thin hard mask or barrier layer of Si 3 N 4 directly over the copper interconnection to protect the copper from oxidation during oxygen ashing in the formation of a subsequent level interconnection. In general, the Si 3 N 4 hard mask layer is very thin, for example, roughly 10% of the thickness of the dielectric layer.
• a method of forming an interconnection is disclosed.
• a sacrificial material that comprises a property that is generally insensitive to a photo-reaction is formed in a via through a dielectric material to a masking material over a conductive material.
• a trench is formed in the dielectric material over the via and the sacrificial material is removed from the via.
• Figure 1 illustrates a cross-sectional side view of a portion of an integrated circuit substrate showing an interconnection insulated by a dielectric material, a hard mask directly overlying the interconnection and a dielectric material overlying the hard mask in accordance with an embodiment of the invention.
• Figure 2 shows the substrate of Figure 1 after the further processing step of patterning a photoresist mask over the dielectric material in accordance with an embodiment of the invention.
• Figure 3 shows the substrate of Figure 1 after the further processing step of opening a via through the dielectric material and stopping at the hard mask layer in accordance with an embodiment of the invention.
• Figure 4 shows the substrate of Figure 1 after the further processing step of cleaning the substrate to remove the photoresist mask in accordance with an embodiment of the invention .
• Figure 5 shows the substrate of Figure 1 after depositing a sacrificial material in the via in accordance with an embodiment of the invention and the step of rendering the sacrificial material insensitive to a photo-reaction.
• Figure 6 shows the substrate of Figure 1 after the cleaning the surface of the substrate and retaining sacrificial material in the via in accordance with an embodiment of the invention.
• Figure 7 shows the substrate of Figure 1 after the further processing step of patterning a masking material over the dielectric material in accordance with an embodiment of the invention.
• Figure 8 shows the substrate of Figure 1 after the further processing step of opening a trench in the dielectric material in accordance with an embodiment of the invention.
• Figure 9 shows the substrate of Figure 1 after the further processing step of removing the material patterned for the trench and the sacrificial material in accordance with an embodiment of the invention.
• Figure 10 shows the substrate of Figure 1 after the further processing step of extending the via through the hard mask material to expose the copper interconnection in accordance with an embodiment of the invention.
• Figure 10 shows the substrate of Figure 1 after the further processing step of depositing a copper material in the trench and via openings and planarizing the copper with the dielectric material in accordance with an embodiment of the invention.
• the invention relates in one aspect to a method of forming an interconnection.
• the invention is useful in one embodiment in protecting underlying interconnections during the formation of subsequent or higher level interconnections .
• the invention also alleviates the burden of unrealistic etch characteristics between a dielectric material and an underlying hard mask incorporated to protect an underlying interconnection such as copper interconnection that might be used as part of a damascene process.
• the invention alleviates this concern by incorporating a second masking material or a sacrificial material in the via over a hard mask. In this manner, photoresist material used to pattern, for example, a via or trench in a dielectric, may be removed without concern of oxidizing an underlying copper interconnection .
• Figures 1-11 illustrate a dual damascene process for forming an interconnection over an underlying copper interconnection.
• a typical integrated circuit may have, for example, four or five interconnection layers or lines each insulated form one and another by dielectric material.
• Figures 1-11 illustrate, for example, the formation of a second interconnection layer or line over and to be electrically connected to a first interconnection layer or line. It is to be appreciated that the method of the invention may be used for each interconnection layer or line.
• Figure 1 illustrates a cross-sectional side view of a portion of an integrated circuit substrate or wafer having a first copper interconnection line 110 formed in dielectric material 100. Copper interconnection line 110 is, for example, coupled to an underlying device or devices formed in and on a semiconductor substrate.
• the dielectric material is, for example, Si ⁇ 2 formed by a tetraethyl orthosilicate (TEOS) or plasma enhanced chemical vapor deposition (PECVD) source.
• TEOS tetraethyl orthosilicate
• PECVD plasma enhanced chemical vapor deposition
• dielectric layer 100 and copper interconnection 110 are planarized.
• first mask layer 120 Overlying the planarized dielectric layer 100/copper interconnection line 110 is first mask layer 120.
• First mask layer 120 serves, in one aspect, as a mask or barrier to prevent oxidation of copper interconnection line 110.
• first mask layer 120 is a layer of silicon nitride (Si 3 N 4 ) or silicon oxynitride (SiN y O z ) . It is to be appreciated that other dielectric materials, including organic polymers, may be suitable for first mask layer
• first mask layer 120 is Si 3 N 4 or Si x N Y O z
• the material is deposited, for example, by chemical vapor deposition (CVD) to a suitable thickness of approximately 100 nm to mask copper interconnection line 110 during subsequent etching steps .
• Si 3 N 4 and Si x N Y O z generally have chemical properties, including dielectric constants, that tend to increase the capacitance between interconnection lines and integrated circuits. Accordingly, a thin amount, e.g., less than or equal to 100 nm, is generally deposited to protect copper interconnection line 110 but not to unacceptably increase the capacitance between interconnection lines.
• first mask layer 120 of Si 3 N 4 material will be described.
• Dielectric layer 130 is, for example, a TEOS or PECVD formed Si0 2 deposited to a thickness of approximately 1,000 nm. The thickness of dielectric layer 130 will depend, in part, on size characteristics and scaling considerations for the device. Once dielectric layer 130 is deposited and formed, the material is planarized for example with a chemical- mechanical polish.
• Second mask layer 140 is, for example, a photo-imageable material such as a photoresist.
• a positive photoresist for example, is spun onto the surface of dielectric layer 130 generally across the wafer.
• a mask or reticle is then used to expose a portion of the photoresist to a light source. In this case, the reticle or mask defines an area for via or opening 145 over dielectric layer 130.
• the exposed material is removed in a conventional manner such as for example, by a developer, and the substrate is baked to harden the remaining photoresist. The process leaves second mask layer 140 of photoresist having an opening 145 over dielectric layer 130.
• an etchant is used to open via 150 through dielectric layer 130.
• An etchant is chosen that does not substantially react or disrupt underlying first mask layer 120.
• a suitable etchant to selectively etch Si0 2 without substantially etching Si 3 N 4 is, for example, a C 4 F 8 etch chemistry.
• One objective of the via etch is to etch the via through dielectric layer 130 and stop the etching prior to etching through Si 3 N 4 first mask layer 120. It is to be appreciated that some of the Si 3 N 4 material of first mask layer 120 may be etched away during the via etch, however, the etch should be monitored so that enough Si 3 N 4 material remains overlying and protecting copper interconnection line 110.
• via pattern or second mask layer 140 is removed from the surface of dielectric layer 130.
• the material may be removed through a conventional oxygen plasma (e.g., oxygen ashing) .
• a wet clean step as known in the art may also be used to remove any residual particles.
• sacrificial material 160 is introduced over dielectric layer 130 and in via 150.
• sacrificial material 160 is a material that is capable of uniformly filling small vias (e.g., via having diameter less than 0.25 microns) .
• sacrificial material 160 is also either generally insensitive to or capable of being made generally insensitive to a development step such as a photoreaction.
• a significant portion of sacrificial material 160 should not change its chemical properties.
• One example is a material that is insoluble in photoresist developer upon exposure to light, particularly light having a wavelength in the ultraviolet (UV) range.
• One suitable material for sacrificial material 160 is heat-treated positive photoresist.
• Figure 5 shows an example where photoresist, such as conventional positive photoresist, is spun-coated on the surface of dielectric layer 130 and fills via 150.
• Positive photoresist is generally sensitive to light exposure, as described above with reference to Figure 2.
• the substrate is heated to cure the photoresist material.
• the heat treatment is, for example, on the order of 150-200°C.
• the heat treatment performs a second function in this embodiment, in that it generally renders the photoresist material insensitive to a photoreaction in the presence of light exposure, e.g., UV light exposure.
• sacrificial material 160 include dyed photoresist or photoresist material with no photo-active compound, i.e., photoresist resin.
• One suitable dyed photoresist is a dye material with light-absorbing properties. Upon exposure to light, including UV light, the dye in the dyed photoresist material will absorb a majority of the light in a region near the superior or top portion of sacrificial material 160 in via 150 (relative to dielectric layer 100/copper interconnection line 110) to inhibit a photo-reactive change of the physical property of the majority of the dyed photoresist and thereby rendering a plug of photoresist material in via 150 after the exposure step.
• One type of dyed photoresist is commercially available from Tokyo Ohka Kogyo of Japan.
• the material may be spun on the surface of dielectric layer 130 and cured by a conventional heat treatment.
• a similar process may be utilized for photoresist resin (i.e., without a photo-active compound), such as DP-Resin, commercially available from Tokyo Ohka Kogyo. Absent a photo-active compound, subsequent exposure to light, including UV light, will not change the physical properties of the compound as an etch-resistant plug material of via 150.
• Figure 6 shows the substrate after the processing step of controlled removal of sacrificial material 160 from the surface of dielectric layer 130.
• sacrificial material 160 is a photoresist
• the controlled removal of photoresist material from the surface of dielectric layer 130 may be accomplished using an oxygen plasma (e.g., oxygen ashing) as known in the art.
• the end point of the removal step is the surface of dielectric layer 130. This may followed by an optional wet clean step as known in the art to remove any residual particles.
• sacrificial material 160 serves the objective of protecting first mask layer 120 during a subsequent etch to, for example, form a trench pattern for a subsequent interconnection line. Accordingly, sacrificial material 160 does not need to completely fill via 150. Still further, sacrificial material 160 should not impede a subsequent etch, such as a subsequent trench etch of dielectric layer 130 around via 150. Thus, in certain situations, it may be desirable to remove a portion of sacrificial material 160 that is in via 150.
• a portion of the photoresist material in via 150 may be removed by continuing the etch with the oxygen plasma (i.e., over-ashing) after the endpoint of the surface of dielectric layer 130 is reached.
• Figure 6 shows an embodied step of the method of the invention wherein a portion of sacrificial material 160 is removed from via 150. It is also to be appreciated that, in another embodiment, sacrificial material 160 is not patterned to completely fill via 150. In such an embodiment, a portion of sacrificial material 160 would not need to be removed, for example, in an over-ashing step.
• Figure 12 is a graphical representation of the controlled height from the surface of dielectric layer 130 into a via having a depth of 1300 nanometers.
• the height of sacrificial material 160 relative to the surface of dielectric layer 130 is compared to the ashing time in seconds beyond the endpoint (i.e., beyond the surface of dielectric layer 130) .
• a photoresist is utilized as photoresist material 160 and the substrate is exposed to an oxygen/nitrogen plasma mixed under low temperature condition (about 200 °C) in photoresist removing equipment. The low temperature during ash process helps control the PR removal process.
• sacrificial material 160 may be formed with a controlled height in via 150 (e.g., a predetermined height over first mask layer 120) based on over-ashing.
• a controlled height in via 150 e.g., a predetermined height over first mask layer 120
• the within-wafer and wafer-to- wafer variability of the height of sacrificial material 160 in a via may be significantly reduced, compared to the performance obtained by using a longer develop process, for example .
• pattern mask or third mask layer 170 is patterned over dielectric layer 130 to pattern a trench in oxide 130.
• Figure 7 shows pattern mask or third mask layer 170 patterned over dielectric layer 130 in such a way as to leave an area 175 exposed for trench patterning.
• a suitable pattern or third mask layer 170 is, for example, a photoresist formed as described above with respect to second mask layer 140.
• third mask layer 170 is a positive photoresist
• the photoresist is coated over dielectric layer 130.
• a mask or reticle is then used to expose a portion of the photoresist to a light source.
• the exposed portion defines a trench over via 150.
• the exposed portion includes an area over sacrificial material 160. Because sacrificial material 160 is generally insensitive to a photoreaction, sacrificial material 160 is not affected by the exposure to, for example, an UV light source. Sacrificial material 160 is insensitive either in that it does not contain any photo-active components or has been treated, for example, by heat, to inactivate its sensitivity to a photoreaction.
• a photoresist containing a light-absorbing dye may be used as sacrificial material 160.
• the light-absorbing dye absorbs any UV light striking sacrificial material 160.
• a trench patterning step to pattern a photoresist mask over dielectric layer 130 will not significantly effect sacrificial material 160.
• trench 180 is formed in dielectric layer 130.
• Trench 180 is patterned to a depth suitable for a conductive interconnection.
• trench 180 has a depth of approximately 500 nm. Again, the precise dimensions of trench 180 will vary depending on the scale of the integrated circuit to be formed.
• a suitable etchant to form trench 180 is, for example C 4 F 8 /0 2 /Ar etch chemistry.
• sacrificial material 160 By incorporating sacrificial material 160 in via 150, underlying first mask layer 120 is protected during the trench etch described above. If concerns of removing underlying first mask layer 120 (such as, for example, Si 3 N 4 layer) are removed, a suitable etchant may be chosen for the trench etch without concern for selectivity between dielectric layer 130 and first mask layer 120. Accordingly, a suitable etchant can be chosen based on other parameters, for example, the etch rate, the verticalness of the etch, etc .
• Figure 9 shows the substrate after the subsequent processing step of removing third mask layer 170.
• Figure 9 also shows the substrate after the step of removing sacrificial material 160 and exposing underlying first mask layer 120.
• sacrificial material 160 is selected, in one embodiment, to have a low etch rate during trench etch.
• sacrificial material 160 and third mask layer 170 are each photoresist thus allowing the simultaneous removal of sacrificial material 160 and third mask layer 170.
• third mask layer 170 is also photoresist, both third mask layer 170 and sacrificial material 160 may be removed by, for example, an oxygen ashing. Since first mask layer 120 overlies copper interconnection line in via 150, copper interconnection line 110 is protected from oxidation by the presence of oxygen during the oxygen ashing step.
• a subsequent etch may be used to remove the exposed Si 3 N 4 material of first mask layer 120. Removing exposed first mask layer 120 in via 150 exposes underlying copper interconnection 110 as shown in Figure 10.
• a suitable etchant to remove first mask layer 120 of Si 3 N 4 is, for example, a CF 4 /0 2 etch chemistry.
• Figure 11 shows the substrate after the subsequent processing step of depositing copper material 190 in trench 180 and via 150.
• the deposition precedes via a conventional damascene process.
• the substrate may be planarized according to conventional damascene processing techniques to form a subsequent level interconnection. The process steps described above with respect to Figures 1-11 may then be repeated for a subsequent interconnection layer.

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• 2000
  • 2000-06-05 AU AU57908/00A patent/AU5790800A/en not_active Abandoned
  • 2000-06-05 JP JP2001506606A patent/JP4675534B2/ja not_active Expired - Fee Related
  • 2000-06-05 KR KR10-2001-7016608A patent/KR100452418B1/ko not_active Expired - Fee Related
  • 2000-06-05 HK HK02104146.3A patent/HK1042380A1/zh unknown
  • 2000-06-05 EP EP00943434A patent/EP1192656A1/en not_active Ceased
  • 2000-06-05 WO PCT/US2000/040108 patent/WO2001001480A1/en not_active Ceased
  • 2000-06-05 IL IL14730100A patent/IL147301A0/xx active IP Right Grant
  • 2000-08-19 TW TW089112999A patent/TW531789B/zh not_active IP Right Cessation
• 2001
  • 2001-12-25 IL IL147301A patent/IL147301A/en not_active IP Right Cessation

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