JP4472286B2 - 変形されたデュアルダマシン工程を利用した半導体素子の金属配線形成方法 - Google Patents
変形されたデュアルダマシン工程を利用した半導体素子の金属配線形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 143
- 239000004065 semiconductor Substances 0.000 title claims description 49
- 229910052751 metal Inorganic materials 0.000 title claims description 36
- 239000002184 metal Substances 0.000 title claims description 36
- 230000008569 process Effects 0.000 title description 71
- 230000009977 dual effect Effects 0.000 title description 9
- 239000000463 material Substances 0.000 claims description 159
- 239000010410 layer Substances 0.000 claims description 95
- 239000011229 interlayer Substances 0.000 claims description 54
- 229920002120 photoresistant polymer Polymers 0.000 claims description 43
- 238000005530 etching Methods 0.000 claims description 41
- 229910052760 oxygen Inorganic materials 0.000 claims description 27
- 239000001301 oxygen Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 22
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 20
- 239000007769 metal material Substances 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 15
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 11
- 229910052799 carbon Inorganic materials 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 9
- -1 oxygen ions Chemical class 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000004380 ashing Methods 0.000 description 34
- 230000002265 prevention Effects 0.000 description 14
- 230000003071 parasitic effect Effects 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 7
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000003449 preventive effect Effects 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 description 3
- 239000001569 carbon dioxide Substances 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000005441 aurora Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 229910021426 porous silicon Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 150000003481 tantalum Chemical class 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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Description
前記したフォトレジスト膜を除去する方法は酸素プラズマ放電を利用する方法またはオゾンを利用する方法を使用して遂行でき、この場合に前記した第1物質膜は炭素がドーピングされた酸化膜のように酸素または酸素イオンに対して高い選択性を有する物質を含むのが望ましい。
そして、前記した第1層間絶縁膜を形成する前に半導体基板上にエッチング防止膜を蒸着する段階をさらに含み、前記した第2物質膜を除去する段階でビアホールに露出されたエッチング防止膜をエッチングする段階をさらに含むことができる。
そして、前記した金属物質を蒸着する前にビアホールに露出された第1層間絶縁膜上には障壁層を形成する段階をさらに含むことができる。
前記したフォトレジスト膜を除去する方法は酸素プラズマ放電を利用する方法またはオゾンを利用する方法を使用して遂行でき、この場合に前記した第1物質膜は炭素がドーピングされた酸化膜のように酸素または酸素イオンに対して高い選択性を有する物質で形成するのが望ましい。
そして、前記したビアコンタクトは隣接した地域の配線のパターン密度が相対的に低い位置に形成されうる。
そして、前記した金属物質を蒸着する前にビアホールに露出された第1層間絶縁膜上には障壁層を形成する段階をさらに含むことができる。
105 導電層
110 エッチング防止膜
121 第1層間絶縁膜パターン
132 第1物質膜パターン
135 第1物質膜
141 第2物質膜パターン
160 ビアホール
Claims (21)
- 半導体素子の金属配線形成方法において、
(a)導電層が形成された半導体基板上に、第1層間絶縁膜と、フォトレジストを除去するために使用する媒体に対して高い選択性を有する物質を含む第1物質膜と、第2物質膜とを順次形成する段階と、
(b)前記第2物質膜上に前記第2物質膜の上面を一部露出させるパターンを有するフォトレジスト膜を形成する段階と、
(c)前記フォトレジスト膜をエッチング防止膜として前記第2物質膜、第1物質膜及び第1層間絶縁膜をエッチングしてビアホールを形成する段階と、
(d)前記フォトレジストを除去するために使用する媒体と反応させて前記第1物質膜の前記ビアホールに露出された部分を変成させると同時に前記フォトレジスト膜を除去する段階と、
(e)前記変成された第1物質膜を除去して前記第1物質膜に前記ビアホールよりも大きい開口を形成する段階と、
(f)残っている前記第2物質膜を除去する段階と、
(g)前記ビアホール及び開口を埋め込むように金属物質を蒸着する段階と、
(h)前記第1層間絶縁膜が表れるまで前記半導体素子を平坦化してビアコンタクトを形成する段階と、
を含むことを特徴とする半導体素子の金属配線形成方法。 - 前記金属物質はCuを含む物質であることを特徴とする請求項1に記載の半導体素子の金属配線形成方法。
- 前記フォトレジスト膜を除去する段階は、酸素プラズマ放電を利用する方法またはオゾンを利用する方法を使用して遂行することを特徴とする請求項1に記載の半導体素子の金属配線形成方法。
- 前記第1物質膜に含まれた物質は酸素または酸素イオンに対して高い選択性を有する物質であることを特徴とする請求項1に記載の半導体素子の金属配線形成方法。
- 前記第1物質膜は炭素がドーピングされた酸化膜であることを特徴とする請求項4に記載の半導体素子の金属配線形成方法。
- 前記ビアコンタクトを形成する段階の後で前記結果物上に前記ビアコンタクトと連結される配線パターンと前記配線パターンを覆い包む第2層間絶縁膜とを含む配線層を形成する段階をさらに含むことを特徴とする請求項1に記載の半導体素子の金属配線形成方法。
- 前記配線層の前記配線パターンはアルミニウムを使用して形成することを特徴とする請求項6に記載の半導体素子の金属配線形成方法。
- 前記第2物質膜は前記フォトレジスト膜を除去する段階で変成されない物質で形成することを特徴とする請求項1に記載の半導体素子の金属配線形成方法。
- 前記第2物質膜はSiONを含む膜、シリコン酸化膜、シリコン窒化膜、シリコンカーバイド膜、ポリシリコン膜、金属酸化物を含む膜または金属窒化物を含む物質で形成することを特徴とする請求項8に記載の半導体素子の金属配線形成方法。
- 前記第1層間絶縁膜を形成する前に前記半導体基板上にエッチング防止膜を形成する段階をさらに含み、
前記金属物質を蒸着する段階の前に前記ビアホールに露出された前記エッチング防止膜をエッチングする段階をさらに含むことを特徴とする請求項1に記載の半導体素子の金属配線形成方法。 - 前記金属物質を蒸着する段階の前に前記ビアホールに露出された前記第1層間絶縁膜上に拡散防止膜を形成する段階をさらに含むことを特徴とする請求項1に記載の半導体素子の金属配線形成方法。
- 前記ビアコンタクトを形成する段階の後で前記結果物上に拡散防止膜を形成する段階をさらに含むことを特徴とする請求項1に記載の半導体素子の金属配線形成方法。
- 半導体素子の金属配線形成方法において、
(a)導電層が形成された半導体基板上に、第1層間絶縁膜と、フォトレジスト膜を除去する段階で使用する媒体に対して高い選択性を有する物質を含む第1物質膜とを順次形成する段階と、
(b)前記第1物質膜上に前記第1物質膜の上面を一部露出させるパターンを有するフォトレジスト膜を形成する段階と、
(c)前記第1物質膜及び第1層間絶縁膜をエッチングしてビアホールを形成する段階と、
(d)前記第1物質膜に含まれた物質と反応して前記第1物質膜の前記フォトレジスト膜と接触する部分及び前記ビアホールに露出された部分を変成させると同時に前記フォトレジスト膜を除去する段階と、
(e)前記変成された第1物質膜を除去して前記第1物質膜に前記ビアホールよりも大きい開口を形成する段階と、
(f)前記ビアホール及び開口を埋め込むように金属物質を蒸着する段階と、
(g)前記第1層間絶縁膜が表れるまで前記半導体素子を平坦化してビアコンタクトを形成する段階と、
を含むことを特徴とする半導体素子の金属配線形成方法。 - 前記金属物質はCuを含む物質であることを特徴とする請求項13に記載の半導体素子の金属配線形成方法。
- 前記開口を形成する段階の後で前記結果物上に拡散防止膜を形成する段階をさらに含むことを特徴とする請求項13に記載の半導体素子の金属配線形成方法。
- 前記第1物質膜に含まれた不純物は酸素または酸素イオンに対して高い選択性を有する物質を含むことを特徴とする請求項13に記載の半導体素子の金属配線形成方法。
- 前記第1物質膜は炭素がドーピングされた酸化膜であることを特徴とする請求項13に記載の半導体素子の金属配線形成方法。
- 前記ビアコンタクトを形成する段階の後で前記結果物上に前記ビアコンタクトと連結される配線パターンと前記配線パターンを覆い包む第2層間絶縁膜を含む配線層とを形成する段階をさらに含むことを特徴とする請求項13に記載の半導体素子の金属配線形成方法。
- 前記配線層の配線パターンはアルミニウムを使用して形成することを特徴とする請求項18に記載の半導体素子の金属配線形成方法。
- 前記第1層間絶縁膜を形成する前に前記半導体基板上にエッチング防止膜を蒸着する段階をさらに含み、
前記開口を形成する段階の後で前記ビアホールに露出された前記エッチング防止膜をエッチングする段階をさらに含むことを特徴とする請求項13に記載の半導体素子の金属配線形成方法。 - 前記金属物質を蒸着する段階の前に前記ビアホールに露出された層間絶縁膜上に拡散防止膜を形成する段階をさらに含むことを特徴とする請求項13に記載の半導体素子の金属配線形成方法。
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KR10-2002-0045610A KR100434508B1 (ko) | 2002-08-01 | 2002-08-01 | 변형된 듀얼 다마신 공정을 이용한 반도체 소자의 금속배선 형성방법 |
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JP2004072107A JP2004072107A (ja) | 2004-03-04 |
JP4472286B2 true JP4472286B2 (ja) | 2010-06-02 |
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US (1) | US7041592B2 (ja) |
JP (1) | JP4472286B2 (ja) |
KR (1) | KR100434508B1 (ja) |
TW (1) | TWI313495B (ja) |
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US7902613B1 (en) * | 2008-01-28 | 2011-03-08 | Cadence Design Systems, Inc. | Self-alignment for semiconductor patterns |
US7687381B2 (en) * | 2008-03-19 | 2010-03-30 | Samsung Electronics Co., Ltd. | Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall |
US8796150B2 (en) | 2011-01-24 | 2014-08-05 | International Business Machines Corporation | Bilayer trench first hardmask structure and process for reduced defectivity |
KR20150092581A (ko) * | 2014-02-05 | 2015-08-13 | 삼성전자주식회사 | 배선 구조물 및 그 형성 방법 |
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JPH04293233A (ja) * | 1991-03-22 | 1992-10-16 | Sony Corp | メタルプラグの形成方法 |
US6627532B1 (en) * | 1998-02-11 | 2003-09-30 | Applied Materials, Inc. | Method of decreasing the K value in SiOC layer deposited by chemical vapor deposition |
US6406995B1 (en) * | 1998-09-30 | 2002-06-18 | Intel Corporation | Pattern-sensitive deposition for damascene processing |
KR20000066846A (ko) * | 1999-04-21 | 2000-11-15 | 김영환 | 접촉홀 형성방법 |
US20010051420A1 (en) * | 2000-01-19 | 2001-12-13 | Besser Paul R. | Dielectric formation to seal porosity of low dielectic constant (low k) materials after etch |
TW486801B (en) * | 2000-04-07 | 2002-05-11 | Taiwan Semiconductor Mfg | Method of fabricating dual damascene structure |
US6509623B2 (en) * | 2000-06-15 | 2003-01-21 | Newport Fab, Llc | Microelectronic air-gap structures and methods of forming the same |
US6358842B1 (en) * | 2000-08-07 | 2002-03-19 | Chartered Semiconductor Manufacturing Ltd. | Method to form damascene interconnects with sidewall passivation to protect organic dielectrics |
KR20020017181A (ko) * | 2000-08-29 | 2002-03-07 | 윤종용 | 반도체 소자의 듀얼 다마신 배선을 위한 컨택 홀 형성 방법 |
US6861347B2 (en) * | 2001-05-17 | 2005-03-01 | Samsung Electronics Co., Ltd. | Method for forming metal wiring layer of semiconductor device |
US6551915B2 (en) * | 2001-07-03 | 2003-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thermal annealing/hydrogen containing plasma method for forming structurally stable low contact resistance damascene conductor structure |
US20030082905A1 (en) * | 2001-10-31 | 2003-05-01 | Jen-Ku Hung | Method for forming a uniform damascene profile |
US6528409B1 (en) * | 2002-04-29 | 2003-03-04 | Advanced Micro Devices, Inc. | Interconnect structure formed in porous dielectric material with minimized degradation and electromigration |
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- 2003-05-30 US US10/449,973 patent/US7041592B2/en not_active Expired - Fee Related
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TWI313495B (en) | 2009-08-11 |
JP2004072107A (ja) | 2004-03-04 |
US7041592B2 (en) | 2006-05-09 |
KR20040013165A (ko) | 2004-02-14 |
KR100434508B1 (ko) | 2004-06-05 |
TW200402839A (en) | 2004-02-16 |
US20040038521A1 (en) | 2004-02-26 |
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