JP4662772B2 - Ｍｏｓ電界効果トランジスタを形成する方法 - Google Patents

Ｍｏｓ電界効果トランジスタを形成する方法 Download PDF

Info

Publication number
JP4662772B2
JP4662772B2 JP2004546734A JP2004546734A JP4662772B2 JP 4662772 B2 JP4662772 B2 JP 4662772B2 JP 2004546734 A JP2004546734 A JP 2004546734A JP 2004546734 A JP2004546734 A JP 2004546734A JP 4662772 B2 JP4662772 B2 JP 4662772B2
Authority
JP
Japan
Prior art keywords
layer
gate
nickel
silicon germanium
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2004546734A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006501685A (ja
JP2006501685A5 (enExample
Inventor
エヌ． ペイトン エリック
シャン キ
アール． ベセル ポール
リン ミン−レン
バン エヌジーオー ミン
ワン ハイホン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2006501685A publication Critical patent/JP2006501685A/ja
Publication of JP2006501685A5 publication Critical patent/JP2006501685A5/ja
Application granted granted Critical
Publication of JP4662772B2 publication Critical patent/JP4662772B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
JP2004546734A 2002-09-30 2003-09-12 Ｍｏｓ電界効果トランジスタを形成する方法 Expired - Lifetime JP4662772B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US41517902P 2002-09-30 2002-09-30
US10/335,492 US6787864B2 (en) 2002-09-30 2002-12-31 Mosfets incorporating nickel germanosilicided gate and methods for their formation
PCT/US2003/028680 WO2004038807A1 (en) 2002-09-30 2003-09-12 Mosfets incorporating nickel germanosilicided gate and methods of their formation

Publications (3)

Publication Number Publication Date
JP2006501685A JP2006501685A (ja) 2006-01-12
JP2006501685A5 JP2006501685A5 (enExample) 2006-11-02
JP4662772B2 true JP4662772B2 (ja) 2011-03-30

Family

ID=32033324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004546734A Expired - Lifetime JP4662772B2 (ja) 2002-09-30 2003-09-12 Ｍｏｓ電界効果トランジスタを形成する方法

Country Status (8)

Country Link
US (1) US6787864B2 (enExample)
EP (1) EP1550164B1 (enExample)
JP (1) JP4662772B2 (enExample)
KR (1) KR101054057B1 (enExample)
CN (1) CN100557817C (enExample)
AU (1) AU2003270598A1 (enExample)
TW (1) TWI338367B (enExample)
WO (1) WO2004038807A1 (enExample)

Families Citing this family (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6703688B1 (en) * 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6946371B2 (en) 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6982474B2 (en) * 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
JP3597831B2 (ja) * 2002-07-01 2004-12-08 株式会社東芝 電界効果トランジスタ及びその製造方法
US6746967B2 (en) * 2002-09-30 2004-06-08 Intel Corporation Etching metal using sonication
US6867428B1 (en) * 2002-10-29 2005-03-15 Advanced Micro Devices, Inc. Strained silicon NMOS having silicon source/drain extensions and method for its fabrication
JP4275395B2 (ja) * 2002-12-11 2009-06-10 株式会社ルネサステクノロジ 半導体装置の製造方法
WO2004073044A2 (en) 2003-02-13 2004-08-26 Massachusetts Institute Of Technology Finfet device and method to make same
CN100437970C (zh) 2003-03-07 2008-11-26 琥珀波系统公司 一种结构及用于形成半导体结构的方法
TWI231994B (en) * 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
US6905976B2 (en) * 2003-05-06 2005-06-14 International Business Machines Corporation Structure and method of forming a notched gate field effect transistor
US7192876B2 (en) * 2003-05-22 2007-03-20 Freescale Semiconductor, Inc. Transistor with independent gate structures
JP4008860B2 (ja) * 2003-07-11 2007-11-14 株式会社東芝 半導体装置の製造方法
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
KR100487566B1 (ko) * 2003-07-23 2005-05-03 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 형성 방법
JP2005086024A (ja) * 2003-09-09 2005-03-31 Toshiba Corp 半導体装置及びその製造方法
US7175966B2 (en) * 2003-09-19 2007-02-13 International Business Machines Corporation Water and aqueous base soluble antireflective coating/hardmask materials
US20050090082A1 (en) * 2003-10-28 2005-04-28 Texas Instruments Incorporated Method and system for improving performance of MOSFETs
KR100738066B1 (ko) * 2003-12-01 2007-07-12 삼성전자주식회사 열적 안정성이 우수한 실리사이드막 형성방법, 이방법으로 형성된 실리사이드막이 구비된 반도체 소자와반도체 메모리 소자 및 이들 소자의 제조 방법
US6949482B2 (en) 2003-12-08 2005-09-27 Intel Corporation Method for improving transistor performance through reducing the salicide interface resistance
JP3879003B2 (ja) * 2004-02-26 2007-02-07 国立大学法人名古屋大学 シリサイド膜の作製方法
US7235471B2 (en) * 2004-05-26 2007-06-26 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a silicide layer
US7009226B1 (en) * 2004-07-12 2006-03-07 Advanced Micro Devices, Inc. In-situ nitride/oxynitride processing with reduced deposition surface pattern sensitivity
JP2008508713A (ja) * 2004-07-27 2008-03-21 エージェンシー フォー サイエンス，テクノロジー アンド リサーチ 高信頼性コンタクト
US7435672B2 (en) * 2004-07-30 2008-10-14 Texas Instruments Incorporated Metal-germanium physical vapor deposition for semiconductor device defect reduction
US7166897B2 (en) * 2004-08-24 2007-01-23 Freescale Semiconductor, Inc. Method and apparatus for performance enhancement in an asymmetrical semiconductor device
US7288448B2 (en) * 2004-08-24 2007-10-30 Orlowski Marius K Method and apparatus for mobility enhancement in a semiconductor device
US7348641B2 (en) * 2004-08-31 2008-03-25 International Business Machines Corporation Structure and method of making double-gated self-aligned finFET having gates of different lengths
US7241649B2 (en) * 2004-10-29 2007-07-10 International Business Machines Corporation FinFET body contact structure
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
KR100678314B1 (ko) 2004-12-15 2007-02-02 동부일렉트로닉스 주식회사 저접촉저항을 갖는 반도체 소자의 제조방법
JP4969779B2 (ja) 2004-12-28 2012-07-04 株式会社東芝 半導体装置の製造方法
WO2006070670A1 (ja) * 2004-12-28 2006-07-06 Matsushita Electric Industrial Co., Ltd. 半導体ナノワイヤ、および当該ナノワイヤを備えた半導体装置
US20060163670A1 (en) * 2005-01-27 2006-07-27 International Business Machines Corporation Dual silicide process to improve device performance
US7319063B2 (en) * 2005-02-02 2008-01-15 United Microelectronics Corp. Fin field effect transistor and method for manufacturing fin field effect transistor
US7348232B2 (en) * 2005-03-01 2008-03-25 Texas Instruments Incorporated Highly activated carbon selective epitaxial process for CMOS
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US7902598B2 (en) 2005-06-24 2011-03-08 Micron Technology, Inc. Two-sided surround access transistor for a 4.5F2 DRAM cell
US7109116B1 (en) * 2005-07-21 2006-09-19 International Business Machines Corporation Method for reducing dendrite formation in nickel silicon salicide processes
KR100685898B1 (ko) 2005-07-27 2007-02-26 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7566609B2 (en) * 2005-11-29 2009-07-28 International Business Machines Corporation Method of manufacturing a semiconductor structure
WO2007112066A2 (en) 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
US7459382B2 (en) 2006-03-24 2008-12-02 International Business Machines Corporation Field effect device with reduced thickness gate
US20070238236A1 (en) * 2006-03-28 2007-10-11 Cook Ted Jr Structure and fabrication method of a selectively deposited capping layer on an epitaxially grown source drain
US7618891B2 (en) * 2006-05-01 2009-11-17 International Business Machines Corporation Method for forming self-aligned metal silicide contacts
EP2062290B1 (en) 2006-09-07 2019-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction using aspect ratio trapping
KR100798814B1 (ko) * 2006-09-20 2008-01-28 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 형성방법
US7875958B2 (en) 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
WO2008039495A1 (en) 2006-09-27 2008-04-03 Amberwave Systems Corporation Tri-gate field-effect transistors formed by aspect ratio trapping
WO2008051503A2 (en) 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US7550796B2 (en) * 2006-12-06 2009-06-23 Electronics And Telecommunications Research Institute Germanium semiconductor device and method of manufacturing the same
KR20080062764A (ko) * 2006-12-29 2008-07-03 삼성전자주식회사 게르마늄실리사이드 형성방법 및 이를 적용하여 게르마늄실리사이드가 형성된 디바이스
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
US9508890B2 (en) 2007-04-09 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Photovoltaics on silicon
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
KR100861211B1 (ko) * 2007-04-12 2008-09-30 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
JP2010538495A (ja) 2007-09-07 2010-12-09 アンバーウェーブ・システムズ・コーポレーション 多接合太陽電池
US20090065804A1 (en) * 2007-09-10 2009-03-12 International Business Machines Corporation Bipolar transistor with low resistance base contact and method of making the same
JP5525127B2 (ja) * 2007-11-12 2014-06-18 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
KR101194843B1 (ko) 2007-12-07 2012-10-25 삼성전자주식회사 Ｇｅ 실리사이드층의 형성방법, Ｇｅ 실리사이드층을포함하는 반도체 소자 및 그의 제조방법
US20090152590A1 (en) * 2007-12-13 2009-06-18 International Business Machines Corporation Method and structure for semiconductor devices with silicon-germanium deposits
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
CN102160145B (zh) 2008-09-19 2013-08-21 台湾积体电路制造股份有限公司 通过外延层过成长的元件形成
US20100072515A1 (en) 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
DE102008053955B4 (de) * 2008-10-31 2010-10-21 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Halbleiterbauelements als Transistor mit Verbesserung der Verspannungsübertragung durch eine späte Gaterekristallisierung und Transistor
KR101561059B1 (ko) * 2008-11-20 2015-10-16 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9379011B2 (en) * 2008-12-19 2016-06-28 Asm International N.V. Methods for depositing nickel films and for making nickel silicide and nickel germanide
CN102379046B (zh) 2009-04-02 2015-06-17 台湾积体电路制造股份有限公司 从晶体材料的非极性平面形成的器件及其制作方法
FR2953989B1 (fr) * 2009-12-10 2012-05-18 Commissariat Energie Atomique Procede de formation de materiaux metalliques comportant des semi-conducteurs
EP2519969A4 (en) * 2009-12-28 2016-07-06 Semiconductor Energy Lab SEMICONDUCTOR COMPONENT
US8729627B2 (en) 2010-05-14 2014-05-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel integrated circuit devices
US20120139014A1 (en) * 2010-12-01 2012-06-07 International Business Machines Corporation Structure and method for low temperature gate stack for advanced substrates
JP2015504479A (ja) 2011-11-08 2015-02-12 トーソー エスエムディー，インク． 特別な表面処理及び優れた粒子性能を有するシリコンスパッターターゲット及びその製造方法
US8580686B1 (en) * 2012-04-23 2013-11-12 Globalfoundries Inc. Silicidation and/or germanidation on SiGe or Ge by cosputtering Ni and Ge and using an intralayer for thermal stability
US8624324B1 (en) * 2012-08-10 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting through vias to devices
US9377394B2 (en) 2012-10-16 2016-06-28 Seagate Technology Llc Distinguishing foreign surface features from native surface features
CN104425364B (zh) * 2013-09-09 2017-09-29 中芯国际集成电路制造(上海)有限公司 连接线的形成方法
US10032876B2 (en) * 2014-03-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact silicide having a non-angular profile
US9590105B2 (en) * 2014-04-07 2017-03-07 National Chiao-Tung University Semiconductor device with metal alloy over fin, conductive layer over channel region of fin, and semiconductive layer over conductive layer and formation thereof
KR20160058499A (ko) 2014-11-17 2016-05-25 삼성전자주식회사 반도체 소자, 및 그 반도체 소자의 제조방법과 제조장치
US9865466B2 (en) * 2015-09-25 2018-01-09 Applied Materials, Inc. Silicide phase control by confinement
CN109950151B (zh) * 2017-12-20 2022-02-15 中芯国际集成电路制造(上海)有限公司 Pmos晶体管及其形成方法
US12476144B2 (en) * 2021-12-07 2025-11-18 International Business Machines Corporation Etch back and film profile shaping of selective dielectric deposition
CN116632062A (zh) * 2022-02-14 2023-08-22 联华电子股份有限公司 中压晶体管及其制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05183160A (ja) * 1991-12-26 1993-07-23 Toshiba Corp 半導体装置及びその製造方法
JPH07202178A (ja) * 1993-12-28 1995-08-04 Toshiba Corp 半導体装置およびその製造方法
US5561302A (en) * 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
JP3326427B2 (ja) * 1996-09-17 2002-09-24 松下電器産業株式会社 半導体装置及びその製造方法
JP4092766B2 (ja) * 1998-03-27 2008-05-28 富士通株式会社 半導体装置
EP1147552A1 (en) * 1998-11-12 2001-10-24 Intel Corporation Field effect transistor structure with abrupt source/drain junctions
KR100332108B1 (ko) * 1999-06-29 2002-04-10 박종섭 반도체 소자의 트랜지스터 및 그 제조 방법
JP2002110989A (ja) * 2000-09-27 2002-04-12 Japan Science & Technology Corp 半導体集積回路装置およびその製造方法
US6724008B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
JP2004531054A (ja) * 2001-03-02 2004-10-07 アンバーウェーブ システムズ コーポレイション 高速ｃｍｏｓ電子機器及び高速アナログ回路のための緩和シリコンゲルマニウムプラットフォーム
JP3547419B2 (ja) * 2001-03-13 2004-07-28 株式会社東芝 半導体装置及びその製造方法
US6506637B2 (en) * 2001-03-23 2003-01-14 Sharp Laboratories Of America, Inc. Method to form thermally stable nickel germanosilicide on SiGe
US6974735B2 (en) * 2001-08-09 2005-12-13 Amberwave Systems Corporation Dual layer Semiconductor Devices

Also Published As

Publication number Publication date
JP2006501685A (ja) 2006-01-12
TW200417029A (en) 2004-09-01
TWI338367B (en) 2011-03-01
CN100557817C (zh) 2009-11-04
US20040061191A1 (en) 2004-04-01
KR101054057B1 (ko) 2011-08-04
KR20050070011A (ko) 2005-07-05
US6787864B2 (en) 2004-09-07
EP1550164A1 (en) 2005-07-06
CN1685520A (zh) 2005-10-19
EP1550164B1 (en) 2012-04-18
WO2004038807A1 (en) 2004-05-06
AU2003270598A1 (en) 2004-05-13

Similar Documents

Publication Publication Date Title
JP4662772B2 (ja) Ｍｏｓ電界効果トランジスタを形成する方法
US7229873B2 (en) Process for manufacturing dual work function metal gates in a microelectronics device
JP5672334B2 (ja) 半導体装置の製造方法
JP4982958B2 (ja) 半導体装置とその製造方法
TWI387010B (zh) 用於製造電晶體之方法
US20070052034A1 (en) Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors
JP5659416B2 (ja) 半導体素子の製造方法
JP2006351581A (ja) 半導体装置の製造方法
JP3594140B2 (ja) 半導体装置の製造方法
US7638433B2 (en) Semiconductor device and method of fabricating the same
US8435862B2 (en) Method of manufacturing semiconductor device
US8575014B2 (en) Semiconductor device fabricated using a metal microstructure control process
JP5157450B2 (ja) 半導体装置およびその製造方法
CN101447454B (zh) 一种调节全硅化金属栅的栅功函数的方法
WO2007026677A1 (ja) 半導体装置の製造方法
JP4533155B2 (ja) 半導体装置及びその製造方法
JP2001326351A (ja) 半導体装置及びその製造方法
JP2005243678A (ja) 半導体装置の製造方法
TWI390640B (zh) 半導體製造方法
JP2003209120A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060911

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060911

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081121

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100209

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100421

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20100430

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20100512

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20100609

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20100616

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100709

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100804

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20100902

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101104

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101201

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110104

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4662772

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140114

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term