CN1685520A - 具有镍锗硅化物栅极的mosfet及其形成方法 - Google Patents

具有镍锗硅化物栅极的mosfet及其形成方法 Download PDF

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CN1685520A
CN1685520A CN03823253.7A CN03823253A CN1685520A CN 1685520 A CN1685520 A CN 1685520A CN 03823253 A CN03823253 A CN 03823253A CN 1685520 A CN1685520 A CN 1685520A
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nickel
source electrode
silicon
germanium
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E·N·佩顿
相奇
P·R·贝瑟
林明仁
M·V·恩戈
王海宏
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Advanced Micro Devices Inc
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Abstract

MOSFET栅极或MOSFET源极或漏极区域包括硅锗或者多晶硅锗。以镍进行硅化，以形成镍锗硅化物(62，64)，该镍锗硅化物较佳地包括镍硅化物的单硅化物相。硅化物中包含的锗在形成单硅化物相的期间内，提供了较宽的温度范围，而却实质地维持了镍单硅化物所呈现的较好薄层电阻。结果，在随后的处理期间，镍锗硅化物比镍单硅化物更能够抵挡较高的温度，而却仍能够提供与镍单硅化物大约相同的薄层电阻与其它有利特性。

Description

具有镍锗硅化物栅极的MOSFET及其形成方法
技术领域
本发明涉及金属氧化物半导体场效应晶体管(MOSFET)，而且更具体的涉及形成与MOSFET源极和漏极区域以及栅极电极的接触所使用的硅金属化合物。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)是大部分半导体器件的主要组件。图1显示了根据传统技术而形成的MOSFET。MOSFET包括半导体衬底10，其中形成有深的源极和漏极区域12以及浅的源极和漏极延伸14。多晶硅栅极16覆盖栅极氧化物18，并且由形成在其侧壁上的间隔物20所保护。源极和漏极区域12连接到导电接触22，该些接触则嵌入于譬如硼磷硅酸盐玻璃(BPSG)的保护层24里。
传统的MOSFET利用硅化物区域26，以促进具有低接触电阻的与源极和漏极区域12的欧姆接触的形成。硅化物区域28也同样形成在栅极16上，以形成传统上称为多晶金属硅化物(Polycide)的结构。传统上，使用譬如钛、钨、钽或钼的难熔金属来形成栅极以及源极/漏极硅化物。近来，钴已经被采用作为形成硅化物的较佳金属。硅化物区域用作界面，该界面减少底层硅与譬如铝的其它材料之间的接触电阻，这些其它材料传统上被用作源极、漏极与栅极的第一连接层。
譬如显示在图1的硅化物区域一般经由自对准工艺而制造，其因而有时被称为″salicides″(自对准金属硅化物)。在自对准金属硅化的工艺中，使用单一掩膜以自对准方式将栅极与栅极氧化物一起图形化，进行低能量的掺杂注入以形成浅的源极和漏极延伸，随后在栅极与栅极氧化物的侧壁上形成间隔物，进行高能量掺杂注入以形成深的源极和漏极区域，而且随后覆盖整个结构形成金属的共形层。随后进行热处理以促进硅化物化合物的形成，该硅化物化合物包括金属和源极和漏极区域的硅以及栅极的多晶硅。在执行了用于产生预期厚度硅化物的足够时间的热处理以后，去除残留的金属，而留下如图1所示的硅化物区域。
增加器件速度与性能的需求，已经驱使持续研究降低MOSFET尺寸和增加MOSFET操作速度的方法。同时，进一步的研究朝向确认可取代传统材料的新材料，以提供譬如更容易微型化和简化工艺整合的优点。
被视为取代传统难熔接触金属的一种材料是镍(Ni)。镍形成镍硅化物的三相：富含金属的硅化二镍(Ni2Si，di-nickel silicide)、单硅化镍(NiSi，nickel monosilicide)以及富含硅的二硅化镍(NiSi2，nickeldi-silicide)。因为与钛相比，单硅化镍具有低的电阻率，所以是特别优选的，其在硅化物形成期间内消耗较少的硅，因而提供了非常薄的有源区域的硅化。单硅化镍薄层电阻也没有不利的线宽依赖性，线宽依赖性经常是具有传统难熔硅化物的问题。因为对单硅化镍而言具体的边缘效应，所以发现单硅化镍薄层电阻在窄线中会减少。硅衬底上的单硅化镍的机械应力会小于钛的机械应力。此外，p型硅的接触电阻会低于硅化钛的接触电阻，而且就n型硅而言也很低。单硅化镍同样呈现出对硅的良好附着。因此，单硅化镍呈现出在具有超浅源极和漏极扩散部分的MOSFET中，传统难熔接触金属的期望的替代物。
单硅化镍的一个缺点在于，在MOSFET制造期间所通常遇到的温度上，它的热稳定性相当差。图2显示了硅化镍化合物三相的薄层电阻与它们所形成温度的关系的图式。如图2所示，单硅化镍最佳形成在300至600℃，而且当在该温度范围形成时，它提供了比每平方三欧姆还小的薄层电阻。反的，富含金属的硅化二镍与富含硅的二硅化镍是在此范围外的温度上形成，每个均在薄层电阻上有着明显的增加。结果，为了譬如源极/漏极注入退火的半导体工艺所基本使用的高工艺温度可引起硅化镍转变成二硅化镍，并因而增加了硅化物的薄层电阻。因此，使用单硅化镍的设计被限制在进一步工艺可用的热预算。
结果，现有技术并没有提供在不明显限制随后工艺可用的热预算的情况下，利用单硅化镍的有利特征的方式。
发明内容
有鉴于上述镍单硅化物的优点与缺点，本发明的目的是利用在MOSFET源极/漏极与栅极硅化物中作为接触金属的镍的优点，而减轻存在于已知镍单硅化物工艺的热预算的限制。
根据本发明的具体实施例，MOSFET的栅极覆盖以一层多晶硅锗。随后对镍进行硅化，以形成镍锗硅化物，该镍锗硅化物较佳地包括镍硅化物的单硅化物相。该源极和漏极区域也可采用镍锗硅化物。硅化物中包含的锗在形成单硅化物的期间内提供了较宽的温度范围，而却实质地维持了镍单硅化物所呈现的薄层电阻。结果，在随后的处理期间，镍锗硅化物比镍单硅化物更能够抵挡较高的温度，但却仍提供与镍单硅化物大约相同的薄层电阻与其它有利特性。
根据本发明的一个具体实施例，MOSFET由其上形成有栅极绝缘层的半导体衬底、形成在该栅极绝缘层上的多晶硅层、以及形成在该多晶硅层上的多晶硅锗层所形成。将该多晶硅锗层、多晶硅层与该栅极绝缘层图形化，以形成栅极绝缘体以及覆盖该栅极绝缘体的栅极，该栅极包括下部多晶硅部分与上部多晶硅锗部分。随后覆盖该栅极的至少上部多晶硅锗部分形成镍层，并且进行热处理，以在该栅极上形成镍锗硅化物。
根据本发明另一具体实施例，MOSFET包括源极和漏极区域，延伸在该源极和漏极区域之间的沟道区域，覆盖该沟道区域的栅极绝缘体，以及覆盖该栅极绝缘体的多晶金属硅化物(polycide)栅极。该多晶金属硅化物栅极具有下部多晶硅部分与上部多晶硅锗部分，以及形成在上部多晶硅锗部分上的镍锗硅化物。或者，多晶金属硅化物栅极以及源极和漏极区域的至少其中之一包括镍锗硅化物。
附图说明
结合附图来说明本发明的具体实施例，其中：
图1显示了采用传统的多晶硅栅极结构的传统MOSFET截面；
图2显示了硅化镍薄层电阻与其形成所使用的热处理温度的关系图；
图3显示了硅化镍与镍锗硅化物的薄层电阻与其形成所使用的热处理温度的关系图；
图4a、4b、4c、4d、4e和4f显示了根据本发明第一优选具体实施例的在制造MOSFET期间内所形成的结构；
图5显示了根据本发明第二优选具体实施例而制造的MOSFET；
图6显示了根据本发明第三优选具体实施例而制造的MOSFET；
图7显示了根据本发明第四优选具体实施例而制造的MOSFET；以及
图8显示了根据优选具体实施例和替代性具体实施例的用于制造器件的工艺流程图。
具体实施方式
图3显示了硅化镍与镍锗硅化物薄层电阻与其形成温度的关系图。图3的图式假定锗/硅合成物Si1-xGex，在此x是0.1-0.4。如图3中所见，图式的曲线类似硅化镍与镍锗硅化物，其在每平方三至十欧姆之间变化，不过，镍锗硅化物的富含硅相的形成温度范围会高于镍硅化物的富含硅相的形成温度范围。形成镍锗硅化物的单硅化物相的理想范围位于大约300℃至700℃的范围内。结果，这使镍锗硅化物能够禁得起较高的处理温度，而没有单硅化物相的明显劣化。
因此，第一优选具体实施例采用镍锗硅化物作为MOSFET的栅极接触层。在制造此器件期间内所形成的结构显示在图4a至4f中。
图4a显示了开始形成第一优选具体实施例的MOSFET的结构。该结构包括在其上形成有譬如氧化硅的栅极绝缘层42的硅半导体衬底40、多晶硅栅极导电层44以及多晶硅锗层46。多晶硅锗层46较佳地具有合成物Si1-xGex，在此x基本上在0.1至0.3的范围内，较佳地大约是0.2。栅极氧化物层42较佳地是10至30埃厚，多晶硅栅极导电层44较佳地是500至1000埃厚，而且硅锗层46较佳地是300至600埃厚。形成该栅极氧化物与多晶硅层的工艺众所皆知。多晶硅锗层可能经由以600至900℃的温度、30mPa的乙硅烷部分压力与60mPa的锗烷(germane)部分压力，使用Si2H6(乙硅烷)与GeH4(锗烷)当作源气体的化学气相沉积而形成。多晶硅锗材料的生长可能使用这些比例而开始，或者锗烷的部分压力可能从较低压力或零压力开始而逐渐地增加，以形成梯度的合成物。多晶硅44与多晶硅锗层46可能以清楚的工艺步骤来形成，不过，较佳地乃是在连续工艺中的适当位置中形成诸层，在该连续工艺中，将部分的锗源气体逐渐地引入，以形成分级的层。要注意的是，多晶硅锗可用比沉积多晶硅所需的更低的温度来沉积，而且当形成分级结构时，如此的温度控制可伴随源气体控制而实施。
图4b显示了在图形化该栅极绝缘层、栅极导电层与多晶硅锗层，以形成包括氧化物栅极绝缘体48的自对准栅极堆栈和包括下部多晶硅部分50与上部多晶硅锗部分52的栅极以后，图4a的结构。
图4c显示了在注入源极和漏极以及形成栅极间隔物以后的图4b的结构。为了产生图4c的结构，在图4b的结构上执行低能量掺杂注入，以形成浅的源极和漏极延伸54。随后则通过沉积譬如氧化硅的保护性材料的共形层来形成栅极间隔物56，接着各向异性地蚀刻以将沉积材料从该栅极顶部与该衬底表面去除。接着，进行高能量的掺杂注入，以形成深的源极和漏极区域58。在高能量注入期间，栅极间隔物56用作保护底部浅的源极和漏极延伸的注入掩膜(implant mask)。
图4d显示了在将镍共形层60形成在衬底与栅极堆栈以后的图4c的结构，其包括源极和漏极区域58暴露出的表面以及栅极堆栈暴露出的表面。镍层较佳地由物理气相沉积(溅射)所形成，但是形成金属层的其它已知方法也可采用。
图4e显示了在图4d结构上进行热处理以后的图4d的结构，其促进在镍层60以及源极和漏极区域的硅与栅极上部分52的多晶硅锗之间形成硅化物。热处理较佳地使用350至700℃的温度范围来进行，以便形成主要包括单硅化物相的镍锗硅化物。因为硅化物形成工艺会消耗硅，所以镍锗硅化物层的厚度由进行热处理的时间数量所决定。最终的结构包括形成在该栅极的上部多晶硅锗部分52的镍锗硅化物区域62，以及形成在源极和漏极区域56表面的镍硅化物区域64。
虽然关于图4a至4f而说明的工艺过程代表制造一种包括镍锗硅化物栅极的MOSFET的较佳方式，但是也可采用其它的工艺方法来实施相同结构或者具有镍锗硅化物栅极的其它MOSFET结构。例如，虽然该优选具体实施例使用镍层沉积之后进行热处理的技术，但是可使用替代性的方法来形成镍锗硅化物层，譬如镍、硅与锗的同时蒸发，或者镍、硅与锗的共同溅射，或者来自镍硅锗靶的溅射。应该理解到的是，此替代性方法可能需要与图4a至4f的工艺不同并且可能配制成特定实施过程的掩膜、蚀刻与去除工艺，以在MOSFET的适当位置上形成镍锗硅化物区域。
图5显示了根据本发明第二优选具体实施例的结构。图5结构不同于图4f结构之处在于该衬底包括硅锗层70，在该硅锗层上形成有″应变的″(strained)薄硅层72。应变硅是由于硅晶格与所形成于其上的底层材料晶格的维度的差异结果而施加张力在硅晶格的硅型态。在所示的例子中，硅锗晶格比纯硅晶格的间隔还宽，而该间隔会随着锗比例的增加而变得更宽。因为在形成期间内，硅晶格会对准较大的硅锗晶格，所以张力则会被分到硅层。实际上，硅原子会彼此拉开。松散的硅具有包括六个相等价带的导带。施加到硅的张力会造成六个价带的其中四个价带能量的增加，以及其中两个价带能量的减少。由于量子效应，当电子通过较低的能带时，其有效重量会减少百分的三十。因此，较低能带会给电子流提供较少的阻力。此外，电子会偶然遇到来自硅原子核的较少振动能，其导致它们以小于松散硅中500至1000倍的速率来散射。结果，与松散的硅相比，载流子迁移率在应变硅中会剧烈地增加，其给电子提供80％或更多迁移率的潜在增加，以及给空穴提供20％或更多。已经发现迁移率的增加会一直持续到电流场增加到1.5百万伏特/公分。令人相信的是，这些因素会在器件尺寸没有进一步减少的情形下使器件速度增加35％，或者在性能没有减少的情形下，减少25％的功耗。
因此，图5的结构通过由使用硅锗层70所支撑的应变硅72的外延层而利用应变硅的有利特征。源极和漏极区域58以及沟道区域形成在应变硅72中。因此，以类似图4a至4f所示的方式形成图5的结构，差别是图4a所示的最初层结构有所改变，以致使在半导体衬底40与栅极绝缘层42之间具有硅锗层和应变硅层。硅锗层70较佳的具有合成物Si1-xGex，在此x大约是0.2，而更普遍的范围是0.1至0.3。例如通过使用Si2H6(乙硅烷)与GeH4(锗烷)为源气体的化学气相沉积，以衬底温度是600至900℃，Si2H6的部分压力是30mPa且GeH4的部分压力是60mPa，可以在硅晶片衬底上生长硅锗。硅锗材料的生长可能使用这些比例开始，或者GeH4的部分压力可以从较低压或零压开始逐渐地增加，以形成梯度合成物。然后，例如通过使用Si2H6(乙硅烷)为源气体的化学气相沉积(CVD)，以30mPa的部分压力，大约是600至900℃的衬底温度，随后在硅锗层上生长应变硅层。
图6显示了根据第三较佳具体实施例而设计的结构。图6结构类似图5结构之处在于它利用形成在硅锗晶格上的应变硅。但是，图6结构的应变硅受限于栅极绝缘体48与间隔物56下面的沟道区域74。在形成间隔物56与注入深的源极和漏极区域58以前，可通过将通过蚀刻外延应变硅层替代具有硅锗的蚀刻应变硅而形成这样的结构。或者，在形成栅极绝缘层与覆盖层以前，可以镶嵌的方式形成应变硅沟道区域74。具有硅锗源极和漏极区域的结构(譬如图6结构)的优点在于应变硅的优点会并入于该器件内，而镍锗硅化物的优点则可同样地并入于源极和漏极区域中。此外，因为在硅锗中硼(B)掺杂物扩散的减少，所以就PMOS实施过程中提供源极和漏极几何结构的精确控制而言，此具体实施例可能特别令人希望。
图7显示了根据本发明第四较佳具体实施例而设计的结构。图7的结构为绝缘体上硅(SOI)结构，其通常被称为垂直的双栅极MOSFET或者FinFET。该结构包括形成在绝缘衬底78上的单片半导体体部76。该半导体体部包括源极和漏极区域80以及延伸于源极和漏极区域之间的沟道区域82。栅极84形成于沟道区域82上及其周围，并且通过栅极绝缘体(未显示)而与该沟道区域相隔并且由介质间隔物(未显示)保护而免于接触源极和漏极区域。根据本发明，该栅极包括下部多晶硅部分86与上部多晶硅锗部分88，在该上部多晶硅锗部分形成有镍锗硅化物90。镍硅化物92也可形成在源极和漏极区域上。在一个具体实施例中，半导体体部76由硅组成。在替代性具体实施例中，半导体体部76可由硅锗形成，并且覆盖着层应变硅。在另一替代性具体实施例中，半导体体部76可由硅锗形成，并且仅在沟道区域中覆盖着一层应变硅，从而能够使镍锗硅化物形成在该源极和漏极区域80上。
虽然图4f、5、6和7的MOSFET结构代表目前较佳的具体实施例，但是镍锗硅化物却能相同的应用到其它类型的MOSFET结构。例如，譬如倒置或底部栅极MOSFETS的其它结构，其中该栅极置于该沟道区域下面，其也可以使用镍锗硅化物，以给源极和漏极区域以及栅极提供低的接触电阻。此替代性结构可将应变硅并入沟道区域以及源极和漏极区域。由于上述的较佳具体实施例，镍锗硅化物会尽可能较佳地由镍单硅化物相所包括。
因此应该理解的是，本发明范围内的具体实施例包括各种MOSFET结构，各个结构的特征在于使用镍锗硅化物作为栅极上的或者源极和漏极区域中的硅化物。
图8显示了制造包括前述较佳具体实施例与替代物以及未明确地说明于其中的额外替代性具体实施例的MOSFET的工艺流程。最初提供一半导体衬底(100)。该衬底具有形成于其上的栅极绝缘层，形成于该栅极绝缘层上的多晶硅层，以及形成于该多晶硅层上的多晶硅锗层。随后将该多晶硅锗层、该多晶硅层与该栅极绝缘层图形化，以形成栅极绝缘体和覆盖该栅极绝缘体的栅极(102)。该栅极因而包括下部多晶硅部分与上部多晶硅锗部分。在该栅极的至少该上部多晶硅锗部分上形成镍层(104)。随后进行热处理，以在该栅极上形成镍锗硅化物(106)。要注意的是，在此参考的衬底可能包括半导体衬底，如图4f、5与6中具体实施例所使用的，或者具有预先图形化在其上的半导体体部的绝缘衬底，其如图8具体实施例所使用的。
在进一步的具体实施例中，期望进行其它类型的工艺或者形成不同类型的结构。例如，可较佳地使镍层与譬如钒、钽或钨的其它金属成为合金，以改善锗硅化物的相稳定性。在锗硅化物形成以前，其它的金属可能被注入于镍层内或者可能作为分隔的CVD或PVD层而形成于镍层上。在其它具体实施例中，可能使用多晶硅锗栅极。在进一步具体实施例中，该栅极的多晶硅锗部分可能通过在锗环境中将多晶硅栅极退火或者将锗注入在多晶硅栅极内而形成。在其它的具体实施例中，期望在沉积镍层以前，在氢环境中进行还原以去除氧化物。
本领域普通技术人员应了解的是，以上工艺所说明的工作并不一定不包括其它工作，更确切地，进一步工作可能根据将要形成的特定结构而并入于上述工艺。例如，中间处理工作，譬如处理工作间的钝化层或者保护层的形成与去除、光刻胶掩膜与其它掩膜层的形成与去除、掺杂与反掺杂、清洁、平坦化以及其它工作，可连同以上具体说明的工作而进行。再者，该工艺不需要在譬如整个晶片的整个衬底上进行，但确切地可选择性地在部分衬底上进行。因此，虽然上述以图式表示并说明了具体实施例，但是应该理解到的是，这些具体实施例仅仅经由实例而提供。本发明并不受限于特定具体实施例，但却可延伸到在权利要求内的种种修改、合并与变更及其均等物。

Claims (10)

1.一种用于形成金属氧化物半导体场效应晶体管的方法，包括：
提供具有形成于其上的栅极绝缘层(42)的半导体衬底、形成于该栅极绝缘层上的多晶硅层(44)以及形成于该多晶硅层上的多晶硅锗层(46)；
图形化该多晶硅锗层(46)、该多晶硅层(44)和该栅极绝缘层(42)，以形成栅极绝缘体(48)和覆盖该栅极绝缘体的栅极，该栅极包括下部多晶硅部分(50)与上部多晶硅锗部分(52)；
在该栅极的至少该上部多晶硅锗部分(52)上形成镍层(60)；以及
进行热处理，以在该栅极上形成镍锗硅化物(62)。
2.如权利要求1所述的方法，其中该镍锗硅化物(62)包括镍单硅化物。
3.如权利要求1所述的方法，其中该多晶硅(44)与多晶硅锗(46)在原位置被形成。
4.如权利要求1所述的方法，其中该镍层(60)的形成由以下步骤进行：
注入浅的源极和漏极延伸(54)；
在该栅极周围形成间隔物(56)；
注入深的源极和漏极区域(58)，以及
其中该镍层(60)接触该深的源极和漏极区域(58)，热处理在该源极和漏极区域中形成包括镍与硅(64)的合成物。
5.如权利要求1所述的方法，其中该衬底包括覆盖硅锗层(70)的应变硅的表面层(72)。
6.如权利要求1所述的方法，其中该衬底包括一层硅锗层(70)，该硅锗层(70)具有形成于其中的应变硅沟道区域(74)，在该应变硅沟道区域(74)上图形化该栅极，
其中该金属氧化物半导体场效应晶体管的源极和漏极区域形成在该硅锗层(70)中，以及
其中该镍层(60)接触该源极和漏极区域，而且该热处理在该源极和漏极区域中形成镍锗硅化物(64)。
7.一种金属氧化物半导体场效应晶体管器件，包括：
源极和漏极区域；
延伸于该源极和漏极区域之间的沟道区域；
覆盖该沟道区域的栅极绝缘体(48)；以及
覆盖该栅极绝缘体的多晶金属硅化物栅极，该多晶金属硅化物栅极包括下部多晶硅部分(50)和上部多晶硅锗部分(52)，以及形成在该栅极的上部多晶硅锗部分(52)上的镍锗硅化物(62)。
8.如权利要求7所述的器件，其中该镍锗硅化物(62)包括镍单硅化物。
9.如权利要求7所述的器件，其中该源极和漏极区域以及该沟道区域包括形成在绝缘层(78)上的半导体体部(76)，由此包括绝缘体上硅金属氧化物半导体场效应晶体管。
10.一种金属氧化物半导体场效晶体管，包括：
源极和漏极区域；
延伸于该源极和漏极区域之间的沟道区域；
覆盖该沟道区域的栅极绝缘体(48)；以及
覆盖该栅极绝缘体的多晶金属硅化物栅极，
其中该多晶金属硅化物栅极与该源极和漏极区域的至少其中一个包括镍锗硅化物(62，64)。
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