JP4651298B2 - 周波数自動補正pll回路 - Google Patents
周波数自動補正pll回路 Download PDFInfo
- Publication number
- JP4651298B2 JP4651298B2 JP2004113725A JP2004113725A JP4651298B2 JP 4651298 B2 JP4651298 B2 JP 4651298B2 JP 2004113725 A JP2004113725 A JP 2004113725A JP 2004113725 A JP2004113725 A JP 2004113725A JP 4651298 B2 JP4651298 B2 JP 4651298B2
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- Prior art keywords
- threshold
- low
- circuit
- comparator
- state
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/104—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional signal from outside the loop for setting or controlling a parameter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004113725A JP4651298B2 (ja) | 2004-04-08 | 2004-04-08 | 周波数自動補正pll回路 |
| US11/087,591 US7519140B2 (en) | 2004-04-08 | 2005-03-24 | Automatic frequency correction PLL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004113725A JP4651298B2 (ja) | 2004-04-08 | 2004-04-08 | 周波数自動補正pll回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005303483A JP2005303483A (ja) | 2005-10-27 |
| JP2005303483A5 JP2005303483A5 (enExample) | 2007-04-19 |
| JP4651298B2 true JP4651298B2 (ja) | 2011-03-16 |
Family
ID=35060526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004113725A Expired - Lifetime JP4651298B2 (ja) | 2004-04-08 | 2004-04-08 | 周波数自動補正pll回路 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7519140B2 (enExample) |
| JP (1) | JP4651298B2 (enExample) |
Families Citing this family (55)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7164322B1 (en) * | 2005-07-21 | 2007-01-16 | Agilent Technologies, Inc. | Establishing a tuning signal window for use in centering a multi-band voltage controlled oscillator |
| JP5027472B2 (ja) * | 2005-11-09 | 2012-09-19 | ルネサスエレクトロニクス株式会社 | 発振器およびそれを用いた情報機器 |
| US7663415B2 (en) * | 2005-12-30 | 2010-02-16 | Stmicroelectronics Pvt. Ltd. | Phase locked loop (PLL) method and architecture |
| EP1833215A1 (en) * | 2006-03-10 | 2007-09-12 | Harris Broadcast Systems Europe | Detection of excessive signal power |
| KR100738360B1 (ko) | 2006-05-11 | 2007-07-12 | 한국과학기술원 | 고속 개루프 자동 주파수 보정 회로를 가지는 위상 고정루프 |
| JP4767085B2 (ja) * | 2006-05-16 | 2011-09-07 | 富士通セミコンダクター株式会社 | 周波数シンセサイザ、および周波数シンセサイザの発振制御方法 |
| ITMI20061272A1 (it) * | 2006-06-30 | 2008-01-01 | St Microelectronics Srl | Metodo di tuning dinamico della frequenza di temporizzazione (clock) in un oscillatore e relativo sistema oscillatore. |
| JP4866707B2 (ja) * | 2006-11-10 | 2012-02-01 | パナソニック株式会社 | Pll回路及び信号送受信システム |
| US7808288B2 (en) * | 2006-12-28 | 2010-10-05 | Stmicroelectronics, Pvt. Ltd. | System and method for an automatic coarse tuning of a voltage controlled oscillator in a phase-locked loop (PLL) |
| JP5104851B2 (ja) * | 2007-03-19 | 2012-12-19 | 富士通株式会社 | 電圧制御発振器およびシンセサイザ回路 |
| KR100869227B1 (ko) * | 2007-04-04 | 2008-11-18 | 삼성전자주식회사 | 프리 캘리브레이션 모드를 가진 위상동기루프 회로 및위상동기루프 회로의 프리 캘리브레이션 방법 |
| JP4971861B2 (ja) * | 2007-04-13 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | クロックアンドデータリカバリ回路 |
| US7940128B2 (en) * | 2007-09-17 | 2011-05-10 | Synopsys, Inc. | High speed PLL clock multiplier |
| US7696798B2 (en) * | 2008-02-08 | 2010-04-13 | Sun Microsystems, Inc. | Method and apparatus to generate system clock synchronization pulses using a PLL lock detect signal |
| JP2009232072A (ja) * | 2008-03-21 | 2009-10-08 | Toyota Industries Corp | Pll回路 |
| US7940140B2 (en) * | 2008-06-03 | 2011-05-10 | Lsi Corporation | Self-calibrated wide range LC tank voltage-controlled oscillator (VCO) system with expanded frequency tuning range and method for providing same |
| US8422594B2 (en) * | 2009-05-26 | 2013-04-16 | Infineon Technologies Ag | Circuit for demodulating a phase modulated signal |
| US8140040B1 (en) * | 2009-09-11 | 2012-03-20 | Qualcomm Atheros, Inc | Method and apparatus for a temperature compensated phase locked loop supporting a continuous stream receiver in an integrated circuit |
| JP5503990B2 (ja) * | 2010-02-02 | 2014-05-28 | ローム株式会社 | 位相ロックループ回路およびそれを用いた電子機器 |
| US8203374B2 (en) * | 2010-05-06 | 2012-06-19 | Aeroflex Colorado Springs Inc. | Electrically tunable continuous-time circuit and method for compensating a polynomial voltage-dependent characteristic of capacitance |
| US8421542B2 (en) * | 2010-05-28 | 2013-04-16 | Marvell World Trade Ltd. | Method and apparatus for drift compensation in PLL |
| US8531222B1 (en) * | 2011-04-04 | 2013-09-10 | Lattice Semiconductor Corporation | Phase locked loop circuit with selectable feedback paths |
| US8754682B2 (en) * | 2011-04-21 | 2014-06-17 | Stmicroelectronics (Canada) Inc. | Fractional divider for avoidance of LC-VCO interference and jitter |
| US8508308B2 (en) * | 2011-09-01 | 2013-08-13 | Lsi Corporation | Automatic frequency calibration of a multi-LCVCO phase locked loop with adaptive thresholds and programmable center control voltage |
| US8666012B2 (en) | 2011-10-20 | 2014-03-04 | Broadcom Corporation | Operating a frequency synthesizer |
| US8456207B1 (en) * | 2011-11-16 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lock detector and method of detecting lock status for phase lock loop |
| US8816732B2 (en) * | 2012-06-22 | 2014-08-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Capactive load PLL with calibration loop |
| US8618840B1 (en) * | 2012-07-11 | 2013-12-31 | Fujitsu Limited | Frequency synthesizer tuning |
| US20140035684A1 (en) * | 2012-07-31 | 2014-02-06 | Research & Business Foundation Sungkyunkwan University | Control circuit and apparatus for digitally controlled oscillator |
| JP6034663B2 (ja) * | 2012-11-01 | 2016-11-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| CN103812504B (zh) * | 2012-11-06 | 2017-03-01 | 瑞昱半导体股份有限公司 | 相位校正装置及相位校正方法 |
| US9083356B1 (en) * | 2013-03-14 | 2015-07-14 | Gsi Technology, Inc. | Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features |
| ITTO20130347A1 (it) * | 2013-04-29 | 2014-10-30 | St Microelectronics Srl | Circuito e metodo di calibrazione per un oscillatore controllato digitalmente |
| US9705514B2 (en) * | 2013-11-27 | 2017-07-11 | Silicon Laboratories Inc. | Hybrid analog and digital control of oscillator frequency |
| US9413366B2 (en) * | 2013-12-19 | 2016-08-09 | Analog Devices Global | Apparatus and methods for phase-locked loops with temperature compensated calibration voltage |
| US9484935B2 (en) * | 2013-12-19 | 2016-11-01 | Analog Devices Global | Apparatus and methods for frequency lock enhancement of phase-locked loops |
| US10860320B1 (en) | 2016-12-06 | 2020-12-08 | Gsi Technology, Inc. | Orthogonal data transposition system and method during data transfers to/from a processing array |
| US10770133B1 (en) | 2016-12-06 | 2020-09-08 | Gsi Technology, Inc. | Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits |
| US10860318B2 (en) | 2016-12-06 | 2020-12-08 | Gsi Technology, Inc. | Computational memory cell and processing array device using memory cells |
| US10998040B2 (en) | 2016-12-06 | 2021-05-04 | Gsi Technology, Inc. | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations |
| US10891076B1 (en) | 2016-12-06 | 2021-01-12 | Gsi Technology, Inc. | Results processing circuits and methods associated with computational memory cells |
| US10854284B1 (en) | 2016-12-06 | 2020-12-01 | Gsi Technology, Inc. | Computational memory cell and processing array device with ratioless write port |
| US10943648B1 (en) | 2016-12-06 | 2021-03-09 | Gsi Technology, Inc. | Ultra low VDD memory cell with ratioless write port |
| US10847212B1 (en) | 2016-12-06 | 2020-11-24 | Gsi Technology, Inc. | Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers |
| US10847213B1 (en) | 2016-12-06 | 2020-11-24 | Gsi Technology, Inc. | Write data processing circuits and methods associated with computational memory cells |
| US11227653B1 (en) | 2016-12-06 | 2022-01-18 | Gsi Technology, Inc. | Storage array circuits and methods for computational memory cells |
| US10777262B1 (en) | 2016-12-06 | 2020-09-15 | Gsi Technology, Inc. | Read data processing circuits and methods associated memory cells |
| JP6872434B2 (ja) * | 2017-06-15 | 2021-05-19 | ルネサスエレクトロニクス株式会社 | 無線信号処理装置、半導体装置、及び発振周波数変動補正方法 |
| TWI649974B (zh) * | 2018-05-25 | 2019-02-01 | 茂達電子股份有限公司 | 具自動校正功能的數位鎖相迴路及其自動校正方法 |
| TWI666879B (zh) * | 2018-05-25 | 2019-07-21 | 茂達電子股份有限公司 | 快速鎖定的數位鎖相迴路及其快速鎖定方法 |
| US10877731B1 (en) | 2019-06-18 | 2020-12-29 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
| US10958272B2 (en) | 2019-06-18 | 2021-03-23 | Gsi Technology, Inc. | Computational memory cell and processing array device using complementary exclusive or memory cells |
| US10930341B1 (en) | 2019-06-18 | 2021-02-23 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
| US12308844B2 (en) * | 2021-11-22 | 2025-05-20 | Intel Corporation | Adaptive cyclic delay line for fractional-N PLL |
| CN114301455B (zh) * | 2021-12-27 | 2026-01-09 | 厦门科塔电子有限公司 | 自动频率校正及频率锁定检测电路 |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0799807B2 (ja) * | 1990-03-09 | 1995-10-25 | 株式会社東芝 | 位相同期回路 |
| JPH0563600A (ja) * | 1991-08-30 | 1993-03-12 | Fujitsu Ltd | 半導体集積回路装置 |
| JP3453006B2 (ja) * | 1995-07-07 | 2003-10-06 | パイオニア株式会社 | 位相同期回路及びディジタル信号再生装置 |
| JP3280556B2 (ja) * | 1995-11-08 | 2002-05-13 | カルソニックカンセイ株式会社 | 位置決め装置 |
| JPH09214335A (ja) * | 1996-02-01 | 1997-08-15 | Nippon Telegr & Teleph Corp <Ntt> | 半導体集積回路 |
| JPH10208253A (ja) * | 1997-01-24 | 1998-08-07 | Sharp Corp | ディスク再生装置 |
| JP3250484B2 (ja) * | 1997-04-08 | 2002-01-28 | 株式会社デンソー | 電圧制御発振回路 |
| IT1295950B1 (it) * | 1997-11-06 | 1999-05-28 | Cselt Centro Studi Lab Telecom | Circuito ad aggancio di fase. |
| JP3591704B2 (ja) * | 1999-06-30 | 2004-11-24 | パイオニア株式会社 | Dab受信機 |
| JP3627609B2 (ja) * | 2000-01-25 | 2005-03-09 | 株式会社デンソー | 車両用乗員保護システムのための起動装置 |
| JP2002237728A (ja) * | 2001-02-07 | 2002-08-23 | Nec Wireless Networks Ltd | 受信増幅装置および受信増幅装置の増幅素子保護方法 |
| JP4342754B2 (ja) * | 2001-09-07 | 2009-10-14 | 株式会社リコー | Pll回路 |
| JP3808343B2 (ja) * | 2001-10-03 | 2006-08-09 | 三菱電機株式会社 | Pll回路 |
| JP2003133949A (ja) * | 2001-10-23 | 2003-05-09 | Fujitsu Ltd | Pll回路 |
| US6753711B2 (en) * | 2002-06-26 | 2004-06-22 | Comtech Ef Data | Digital summing phase-lock loop circuit with sideband control and method therefor |
| JP4316198B2 (ja) * | 2002-07-24 | 2009-08-19 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置、受信機及び半導体装置の制御方法 |
| DE60328925D1 (de) * | 2002-12-24 | 2009-10-01 | Fujitsu Microelectronics Ltd | Jittergenerator |
| JPWO2005060131A1 (ja) * | 2003-12-05 | 2007-07-12 | 日本電信電話株式会社 | リアクタンス調整器、これを用いたトランシーバおよび送信装置、並びにこれらに好適な信号処理回路、並びにリアクタンス調整方法、送信方法、および受信方法 |
| TWI240915B (en) * | 2003-12-30 | 2005-10-01 | Mediatek Inc | Method and apparatus for detecting position of blank area for an optical disk |
-
2004
- 2004-04-08 JP JP2004113725A patent/JP4651298B2/ja not_active Expired - Lifetime
-
2005
- 2005-03-24 US US11/087,591 patent/US7519140B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US7519140B2 (en) | 2009-04-14 |
| US20050226357A1 (en) | 2005-10-13 |
| JP2005303483A (ja) | 2005-10-27 |
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