IT1295950B1 - Circuito ad aggancio di fase. - Google Patents

Circuito ad aggancio di fase.

Info

Publication number
IT1295950B1
IT1295950B1 IT97TO000970A ITTO970970A IT1295950B1 IT 1295950 B1 IT1295950 B1 IT 1295950B1 IT 97TO000970 A IT97TO000970 A IT 97TO000970A IT TO970970 A ITTO970970 A IT TO970970A IT 1295950 B1 IT1295950 B1 IT 1295950B1
Authority
IT
Italy
Prior art keywords
phase lock
lock circuit
circuit
phase
lock
Prior art date
Application number
IT97TO000970A
Other languages
English (en)
Inventor
Marco Burzio
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Priority to IT97TO000970A priority Critical patent/IT1295950B1/it
Publication of ITTO970970A0 publication Critical patent/ITTO970970A0/it
Priority to US09/156,930 priority patent/US6127896A/en
Priority to JP10324400A priority patent/JPH11225070A/ja
Priority to DE69824114T priority patent/DE69824114T2/de
Priority to EP98120641A priority patent/EP0915568B1/en
Priority to CA002253583A priority patent/CA2253583C/en
Publication of ITTO970970A1 publication Critical patent/ITTO970970A1/it
Application granted granted Critical
Publication of IT1295950B1 publication Critical patent/IT1295950B1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H03L7/102—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
IT97TO000970A 1997-11-06 1997-11-06 Circuito ad aggancio di fase. IT1295950B1 (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT97TO000970A IT1295950B1 (it) 1997-11-06 1997-11-06 Circuito ad aggancio di fase.
US09/156,930 US6127896A (en) 1997-11-06 1998-09-18 Phase locked loop having control circuit for automatically operating VCO on an optimum input/output characteristic
JP10324400A JPH11225070A (ja) 1997-11-06 1998-10-30 フェーズロックドループ
DE69824114T DE69824114T2 (de) 1997-11-06 1998-11-03 Phasenregelkreis und Verfahren zum Steuern des Phasenregelkreises
EP98120641A EP0915568B1 (en) 1997-11-06 1998-11-03 Phase locked loop and method of controlling it
CA002253583A CA2253583C (en) 1997-11-06 1998-11-04 Phase locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT97TO000970A IT1295950B1 (it) 1997-11-06 1997-11-06 Circuito ad aggancio di fase.

Publications (3)

Publication Number Publication Date
ITTO970970A0 ITTO970970A0 (it) 1997-11-06
ITTO970970A1 ITTO970970A1 (it) 1999-05-06
IT1295950B1 true IT1295950B1 (it) 1999-05-28

Family

ID=11416118

Family Applications (1)

Application Number Title Priority Date Filing Date
IT97TO000970A IT1295950B1 (it) 1997-11-06 1997-11-06 Circuito ad aggancio di fase.

Country Status (6)

Country Link
US (1) US6127896A (it)
EP (1) EP0915568B1 (it)
JP (1) JPH11225070A (it)
CA (1) CA2253583C (it)
DE (1) DE69824114T2 (it)
IT (1) IT1295950B1 (it)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3573975B2 (ja) * 1998-10-23 2004-10-06 日本オプネクスト株式会社 光受信器、位相同期ループ回路、電圧制御発振器および周波数応答可変増幅器
IT1303599B1 (it) * 1998-12-11 2000-11-14 Cselt Ct Studi E Lab T Circuito ad aggancio di fase.
US6674331B2 (en) 2001-11-09 2004-01-06 Agere Systems, Inc. Method and apparatus for simplified tuning of a two-point modulated PLL
US7187220B1 (en) * 2003-12-18 2007-03-06 Nvidia Corporation Memory clock slowdown
US7315957B1 (en) 2003-12-18 2008-01-01 Nvidia Corporation Method of providing a second clock while changing a first supplied clock frequency then supplying the changed first clock
JP4651298B2 (ja) * 2004-04-08 2011-03-16 三菱電機株式会社 周波数自動補正ｐｌｌ回路
DE102004063935A1 (de) * 2004-07-01 2006-03-30 Krohne Meßtechnik GmbH & Co KG Frequenzsynthesizer und Verfahren zum Betrieb eines Frequenzsynthesizers
TWI296464B (en) * 2005-06-20 2008-05-01 Airoha Tech Corp Phase lock loop and operating method thereof
US9262837B2 (en) 2005-10-17 2016-02-16 Nvidia Corporation PCIE clock rate stepping for graphics and platform processors
US7336110B1 (en) 2007-01-17 2008-02-26 Atmel Corporation Differential amplitude controlled sawtooth generator
US7671642B2 (en) * 2006-12-13 2010-03-02 Atmel Corporation Amplitude controlled sawtooth generator
US20090153252A1 (en) * 2007-12-13 2009-06-18 Mei-Show Chen Multi-band voltage controlled oscillator controlling module, phase locked loop utilizing which and related method thereof
US7834708B1 (en) * 2008-04-30 2010-11-16 Integrated Device Technology, Inc. Method and apparatus for analog smooth switch in VCO loading control

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799807B2 (ja) * 1990-03-09 1995-10-25 株式会社東芝 位相同期回路
DE4031939A1 (de) * 1990-10-09 1992-05-07 Rohde & Schwarz Verfahren zum voreinstellen eines phasengeregelten oszillators auf einen vorgegebenen frequenzwert
US5257294A (en) * 1990-11-13 1993-10-26 National Semiconductor Corporation Phase-locked loop circuit and method
KR940005459A (ko) * 1992-06-22 1994-03-21 모리시타 요이찌 Pll회로
US5331292A (en) * 1992-07-16 1994-07-19 National Semiconductor Corporation Autoranging phase-lock-loop circuit
US5422603A (en) * 1994-06-02 1995-06-06 International Business Machines Corporation CMOS frequency synthesizer

Also Published As

Publication number Publication date
EP0915568A3 (en) 2000-07-19
JPH11225070A (ja) 1999-08-17
DE69824114D1 (de) 2004-07-01
US6127896A (en) 2000-10-03
ITTO970970A0 (it) 1997-11-06
EP0915568B1 (en) 2004-05-26
EP0915568A2 (en) 1999-05-12
CA2253583C (en) 2001-05-15
DE69824114T2 (de) 2005-07-07
CA2253583A1 (en) 1999-05-06
ITTO970970A1 (it) 1999-05-06

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Legal Events

Date Code Title Description
0001 Granted