JP4615839B2 - 不揮発性メモリ装置 - Google Patents
不揮発性メモリ装置 Download PDFInfo
- Publication number
- JP4615839B2 JP4615839B2 JP2003336151A JP2003336151A JP4615839B2 JP 4615839 B2 JP4615839 B2 JP 4615839B2 JP 2003336151 A JP2003336151 A JP 2003336151A JP 2003336151 A JP2003336151 A JP 2003336151A JP 4615839 B2 JP4615839 B2 JP 4615839B2
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- JP
- Japan
- Prior art keywords
- memory element
- write
- resistance
- state
- nonvolatile
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Description
ハイデータが貯蔵されているとき、入力信号に応じるロジックスイッチSW2の動作状態を表わす。
ローデータが貯蔵されているとき、入力信号に応じるロジックスイッチSW2の動作状態を表わす。
30 フリップフロップ部
Claims (6)
- 書き込み動作時に位相が互いに逆の書込み制御信号の状態に応じて得られる書込み/読取り制御信号の出力を選択的に制御する書込み/読取り制御部と、
前記書込み/読取り制御信号が得られるときに電流の大きさに応じて変化する抵抗の状態に基づいて互いに異なる論理値を貯蔵する不揮発性抵抗記憶素子と、
前記書込み/読取り制御信号が得られないときに前記不揮発性抵抗記憶素子に既に貯蔵された互いに異なる前記論理値に応じてスイッチング状態が定められるロジックスイッチを備えることを特徴とする不揮発性メモリ装置。 - 前記書込み/読取り制御部は、
第1の書込み制御信号の状態に応じてスイッチング制御される第1のNMOSトランジスタと、
前記第1のNMOSトランジスタに並列連結され、前記第1の書込み制御信号と位相が互いに逆の第2の書込み制御信号の状態に応じてスイッチング制御される第1のPMOSトランジスタとを備えることを特徴とする請求項1に記載の不揮発性メモリ装置。 - 前記不揮発性抵抗記憶素子は、第1の入力ノードと前記書込み/読取り
制御部の出力ノードの間に連結された第1の抵抗記憶素子と、 第2の入力ノードと前記書込み/読取り制御部の出力ノードの間に連結された第2の抵抗記憶素子とを備えることを特徴とする請求項1に記載の不揮発性メモリ装置。 - 前記不揮発性抵抗記憶素子は、
前記第1の抵抗記憶素子が低抵抗状態にて前記第2の抵抗記憶素子が高抵抗状態のとき前記第1の抵抗記憶素子に入力される第1の入力信号の状態に応じて前記ロジックスイッチのスイッチング状態が決定され、前記第1の抵抗記憶素子が高抵抗状態にて前記第2の抵抗記憶素子が低抵抗状態のとき前記第2の抵抗記憶素子に入力される第2の入力信号の状態に応じて前記ロジックスイッチのスイッチング状態が定められることを特徴とする請求項3に記載の不揮発性メモリ装置。 - 前記第1の抵抗記憶素子及び第2の抵抗記憶素子がそれぞれ前記第1の入力ノード又は前記第2の入力ノードと連結された第1の電極、
前記書込み/読取り制御部の出力ノードと連結された第2の電極、及び
前記第1の電極と第2の電極との間に形成された位相変化層を備えることを特徴とする請求項4に記載の不揮発性メモリ装置。 - 前記不揮発性抵抗記憶素子が位相変化メモリ素子、磁気抵抗素子及びメタルメモリ素子のうち少なくとも何れか1つを備えることを特徴とする請求項1に記載の不揮発性メモリ装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0086704A KR100479810B1 (ko) | 2002-12-30 | 2002-12-30 | 불휘발성 메모리 장치 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010088786A Division JP5180986B2 (ja) | 2002-12-30 | 2010-04-07 | 不揮発性メモリ装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004213860A JP2004213860A (ja) | 2004-07-29 |
JP4615839B2 true JP4615839B2 (ja) | 2011-01-19 |
Family
ID=32588934
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003336151A Expired - Fee Related JP4615839B2 (ja) | 2002-12-30 | 2003-09-26 | 不揮発性メモリ装置 |
JP2010088786A Expired - Fee Related JP5180986B2 (ja) | 2002-12-30 | 2010-04-07 | 不揮発性メモリ装置 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010088786A Expired - Fee Related JP5180986B2 (ja) | 2002-12-30 | 2010-04-07 | 不揮発性メモリ装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6944050B2 (ja) |
JP (2) | JP4615839B2 (ja) |
KR (1) | KR100479810B1 (ja) |
CN (1) | CN1224107C (ja) |
DE (1) | DE10335065A1 (ja) |
TW (1) | TWI239013B (ja) |
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2002
- 2002-12-30 KR KR10-2002-0086704A patent/KR100479810B1/ko not_active IP Right Cessation
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2003
- 2003-07-30 US US10/629,903 patent/US6944050B2/en not_active Expired - Lifetime
- 2003-07-31 TW TW092121016A patent/TWI239013B/zh not_active IP Right Cessation
- 2003-07-31 DE DE10335065A patent/DE10335065A1/de not_active Ceased
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- 2003-09-26 JP JP2003336151A patent/JP4615839B2/ja not_active Expired - Fee Related
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2001273758A (ja) * | 2000-03-27 | 2001-10-05 | Sharp Corp | 磁気メモリ |
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US20040125643A1 (en) | 2004-07-01 |
JP2004213860A (ja) | 2004-07-29 |
KR100479810B1 (ko) | 2005-03-31 |
JP2010176843A (ja) | 2010-08-12 |
TWI239013B (en) | 2005-09-01 |
US6944050B2 (en) | 2005-09-13 |
KR20040060169A (ko) | 2004-07-06 |
JP5180986B2 (ja) | 2013-04-10 |
DE10335065A1 (de) | 2004-07-22 |
CN1512591A (zh) | 2004-07-14 |
TW200411672A (en) | 2004-07-01 |
CN1224107C (zh) | 2005-10-19 |
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