JP4583694B2 - パイプラインアナログ−デジタル（ａ／ｄ）変換器のためのデジタル論理訂正回路 - Google Patents

パイプラインアナログ−デジタル（ａ／ｄ）変換器のためのデジタル論理訂正回路 Download PDF

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Publication number
JP4583694B2
JP4583694B2 JP2001560540A JP2001560540A JP4583694B2 JP 4583694 B2 JP4583694 B2 JP 4583694B2 JP 2001560540 A JP2001560540 A JP 2001560540A JP 2001560540 A JP2001560540 A JP 2001560540A JP 4583694 B2 JP4583694 B2 JP 4583694B2
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Japan
Prior art keywords
digital
converter
mdac
stage
circuit
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Expired - Fee Related
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JP2001560540A
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Japanese (ja)
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JP2003523679A (ja
JP2003523679A5 (enExample
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チアン，メーイ−リン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
    • H03M1/0695—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
    • H03M1/442—Sequential comparisons in series-connected stages with change in value of analogue signal using switched capacitors

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
JP2001560540A 2000-02-17 2000-08-25 パイプラインアナログ−デジタル（ａ／ｄ）変換器のためのデジタル論理訂正回路 Expired - Fee Related JP4583694B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/506,037 2000-02-17
US09/506,037 US6359579B1 (en) 2000-02-17 2000-02-17 Digital logic correction circuit for a pipeline analog to digital (A/D) converter
PCT/US2000/023456 WO2001061860A1 (en) 2000-02-17 2000-08-25 Digital logic correction circuit for a pipeline analog to digital (a/d) converter

Publications (3)

Publication Number Publication Date
JP2003523679A JP2003523679A (ja) 2003-08-05
JP2003523679A5 JP2003523679A5 (enExample) 2007-09-13
JP4583694B2 true JP4583694B2 (ja) 2010-11-17

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Family Applications (1)

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JP2001560540A Expired - Fee Related JP4583694B2 (ja) 2000-02-17 2000-08-25 パイプラインアナログ−デジタル（ａ／ｄ）変換器のためのデジタル論理訂正回路

Country Status (7)

Country Link
US (1) US6359579B1 (enExample)
EP (1) EP1256173A1 (enExample)
JP (1) JP4583694B2 (enExample)
KR (1) KR100647885B1 (enExample)
CN (1) CN1199356C (enExample)
TW (1) TW469704B (enExample)
WO (1) WO2001061860A1 (enExample)

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US6784814B1 (en) 2003-03-07 2004-08-31 Regents Of The University Of Minnesota Correction for pipelined analog to digital (A/D) converter
JP3843105B2 (ja) * 2003-03-26 2006-11-08 三洋電機株式会社 アナログ−デジタル変換回路および画像処理回路
KR20050019676A (ko) * 2003-08-20 2005-03-03 이화트론 주식회사 인터넷 위성방송을 위한 디지털 인터넷 비디오 익스프레스시스템
US7065666B2 (en) * 2003-11-13 2006-06-20 Micron Technology, Inc. Apparatus and method for generating a delayed clock signal
JP3785175B2 (ja) * 2004-03-30 2006-06-14 株式会社東芝 多入力ａ／ｄ変換装置及びこれを用いた無線受信機
US8074051B2 (en) 2004-04-07 2011-12-06 Aspen Acquisition Corporation Multithreaded processor with multiple concurrent pipelines per thread
US6933875B1 (en) * 2004-11-08 2005-08-23 United Microelectronics Corp. Pipelined analog-to-digital converter with unequal work timing
US7417574B2 (en) * 2004-12-13 2008-08-26 Texas Instruments Incorporated Efficient amplifier sharing in a multi-stage analog to digital converter
JP4579726B2 (ja) * 2005-03-14 2010-11-10 株式会社エヌ・ティ・ティ・ドコモ 移動通信端末
US7280064B2 (en) * 2005-09-08 2007-10-09 Realtek Semiconductor Corp. Pipeline ADC with minimum overhead digital error correction
KR100843554B1 (ko) * 2006-08-31 2008-07-04 삼성전자주식회사 멀티-채널 파이프라인드 신호 변환기
US8704581B2 (en) * 2007-04-23 2014-04-22 Qualcomm Incorporated Switched capacitor integration and summing circuits
US7414564B1 (en) 2007-06-18 2008-08-19 Analog Devices, Inc. Enhanced-accuracy converter stages for pipelined signal converter systems
KR101140349B1 (ko) 2008-09-16 2012-05-03 한국전자통신연구원 다단 연속 근사 레지스터 아날로그 디지털 변환기
JP5417993B2 (ja) * 2009-06-01 2014-02-19 日本テキサス・インスツルメンツ株式会社 アナログ−デジタル変換回路
JP2011071966A (ja) * 2009-08-24 2011-04-07 Kyushu Institute Of Technology パイプライン型アナログデジタル変換装置
JP5565903B2 (ja) * 2010-05-06 2014-08-06 ローム株式会社 スイッチドキャパシタ利得段
KR101685011B1 (ko) 2010-12-09 2016-12-14 한국전자통신연구원 파이프라인 아날로그 디지털 변환기
TWI489785B (zh) * 2011-08-31 2015-06-21 Pixart Imaging Inc 管線式類比數位轉換器及其方法
US8779957B2 (en) 2012-08-02 2014-07-15 Qualcomm Incorporated Low distortion feed-forward delta-sigma modulator
KR101666275B1 (ko) * 2014-06-26 2016-10-14 한국과학기술원 타임 레지스터를 이용한 시간-디지털 변환 장치 및 그 방법
CN104270151B (zh) * 2014-09-22 2017-05-03 电子科技大学 一种用于流水线模数转换器的输出延时电路
KR101986938B1 (ko) * 2017-10-26 2019-06-07 고려대학교 세종산학협력단 다이나믹 레퍼런스 및 2단 샘플앤드홀드를 이용한 고속, 저전력 파이프라인드 아날로그-디지털 변환기
US11438005B2 (en) * 2020-02-26 2022-09-06 Analog Devices International Unlimited Company Timing methods for SAR ADCs
CN114696829B (zh) * 2020-12-28 2024-07-02 北京特邦微电子科技有限公司 模数转换电路及流水线模数转换器
CN115580299A (zh) * 2021-07-06 2023-01-06 瑞昱半导体股份有限公司 管线式模拟数字转换器与信号转换方法
WO2025013417A1 (ja) * 2023-07-11 2025-01-16 ソニーセミコンダクタソリューションズ株式会社 アナログデジタル変換器、集積回路、および、アナログデジタル変換器の制御方法

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US5043732A (en) * 1989-09-26 1991-08-27 Analog Devices, Inc. Analog-to-digital converter employing a pipeline multi-stage architecture
US4994808A (en) 1989-12-14 1991-02-19 Wichelman Karl F Pipelined analog to digital converter with summing and comparator functions occurring in parallel for each bit
US5047772A (en) * 1990-06-04 1991-09-10 General Electric Company Digital error correction system for subranging analog-to-digital converters
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JPH05218868A (ja) 1992-02-03 1993-08-27 Hitachi Ltd 多段型ａｄ変換器
JP2945805B2 (ja) 1992-10-01 1999-09-06 松下電器産業株式会社 Ａ／ｄ変換器
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US5572212A (en) 1995-03-31 1996-11-05 Exar Corporation Pipelined analog to digital converter
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KR0157122B1 (ko) 1995-12-23 1999-02-18 김광호 디지탈 보상형 아날로그 디지탈 변환기
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US5771012A (en) * 1996-09-11 1998-06-23 Harris Corporation Integrated circuit analog-to-digital converter and associated calibration method and apparatus
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US5710563A (en) * 1997-01-09 1998-01-20 National Semiconductor Corporation Pipeline analog to digital converter architecture with reduced mismatch error
US5861832A (en) 1997-03-27 1999-01-19 Lucent Technologies Inc. Analog-to-digital converter having amplifier and comparator stages
US6166675A (en) * 1997-09-03 2000-12-26 Texas Instruments Incorporated Pipeline analog-to-digital conversion system using double sampling and method of operation
JP3384717B2 (ja) * 1997-09-04 2003-03-10 三洋電機株式会社 アナログ−デジタル変換回路
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Also Published As

Publication number Publication date
KR100647885B1 (ko) 2006-11-23
KR20020079862A (ko) 2002-10-19
US6359579B1 (en) 2002-03-19
CN1435010A (zh) 2003-08-06
JP2003523679A (ja) 2003-08-05
EP1256173A1 (en) 2002-11-13
WO2001061860A1 (en) 2001-08-23
CN1199356C (zh) 2005-04-27
TW469704B (en) 2001-12-21

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