TW469704B - Digital logic correction circuit for a pipeline analog to digital (A/D) converter - Google Patents
Digital logic correction circuit for a pipeline analog to digital (A/D) converter Download PDFInfo
- Publication number
- TW469704B TW469704B TW089118028A TW89118028A TW469704B TW 469704 B TW469704 B TW 469704B TW 089118028 A TW089118028 A TW 089118028A TW 89118028 A TW89118028 A TW 89118028A TW 469704 B TW469704 B TW 469704B
- Authority
- TW
- Taiwan
- Prior art keywords
- digital
- signal
- converter
- output
- timing
- Prior art date
Links
- 238000012937 correction Methods 0.000 title claims abstract description 31
- 230000003111 delayed effect Effects 0.000 claims abstract description 15
- 238000005070 sampling Methods 0.000 claims description 30
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- 230000014509 gene expression Effects 0.000 claims description 7
- 230000001934 delay Effects 0.000 claims description 5
- 230000009471 action Effects 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 3
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 1
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- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 35
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- 238000010586 diagram Methods 0.000 description 21
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- 238000000034 method Methods 0.000 description 15
- 239000003990 capacitor Substances 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- 230000005540 biological transmission Effects 0.000 description 9
- 238000004364 calculation method Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
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- 230000033228 biological regulation Effects 0.000 description 4
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- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
- H03M1/0695—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
- H03M1/442—Sequential comparisons in series-connected stages with change in value of analogue signal using switched capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/506,037 US6359579B1 (en) | 2000-02-17 | 2000-02-17 | Digital logic correction circuit for a pipeline analog to digital (A/D) converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW469704B true TW469704B (en) | 2001-12-21 |
Family
ID=24012906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089118028A TW469704B (en) | 2000-02-17 | 2000-09-04 | Digital logic correction circuit for a pipeline analog to digital (A/D) converter |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6359579B1 (enExample) |
| EP (1) | EP1256173A1 (enExample) |
| JP (1) | JP4583694B2 (enExample) |
| KR (1) | KR100647885B1 (enExample) |
| CN (1) | CN1199356C (enExample) |
| TW (1) | TW469704B (enExample) |
| WO (1) | WO2001061860A1 (enExample) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6700523B2 (en) * | 2001-10-25 | 2004-03-02 | Oki Electric Industry Co., Ltd. | Analog to digital converter selecting reference voltages in accordance with feedback from prior stages |
| KR100460700B1 (ko) * | 2002-10-15 | 2004-12-09 | 한국전자통신연구원 | 아날로그-디지털 변환기의 디지털 오류 교정 방법 |
| US6784814B1 (en) | 2003-03-07 | 2004-08-31 | Regents Of The University Of Minnesota | Correction for pipelined analog to digital (A/D) converter |
| JP3843105B2 (ja) * | 2003-03-26 | 2006-11-08 | 三洋電機株式会社 | アナログ−デジタル変換回路および画像処理回路 |
| KR20050019676A (ko) * | 2003-08-20 | 2005-03-03 | 이화트론 주식회사 | 인터넷 위성방송을 위한 디지털 인터넷 비디오 익스프레스시스템 |
| US7065666B2 (en) * | 2003-11-13 | 2006-06-20 | Micron Technology, Inc. | Apparatus and method for generating a delayed clock signal |
| JP3785175B2 (ja) * | 2004-03-30 | 2006-06-14 | 株式会社東芝 | 多入力ａ／ｄ変換装置及びこれを用いた無線受信機 |
| US8074051B2 (en) | 2004-04-07 | 2011-12-06 | Aspen Acquisition Corporation | Multithreaded processor with multiple concurrent pipelines per thread |
| US6933875B1 (en) * | 2004-11-08 | 2005-08-23 | United Microelectronics Corp. | Pipelined analog-to-digital converter with unequal work timing |
| US7417574B2 (en) * | 2004-12-13 | 2008-08-26 | Texas Instruments Incorporated | Efficient amplifier sharing in a multi-stage analog to digital converter |
| JP4579726B2 (ja) * | 2005-03-14 | 2010-11-10 | 株式会社エヌ・ティ・ティ・ドコモ | 移動通信端末 |
| US7280064B2 (en) * | 2005-09-08 | 2007-10-09 | Realtek Semiconductor Corp. | Pipeline ADC with minimum overhead digital error correction |
| KR100843554B1 (ko) * | 2006-08-31 | 2008-07-04 | 삼성전자주식회사 | 멀티-채널 파이프라인드 신호 변환기 |
| US8704581B2 (en) * | 2007-04-23 | 2014-04-22 | Qualcomm Incorporated | Switched capacitor integration and summing circuits |
| US7414564B1 (en) | 2007-06-18 | 2008-08-19 | Analog Devices, Inc. | Enhanced-accuracy converter stages for pipelined signal converter systems |
| KR101140349B1 (ko) | 2008-09-16 | 2012-05-03 | 한국전자통신연구원 | 다단 연속 근사 레지스터 아날로그 디지털 변환기 |
| JP5417993B2 (ja) * | 2009-06-01 | 2014-02-19 | 日本テキサス・インスツルメンツ株式会社 | アナログ−デジタル変換回路 |
| JP2011071966A (ja) * | 2009-08-24 | 2011-04-07 | Kyushu Institute Of Technology | パイプライン型アナログデジタル変換装置 |
| JP5565903B2 (ja) * | 2010-05-06 | 2014-08-06 | ローム株式会社 | スイッチドキャパシタ利得段 |
| KR101685011B1 (ko) | 2010-12-09 | 2016-12-14 | 한국전자통신연구원 | 파이프라인 아날로그 디지털 변환기 |
| TWI489785B (zh) * | 2011-08-31 | 2015-06-21 | Pixart Imaging Inc | 管線式類比數位轉換器及其方法 |
| US8779957B2 (en) | 2012-08-02 | 2014-07-15 | Qualcomm Incorporated | Low distortion feed-forward delta-sigma modulator |
| KR101666275B1 (ko) * | 2014-06-26 | 2016-10-14 | 한국과학기술원 | 타임 레지스터를 이용한 시간-디지털 변환 장치 및 그 방법 |
| CN104270151B (zh) * | 2014-09-22 | 2017-05-03 | 电子科技大学 | 一种用于流水线模数转换器的输出延时电路 |
| KR101986938B1 (ko) * | 2017-10-26 | 2019-06-07 | 고려대학교 세종산학협력단 | 다이나믹 레퍼런스 및 2단 샘플앤드홀드를 이용한 고속, 저전력 파이프라인드 아날로그-디지털 변환기 |
| US11438005B2 (en) * | 2020-02-26 | 2022-09-06 | Analog Devices International Unlimited Company | Timing methods for SAR ADCs |
| CN114696829B (zh) * | 2020-12-28 | 2024-07-02 | 北京特邦微电子科技有限公司 | 模数转换电路及流水线模数转换器 |
| CN115580299A (zh) * | 2021-07-06 | 2023-01-06 | 瑞昱半导体股份有限公司 | 管线式模拟数字转换器与信号转换方法 |
| WO2025013417A1 (ja) * | 2023-07-11 | 2025-01-16 | ソニーセミコンダクタソリューションズ株式会社 | アナログデジタル変換器、集積回路、および、アナログデジタル変換器の制御方法 |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4633223A (en) | 1981-10-13 | 1986-12-30 | Intel Corporation | DC offset correction circuit utilizing switched capacitor differential integrator |
| US5043732A (en) * | 1989-09-26 | 1991-08-27 | Analog Devices, Inc. | Analog-to-digital converter employing a pipeline multi-stage architecture |
| US4994808A (en) | 1989-12-14 | 1991-02-19 | Wichelman Karl F | Pipelined analog to digital converter with summing and comparator functions occurring in parallel for each bit |
| US5047772A (en) * | 1990-06-04 | 1991-09-10 | General Electric Company | Digital error correction system for subranging analog-to-digital converters |
| JPH04152717A (ja) | 1990-10-17 | 1992-05-26 | Hitachi Ltd | Ａ／ｄ変換器 |
| JP3153271B2 (ja) * | 1991-07-05 | 2001-04-03 | 株式会社日立製作所 | Ａｄ変換器 |
| JPH05218868A (ja) | 1992-02-03 | 1993-08-27 | Hitachi Ltd | 多段型ａｄ変換器 |
| JP2945805B2 (ja) | 1992-10-01 | 1999-09-06 | 松下電器産業株式会社 | Ａ／ｄ変換器 |
| KR970005828B1 (ko) | 1993-12-31 | 1997-04-21 | 김정덕 | 파이프 라인 구조의 다단 아날로그/디지탈 변환기 |
| US5572212A (en) | 1995-03-31 | 1996-11-05 | Exar Corporation | Pipelined analog to digital converter |
| US5541602A (en) | 1995-05-26 | 1996-07-30 | National Semiconductor Corporation | Multi-phased pipeland analog to digital converter |
| KR0157122B1 (ko) | 1995-12-23 | 1999-02-18 | 김광호 | 디지탈 보상형 아날로그 디지탈 변환기 |
| FR2750549B1 (fr) | 1996-06-28 | 1998-09-18 | Thomson Csf | Convertisseur analogique-numerique |
| US5771012A (en) * | 1996-09-11 | 1998-06-23 | Harris Corporation | Integrated circuit analog-to-digital converter and associated calibration method and apparatus |
| JP3042423B2 (ja) | 1996-09-30 | 2000-05-15 | 日本電気株式会社 | 直並列型ａ／ｄ変換器 |
| US5710563A (en) * | 1997-01-09 | 1998-01-20 | National Semiconductor Corporation | Pipeline analog to digital converter architecture with reduced mismatch error |
| US5861832A (en) | 1997-03-27 | 1999-01-19 | Lucent Technologies Inc. | Analog-to-digital converter having amplifier and comparator stages |
| US6166675A (en) * | 1997-09-03 | 2000-12-26 | Texas Instruments Incorporated | Pipeline analog-to-digital conversion system using double sampling and method of operation |
| JP3384717B2 (ja) * | 1997-09-04 | 2003-03-10 | 三洋電機株式会社 | アナログ−デジタル変換回路 |
| DE69922433T2 (de) * | 1998-04-24 | 2006-03-23 | Texas Instruments Inc., Dallas | Pipeline-Analog-Digital-Wandlersystem mit geändertem Kodierungsschema und dessen Betriebsverfahren |
-
2000
- 2000-02-17 US US09/506,037 patent/US6359579B1/en not_active Expired - Lifetime
- 2000-08-25 EP EP00955891A patent/EP1256173A1/en not_active Withdrawn
- 2000-08-25 JP JP2001560540A patent/JP4583694B2/ja not_active Expired - Fee Related
- 2000-08-25 WO PCT/US2000/023456 patent/WO2001061860A1/en not_active Ceased
- 2000-08-25 CN CNB008190429A patent/CN1199356C/zh not_active Expired - Fee Related
- 2000-08-25 KR KR1020027010716A patent/KR100647885B1/ko not_active Expired - Fee Related
- 2000-09-04 TW TW089118028A patent/TW469704B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100647885B1 (ko) | 2006-11-23 |
| KR20020079862A (ko) | 2002-10-19 |
| US6359579B1 (en) | 2002-03-19 |
| JP4583694B2 (ja) | 2010-11-17 |
| CN1435010A (zh) | 2003-08-06 |
| JP2003523679A (ja) | 2003-08-05 |
| EP1256173A1 (en) | 2002-11-13 |
| WO2001061860A1 (en) | 2001-08-23 |
| CN1199356C (zh) | 2005-04-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |