JP4564166B2 - ウエハ・パッシベーション層の形成方法 - Google Patents

ウエハ・パッシベーション層の形成方法 Download PDF

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Publication number
JP4564166B2
JP4564166B2 JP2000526962A JP2000526962A JP4564166B2 JP 4564166 B2 JP4564166 B2 JP 4564166B2 JP 2000526962 A JP2000526962 A JP 2000526962A JP 2000526962 A JP2000526962 A JP 2000526962A JP 4564166 B2 JP4564166 B2 JP 4564166B2
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Japan
Prior art keywords
layer
material layer
bond pad
dielectric layer
silicon nitride
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Expired - Lifetime
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JP2000526962A
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Japanese (ja)
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JP2002500440A5 (https=
JP2002500440A (ja
Inventor
ボーア，マーク・ティ
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Intel Corp
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Intel Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)
JP2000526962A 1997-12-31 1998-11-16 ウエハ・パッシベーション層の形成方法 Expired - Lifetime JP4564166B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/002,178 1997-12-31
US09/002,178 US6875681B1 (en) 1997-12-31 1997-12-31 Wafer passivation structure and method of fabrication
PCT/US1998/024358 WO1999034423A1 (en) 1997-12-31 1998-11-16 Wafer passivation structure and method of fabrication

Publications (3)

Publication Number Publication Date
JP2002500440A JP2002500440A (ja) 2002-01-08
JP2002500440A5 JP2002500440A5 (https=) 2006-01-12
JP4564166B2 true JP4564166B2 (ja) 2010-10-20

Family

ID=21699571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000526962A Expired - Lifetime JP4564166B2 (ja) 1997-12-31 1998-11-16 ウエハ・パッシベーション層の形成方法

Country Status (5)

Country Link
US (2) US6875681B1 (https=)
JP (1) JP4564166B2 (https=)
KR (2) KR100526445B1 (https=)
AU (1) AU1410999A (https=)
WO (1) WO1999034423A1 (https=)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6620720B1 (en) * 2000-04-10 2003-09-16 Agere Systems Inc Interconnections to copper IC's
US6426282B1 (en) 2000-05-04 2002-07-30 Applied Materials, Inc. Method of forming solder bumps on a semiconductor wafer
US7034402B1 (en) 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
US6521996B1 (en) 2000-06-30 2003-02-18 Intel Corporation Ball limiting metallurgy for input/outputs and methods of fabrication
FR2828009B1 (fr) * 2001-07-25 2003-10-10 Novatec Methode de realisation de bossages presentant des performances thermomecaniques ameliorees
US7180195B2 (en) 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing
US9222169B2 (en) * 2004-03-15 2015-12-29 Sharp Laboratories Of America, Inc. Silicon oxide-nitride-carbide thin-film with embedded nanocrystalline semiconductor particles
JP4525129B2 (ja) * 2004-03-26 2010-08-18 ソニー株式会社 固体撮像素子とその製造方法、及び半導体集積回路装置とその製造方法
US7452803B2 (en) * 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
JP4504791B2 (ja) * 2004-11-24 2010-07-14 パナソニック株式会社 半導体回路装置及びその製造方法
US7956460B2 (en) * 2004-12-28 2011-06-07 Rohm Co., Ltd. Semiconductor chip and method for manufacturing same, electrode structure of semiconductor chip and method for forming same, and semiconductor device
US7927933B2 (en) * 2005-02-16 2011-04-19 Imec Method to enhance the initiation of film growth
US20060211232A1 (en) * 2005-03-16 2006-09-21 Mei-Jen Liu Method for Manufacturing Gold Bumps
CN1901162B (zh) 2005-07-22 2011-04-20 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
KR100660893B1 (ko) * 2005-11-22 2006-12-26 삼성전자주식회사 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법
JP4854675B2 (ja) * 2005-11-28 2012-01-18 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US20080163897A1 (en) * 2007-01-10 2008-07-10 Applied Materials, Inc. Two step process for post ash cleaning for cu/low-k dual damascene structure with metal hard mask
US20080237822A1 (en) * 2007-03-30 2008-10-02 Raravikar Nachiket R Microelectronic die having nano-particle containing passivation layer and package including same
US8373275B2 (en) * 2008-01-29 2013-02-12 International Business Machines Corporation Fine pitch solder bump structure with built-in stress buffer
KR101037832B1 (ko) * 2008-05-09 2011-05-31 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101140063B1 (ko) * 2010-09-14 2012-04-30 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US8580672B2 (en) * 2011-10-25 2013-11-12 Globalfoundries Inc. Methods of forming bump structures that include a protection layer
US8765531B2 (en) * 2012-08-21 2014-07-01 Infineon Technologies Ag Method for manufacturing a metal pad structure of a die, a method for manufacturing a bond pad of a chip, a die arrangement and a chip arrangement
US9502343B1 (en) * 2015-09-18 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy metal with zigzagged edges
US11365117B2 (en) 2019-12-23 2022-06-21 Industrial Technology Research Institute MEMS device and manufacturing method of the same
US11939212B2 (en) 2019-12-23 2024-03-26 Industrial Technology Research Institute MEMS device, manufacturing method of the same, and integrated MEMS module using the same
US11251114B2 (en) * 2020-05-01 2022-02-15 Taiwan Semiconductor Manufacturing Co., Ltd. Package substrate insulation opening design

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR890005819A (ko) * 1987-09-21 1989-05-17 강진구 반도체 소자의 보호막 제조방법
KR910000793B1 (ko) * 1987-12-15 1991-02-08 삼성전자 주식회사 반도체 장치의 보호막 형성방법
US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US4921810A (en) * 1988-06-22 1990-05-01 Nec Electronics Inc. Method for testing semiconductor devices
US4927505A (en) * 1988-07-05 1990-05-22 Motorola Inc. Metallization scheme providing adhesion and barrier properties
US5023205A (en) * 1989-04-27 1991-06-11 Polycon Method of fabricating hybrid circuit structures
JP2814009B2 (ja) * 1990-06-05 1998-10-22 三菱電機株式会社 半導体装置の製造方法
US5136364A (en) * 1991-06-12 1992-08-04 National Semiconductor Corporation Semiconductor die sealing
US5369695A (en) * 1992-01-06 1994-11-29 At&T Corp. Method of redirecting a telephone call to an alternate destination
US5787010A (en) * 1992-04-02 1998-07-28 Schaefer; Thomas J. Enhanced dynamic programming method for technology mapping of combinational logic circuits
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
JP2611615B2 (ja) * 1992-12-15 1997-05-21 日本電気株式会社 半導体装置の製造方法
TW347149U (en) * 1993-02-26 1998-12-01 Dow Corning Integrated circuits protected from the environment by ceramic and barrier metal layers
US5369299A (en) * 1993-07-22 1994-11-29 National Semiconductor Corporation Tamper resistant integrated circuit structure
US5565384A (en) * 1994-04-28 1996-10-15 Texas Instruments Inc Self-aligned via using low permittivity dielectric
US5508229A (en) * 1994-05-24 1996-04-16 National Semiconductor Corporation Method for forming solder bumps in semiconductor devices
EP0696056B1 (en) * 1994-07-29 2000-01-19 STMicroelectronics, Inc. Method of testing and repairing an integrated circuit structure and forming a passivation structure
JPH09511622A (ja) * 1994-11-07 1997-11-18 マクロニクス インターナショナル カンパニー リミテッド 集積回路表面保護方法および構造
US5587336A (en) 1994-12-09 1996-12-24 Vlsi Technology Bump formation on yielded semiconductor dies
US6204074B1 (en) * 1995-01-09 2001-03-20 International Business Machines Corporation Chip design process for wire bond and flip-chip package
US5559056A (en) 1995-01-13 1996-09-24 National Semiconductor Corporation Method and apparatus for capping metallization layer
US5661082A (en) * 1995-01-20 1997-08-26 Motorola, Inc. Process for forming a semiconductor device having a bond pad
KR100367702B1 (ko) * 1995-03-20 2003-04-07 유나이티브 인터내셔널 리미티드 티타늄장벽층을포함하는솔더범프제조방법및구조
KR100312377B1 (ko) * 1995-06-28 2003-08-06 주식회사 하이닉스반도체 반도체소자의보호막제조방법
US5900668A (en) * 1995-11-30 1999-05-04 Advanced Micro Devices, Inc. Low capacitance interconnection
US5693565A (en) * 1996-07-15 1997-12-02 Dow Corning Corporation Semiconductor chips suitable for known good die testing
JP3305211B2 (ja) * 1996-09-10 2002-07-22 松下電器産業株式会社 半導体装置及びその製造方法
US6025275A (en) * 1996-12-19 2000-02-15 Texas Instruments Incorporated Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect
US5759906A (en) * 1997-04-11 1998-06-02 Industrial Technology Research Institute Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits
US6143638A (en) * 1997-12-31 2000-11-07 Intel Corporation Passivation structure and its method of fabrication

Also Published As

Publication number Publication date
KR100526445B1 (ko) 2005-11-08
JP2002500440A (ja) 2002-01-08
US7145235B2 (en) 2006-12-05
AU1410999A (en) 1999-07-19
KR20010033662A (ko) 2001-04-25
WO1999034423A1 (en) 1999-07-08
KR100522130B1 (ko) 2005-10-19
KR20050065684A (ko) 2005-06-29
US20050158978A1 (en) 2005-07-21
US6875681B1 (en) 2005-04-05

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