KR100526445B1 - 웨이퍼 패시베이션 구조 - Google Patents

웨이퍼 패시베이션 구조 Download PDF

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Publication number
KR100526445B1
KR100526445B1 KR10-2005-7010038A KR20057010038A KR100526445B1 KR 100526445 B1 KR100526445 B1 KR 100526445B1 KR 20057010038 A KR20057010038 A KR 20057010038A KR 100526445 B1 KR100526445 B1 KR 100526445B1
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KR
South Korea
Prior art keywords
dielectric layer
layer
dielectric
passivation structure
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR10-2005-7010038A
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English (en)
Korean (ko)
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KR20050065684A (ko
Inventor
마크 티 보어
Original Assignee
인텔 코오퍼레이션
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Application filed by 인텔 코오퍼레이션 filed Critical 인텔 코오퍼레이션
Publication of KR20050065684A publication Critical patent/KR20050065684A/ko
Application granted granted Critical
Publication of KR100526445B1 publication Critical patent/KR100526445B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)
KR10-2005-7010038A 1997-12-31 1998-11-16 웨이퍼 패시베이션 구조 Expired - Lifetime KR100526445B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/002,178 1997-12-31
US09/002,178 US6875681B1 (en) 1997-12-31 1997-12-31 Wafer passivation structure and method of fabrication
KR10-2000-7007182A KR100522130B1 (ko) 1997-12-31 1998-11-16 웨이퍼 패시베이션 구조 및 제조방법

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR10-2000-7007182A Division KR100522130B1 (ko) 1997-12-31 1998-11-16 웨이퍼 패시베이션 구조 및 제조방법

Publications (2)

Publication Number Publication Date
KR20050065684A KR20050065684A (ko) 2005-06-29
KR100526445B1 true KR100526445B1 (ko) 2005-11-08

Family

ID=21699571

Family Applications (2)

Application Number Title Priority Date Filing Date
KR10-2005-7010038A Expired - Lifetime KR100526445B1 (ko) 1997-12-31 1998-11-16 웨이퍼 패시베이션 구조
KR10-2000-7007182A Expired - Lifetime KR100522130B1 (ko) 1997-12-31 1998-11-16 웨이퍼 패시베이션 구조 및 제조방법

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR10-2000-7007182A Expired - Lifetime KR100522130B1 (ko) 1997-12-31 1998-11-16 웨이퍼 패시베이션 구조 및 제조방법

Country Status (5)

Country Link
US (2) US6875681B1 (https=)
JP (1) JP4564166B2 (https=)
KR (2) KR100526445B1 (https=)
AU (1) AU1410999A (https=)
WO (1) WO1999034423A1 (https=)

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US6521996B1 (en) 2000-06-30 2003-02-18 Intel Corporation Ball limiting metallurgy for input/outputs and methods of fabrication
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US7180195B2 (en) 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing
US9222169B2 (en) * 2004-03-15 2015-12-29 Sharp Laboratories Of America, Inc. Silicon oxide-nitride-carbide thin-film with embedded nanocrystalline semiconductor particles
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US7452803B2 (en) * 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
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US7956460B2 (en) * 2004-12-28 2011-06-07 Rohm Co., Ltd. Semiconductor chip and method for manufacturing same, electrode structure of semiconductor chip and method for forming same, and semiconductor device
US7927933B2 (en) * 2005-02-16 2011-04-19 Imec Method to enhance the initiation of film growth
US20060211232A1 (en) * 2005-03-16 2006-09-21 Mei-Jen Liu Method for Manufacturing Gold Bumps
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KR100660893B1 (ko) * 2005-11-22 2006-12-26 삼성전자주식회사 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법
JP4854675B2 (ja) * 2005-11-28 2012-01-18 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US20080163897A1 (en) * 2007-01-10 2008-07-10 Applied Materials, Inc. Two step process for post ash cleaning for cu/low-k dual damascene structure with metal hard mask
US20080237822A1 (en) * 2007-03-30 2008-10-02 Raravikar Nachiket R Microelectronic die having nano-particle containing passivation layer and package including same
US8373275B2 (en) * 2008-01-29 2013-02-12 International Business Machines Corporation Fine pitch solder bump structure with built-in stress buffer
KR101037832B1 (ko) * 2008-05-09 2011-05-31 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101140063B1 (ko) * 2010-09-14 2012-04-30 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
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Also Published As

Publication number Publication date
JP4564166B2 (ja) 2010-10-20
JP2002500440A (ja) 2002-01-08
US7145235B2 (en) 2006-12-05
AU1410999A (en) 1999-07-19
KR20010033662A (ko) 2001-04-25
WO1999034423A1 (en) 1999-07-08
KR100522130B1 (ko) 2005-10-19
KR20050065684A (ko) 2005-06-29
US20050158978A1 (en) 2005-07-21
US6875681B1 (en) 2005-04-05

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