JP4202987B2 - 金属誘導側面結晶化方法を用いた薄膜トランジスタ及びその製造方法 - Google Patents
金属誘導側面結晶化方法を用いた薄膜トランジスタ及びその製造方法 Download PDFInfo
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- 238000002425 crystallisation Methods 0.000 title claims description 117
- 239000010409 thin film Substances 0.000 title claims description 58
- 229910052751 metal Inorganic materials 0.000 title claims description 55
- 239000002184 metal Substances 0.000 title claims description 55
- 238000000034 method Methods 0.000 title claims description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 230000008025 crystallization Effects 0.000 claims description 112
- 239000010408 film Substances 0.000 claims description 105
- 239000010410 layer Substances 0.000 claims description 93
- 230000006698 induction Effects 0.000 claims description 53
- 230000001939 inductive effect Effects 0.000 claims description 46
- 239000011229 interlayer Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 25
- 230000001681 protective effect Effects 0.000 claims description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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Description
図1〜図5は、本発明の第1の実施形態に係るMILC方法を用いた薄膜トランジスタの製造方法を説明するための工程断面図である。
図6は、本発明の第2の実施形態に係るMILC方法を用いた薄膜トランジスタを説明するための断面図である。
120,240 ゲート電極
130,251,255 コンタクトホール
200 絶縁基板
210 バッファー層
221 ソース領域
223 チャンネル領域
225 ドレイン領域
230 ゲート絶縁膜
250 層間絶縁膜
260 結晶化誘導金属膜
271 ソース電極
275 ドレイン電極
300,400 絶縁基板
310,410 バッファー層
320,420,500 活性層
321,421 ソース領域
323,423 チャネル領域
325,425 ドレイン領域
330,430 ゲート絶縁膜
340,440,530 ゲート電極
350,450 層間絶縁膜
351,355,451,455,510 コンタクトホール
357,457,520 結晶化誘導パターン
360 結晶化誘導金属膜
371,471,471,475 ソース電極
375,475 ドレイン電極
477 保護金属膜
Claims (19)
- 絶縁基板上に形成され、ソース領域、ドレイン領域、及び前記ソース領域とドレイン領域との間に形成されるチャンネル領域を備える活性層と、
前記活性層を含む前記絶縁基板の上面に形成されたゲート絶縁膜、及びこのゲート絶縁膜上に形成されたゲート電極と、
前記ゲート絶縁膜及びゲート電極の上方に形成された層間絶縁膜と、
前記層間絶縁膜、及び前記ゲート絶縁膜を上方から貫通して前記ソース領域、ドレイン領域それぞれの一部分を露出させる複数のコンタクトホールと、
前記コンタクトホールとは異なる位置に形成され、前記層間絶縁膜、及び前記ゲート絶縁膜を上方から貫通して前記ソース領域、及びドレイン領域の少なくとも一方の一部分を露出させる少なくとも一つの結晶化誘導パターンと、
前記各コンタクトホールを通して前記ソース領域と電気的に連結するソース電極、及び、前記ドレイン領域と電気的に連結するドレイン電極とを含み、
前記結晶化誘導パターンは、前記ソース領域とソース電極との電気的な連結、及び前記ドレイン領域と前記ドレイン電極との電気的な連結に寄与しないことを特徴とする薄膜トランジスタ。 - 前記結晶化誘導パターンは、前記コンタクトホールと、前記チャンネル領域との間に形成されることを特徴とする請求項1に記載の薄膜トランジスタ。
- 前記ソース領域から、チャンネル領域及びドレイン領域へ向かう方向を所定方向としたとき、前記結晶化誘導パターンによって活性層が露出される部分の前記所定方向の幅は、一つのコンタクトホールによって活性層が露出される部分の前記所定方向の幅より大きいことを特徴とする請求項1に記載の薄膜トランジスタ。
- 前記結晶化誘導パターンによって活性層が露出される部分の前記所定方向の幅は、前記チャンネル領域の前記所定方向の幅と同一であることを特徴とする請求項3に記載の薄膜トランジスタ。
- 絶縁基板上に形成され、ソース領域、ドレイン領域、及び前記ソース領域とドレイン領域との間に形成されるチャンネル領域を備える活性層と、
前記活性層を含む前記絶縁基板の上面に形成されたゲート絶縁膜、及びこのゲート絶縁膜上に形成されたゲート電極と、
前記ゲート絶縁膜及びゲート電極の上方に形成された層間絶縁膜と、
前記層間絶縁膜、及び前記ゲート絶縁膜を上方から貫通して前記ソース領域、ドレイン領域それぞれの一部分を露出させる複数のコンタクトホールと、
前記コンタクトホールとは異なる位置に形成され、前記層間絶縁膜、及び前記ゲート絶縁膜を上方から貫通して前記ソース領域、及びドレイン領域の少なくとも一方の一部分を露出させる少なくとも一つの結晶化誘導パターンと、
前記各コンタクトホールを通して前記ソース領域と電気的に連結するソース電極、及び、前記ドレイン領域と電気的に連結するドレイン電極と、
前記結晶化誘導パターンの、前記ソース領域露出面、及び前記ドレイン領域露出面に形成され、前記ソース領域、及びドレイン領域を保護する保護金属膜と、を含み、
前記結晶化誘導パターン及び前記保護金属膜は、前記ソース領域とソース電極との電気的な連結、及び前記ドレイン領域と前記ドレイン電極との電気的な連結に寄与しないことを特徴とする薄膜トランジスタ。 - 前記結晶化誘導パターンは、前記コンタクトホールと、前記チャンネル領域との間に形成されることを特徴とする請求項5に記載の薄膜トランジスタ。
- 前記ソース領域から、チャンネル領域及びドレイン領域へ向かう方向を所定方向としたとき、前記結晶化誘導パターンによって活性層が露出される部分の前記所定方向の幅は、一つのコンタクトホールによって活性層が露出される部分の前記所定方向の幅より大きいことを特徴とする請求項5に記載の薄膜トランジスタ。
- 前記結晶化誘導パターンによって活性層が露出される部分の前記所定方向の幅は、前記チャンネル領域の前記所定方向の幅と同一であることを特徴とする請求項7に記載の薄膜トランジスタ。
- 前記保護金属膜は、前記活性層中の、前記結晶化誘導パターンによって露出するソース領域、及びドレイン領域を保護することを特徴とする請求項7に記載の薄膜トランジスタ。
- 前記保護金属膜は、前記ソース電極、及び前記ドレイン電極と同一の物質からなることを特徴とする請求項7に記載の薄膜トランジスタ。
- 絶縁基板上に非晶質シリコンからなる活性層を形成するステップと、
前記活性層を含む前記絶縁基板の上面にゲート絶縁膜を形成し、且つ、該ゲート絶縁膜上にゲート電極を形成するステップと、
前記活性層に所定の不純物を注入してソース領域、及びドレイン領域を形成するステップと、
前記ゲート絶縁膜及びゲート電極の上方に、層間絶縁膜を形成するステップと、
前記層間絶縁膜、及び前記ゲート絶縁膜を上方から貫通して、前記ソース領域、ドレイン領域の一部分を露出させる複数のコンタクトホールを形成するステップと、
前記コンタクトホールとは異なる位置で、前記層間絶縁膜、及び前記ゲート絶縁膜を上方から貫通して、前記ソース領域、及びドレイン領域の少なくとも一方を露出させる少なくとも一つの結晶化誘導パターンを形成するステップと、
前記層間絶縁膜全面に、結晶化誘導金属膜を蒸着するステップと、
MILC(Metal Induced Lateral Crystallization)方法を用いて、前記非晶質シリコンの活性層を、多結晶シリコンの活性層として結晶化するステップと、
前記コンタクトホールを通して、前記ソース領域と電気的に連結するソース電極、及び前記ドレイン領域と電気的に連結するドレイン電極を形成するステップと、を含み、
前記結晶化誘導パターンは、前記ソース領域と前記ソース電極との電気的な連結、及び前記ドレイン領域と前記ドレイン電極との電気的な連結に寄与しないことを特徴とする薄膜トランジスタの製造方法。 - 前記結晶化誘導金属膜は、50オングストローム以上の厚さを有することを特徴とする請求項11に記載の薄膜トランジスタの製造方法。
- 前記結晶化誘導金属膜は、200オングストローム以上の厚さを有することを特徴とする請求項12に記載の薄膜トランジスタの製造方法。
- 前記結晶化誘導金属膜は、ニッケル(Ni)からなることを特徴とする請求項11に記載の薄膜トランジスタの製造方法。
- 前記結晶化誘導パターンは、前記コンタクトホールと前記チャンネル領域との間に形成されることを特徴とする請求項11に記載の薄膜トランジスタの製造方法。
- 前記ソース領域から、チャンネル領域及びドレイン領域へ向かう方向を所定方向としたとき、前記結晶化誘導パターンによって活性層が露出される部分の前記所定方向の幅は、一つのコンタクトホールによって活性層が露出される部分の前記所定方向の幅より大きいことを特徴とする請求項11に記載の薄膜トランジスタの製造方法。
- 前記結晶化誘導パターンによって活性層が露出される部分の前記所定方向の幅は、前記チャンネル領域の前記所定方向の幅と同一であることを特徴とする請求項16に記載の薄膜トランジスタの製造方法。
- 前記MILC方法を用いて、前記非晶質シリコンの活性層を、多結晶シリコンの活性層として結晶化した後、蒸着した前記結晶化誘導金属膜を除去し、その後、前記結晶化誘導パターンの、前記ソース領域露出面、及び前記ドレイン領域露出面に、前記ソース領域、及び前記ドレイン領域を保護する保護金属膜を形成するステップを更に含むことを特徴とする請求項11に記載の薄膜トランジスタの製造方法。
- 前記保護金属膜は、前記ソース電極、及びドレイン電極と同一の物質からなり、前記ソース電極、ドレイン電極の形成時に前記活性層中の、前記結晶化誘導パターンによって露出されるソース領域、及びドレイン領域を保護することを特徴とする請求項18に記載の薄膜トランジスタの製造方法。
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KR100624427B1 (ko) * | 2004-07-08 | 2006-09-19 | 삼성전자주식회사 | 다결정 실리콘 제조방법 및 이를 이용하는 반도체 소자의제조방법 |
KR100776362B1 (ko) * | 2004-12-03 | 2007-11-15 | 네오폴리((주)) | 비정질 실리콘 박막의 결정화 방법 및 이를 이용한 다결정 실리콘 박막 트랜지스터의 제조방법 |
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TW546846B (en) * | 2001-05-30 | 2003-08-11 | Matsushita Electric Ind Co Ltd | Thin film transistor and method for manufacturing the same |
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KR101456405B1 (ko) * | 2012-06-29 | 2014-10-31 | 보에 테크놀로지 그룹 컴퍼니 리미티드 | 박막 트랜지스터, 어레이 기판, 및 그 제조방법 |
US8963157B2 (en) | 2012-06-29 | 2015-02-24 | Boe Technology Group Co., Ltd. | Thin film transistor, array substrate, and manufacturing method thereof |
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US20050110022A1 (en) | 2005-05-26 |
KR100611224B1 (ko) | 2006-08-09 |
JP2005159305A (ja) | 2005-06-16 |
CN1645630A (zh) | 2005-07-27 |
KR20050049684A (ko) | 2005-05-27 |
US7202501B2 (en) | 2007-04-10 |
CN100388508C (zh) | 2008-05-14 |
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