JP2005159305A - 金属誘導側面結晶化方法を用いた薄膜トランジスタ及びその製造方法 - Google Patents
金属誘導側面結晶化方法を用いた薄膜トランジスタ及びその製造方法 Download PDFInfo
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- 238000002425 crystallisation Methods 0.000 title claims abstract description 119
- 239000010409 thin film Substances 0.000 title claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 54
- 239000002184 metal Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 230000008025 crystallization Effects 0.000 claims abstract description 113
- 239000010410 layer Substances 0.000 claims abstract description 90
- 239000010408 film Substances 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 230000006698 induction Effects 0.000 claims description 62
- 238000000034 method Methods 0.000 claims description 49
- 230000001939 inductive effect Effects 0.000 claims description 35
- 230000001681 protective effect Effects 0.000 claims description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000007790 solid phase Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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Abstract
【解決手段】 絶縁基板上に形成され、ソース/ドレイン領域及びチャンネル領域を備える活性層と、ゲート絶縁膜上に形成されたゲート電極と、ソース/ドレイン領域それぞれの一部分を露出させるコンタクトホール及び結晶化誘導パターンを備える層間絶縁膜と、コンタクトホールを通してソース/ドレイン領域と電気的に連結するソース/ドレイン電極とを含み、結晶化誘導パターンは、ソース/ドレイン領域とソース/ドレイン電極が電気的に連結することに寄与しないことを特徴とする。
【選択図】 図5
Description
図1〜図5は、本発明の第1の実施形態に係るMILC方法を用いた薄膜トランジスタの製造方法を説明するための工程断面図である。
図6は、本発明の第2の実施形態に係るMILC方法を用いた薄膜トランジスタを説明するための断面図である。
120,240 ゲート電極
130,251,255 コンタクトホール
200 絶縁基板
210 バッファー層
221 ソース領域
223 チャンネル領域
225 ドレイン領域
230 ゲート絶縁膜
250 層間絶縁膜
260 結晶化誘導金属膜
271 ソース電極
275 ドレイン電極
300,400 絶縁基板
310,410 バッファー層
320,420,500 活性層
321,421 ソース領域
323,423 チャネル領域
325,425 ドレイン領域
330,430 ゲート絶縁膜
340,440,530 ゲート電極
350,450 層間絶縁膜
351,355,451,455,510 コンタクトホール
357,457,520 結晶化誘導パターン
360 結晶化誘導金属膜
371,471,471,475 ソース電極
375,475 ドレイン電極
477 保護金属膜
Claims (19)
- 絶縁基板上に形成され、ソース/ドレイン領域及びチャンネル領域を備える活性層と、
前記活性層を含む前記絶縁基板の上面に形成されたゲート絶縁膜、及びこのゲート絶縁膜上に形成されたゲート電極と、
前記ゲート絶縁膜及びゲート電極の上方に形成され、前記ソース/ドレイン領域それぞれの一部分を露出させるコンタクトホールと、少なくとも一つの結晶化誘導パターンを備える層間絶縁膜と、
前記コンタクトホールを通してソース/ドレイン領域と電気的に連結するソース/ドレイン電極とを含み、
前記結晶化誘導パターンは、前記ソース/ドレイン領域と前記ソース/ドレイン電極が電気的に連結することに寄与しないことを特徴とする薄膜トランジスタ。 - 前記結晶化誘導パターンは、前記コンタクトホールと、前記チャンネル領域との間に形成されることを特徴とする請求項1に記載の薄膜トランジスタ。
- 前記結晶化誘導パターンによって活性層が露出される部分の幅は、一つのコンタクトホールによって活性層が露出される部分の幅より大きいことを特徴とする請求項1に記載の薄膜トランジスタ。
- 前記結晶化誘導パターンによって活性層が露出される部分の幅は、前記チャンネル領域の幅と同一であることを特徴とする請求項3に記載の薄膜トランジスタ。
- 絶縁基板上に形成され、ソース/ドレイン領域及びチャンネル領域を備える活性層と、
前記活性層を含む前記絶縁基板の上面に形成されたゲート絶縁膜、及びこのゲート絶縁膜上に形成されたゲート電極と、
前記ゲート絶縁膜及びゲート電極の上方に形成され、前記ソース/ドレイン領域それぞれの一部分を露出させるコンタクトホールと、少なくとも一つの結晶化誘導パターンを備える層間絶縁膜と、
前記コンタクトホールを通してソース/ドレイン領域と電気的に連結するソース/ドレイン電極と、
前記結晶化誘導パターン内に形成された保護金属膜とを含み、
前記結晶化誘導パターン及び前記保護金属膜は、前記ソース/ドレイン領域と前記ソース/ドレイン電極が電気的に連結することに寄与しないことを特徴とする薄膜トランジスタ。 - 前記結晶化誘導パターンは、前記コンタクトホールと、前記チャンネル領域との間に形成されることを特徴とする請求項5に記載の薄膜トランジスタ。
- 前記結晶化誘導パターンによって活性層が露出される部分の幅は、一つのコンタクトホールによって活性層が露出される部分の幅より大きいことを特徴とする請求項5に記載の薄膜トランジスタ。
- 前記結晶化誘導パターンによって活性層が露出される部分の幅は、前記チャンネル領域の幅と同一であることを特徴とする請求項7に記載の薄膜トランジスタ。
- 前記保護金属膜は、前記活性層中の、前記結晶化誘導パターンによって露出する領域を保護することを特徴とする請求項7に記載の薄膜トランジスタ。
- 前記保護金属膜は、前記ソース/ドレイン電極と同一の物質からなることを特徴とする請求項7に記載の薄膜トランジスタ。
- 絶縁基板上に非晶質シリコンからなる活性層を形成するステップと、
前記活性層を含む前記絶縁基板の上面にゲート絶縁膜を形成し、且つ、該ゲート絶縁膜上にゲート電極を形成するステップと、
前記活性層に所定の不純物を注入してソース/ドレイン領域を形成するステップと、
前記ゲート絶縁膜及びゲート電極の上方に、前記ソース/ドレイン領域それぞれの一部分を露出させるコンタクトホール及び少なくとも一つの結晶化誘導パターンを備える層間絶縁膜を形成するステップと、
前記絶縁基板全面に、結晶化誘導金属膜を蒸着するステップと、
MILC(Metal Induced Lateral Crystallization)方法を用いて、前記非晶質シリコンの活性層を多結晶シリコンの活性層として結晶化するステップと、
前記コンタクトホールを通して、ソース/ドレイン領域と電気的に連結するソース/ドレイン電極を形成するステップと、を含み、
前記結晶化誘導パターンは、前記ソース/ドレイン領域と前記ソース/ドレイン電極とが電気的に連結することに寄与しないことを特徴とする薄膜トランジスタの製造方法。 - 前記結晶化誘導金属膜は、50オングストローム以上の厚さを有することを特徴とする請求項11に記載の薄膜トランジスタの製造方法。
- 前記結晶化誘導金属膜は、200オングストローム以上の厚さを有することを特徴とする請求項12に記載の薄膜トランジスタの製造方法。
- 前記結晶化誘導金属膜は、ニッケル(Ni)からなることを特徴とする請求項11に記載の薄膜トランジスタの製造方法。
- 前記結晶化誘導パターンは、前記コンタクトホールと前記チャンネル領域との間に存在することを特徴とする請求項11に記載の薄膜トランジスタの製造方法。
- 前記結晶化誘導パターンによって活性層が露出される部分の幅は、一つのコンタクトホールによって活性層が露出される部分の幅よりも大きいことを特徴とする請求項11に記載の薄膜トランジスタの製造方法。
- 前記結晶化誘導パターンによって活性層が露出される部分の幅は、前記チャンネル領域の幅と同一であることを特徴とする請求項16に記載の薄膜トランジスタの製造方法。
- 前記結晶化誘導パターン内に保護金属膜を更に含むことを特徴とする請求項11に記載の薄膜トランジスタの製造方法。
- 前記保護金属膜は、前記ソース/ドレイン電極と同一の物質からなり、前記ソース/ドレイン電極形成時に前記活性層中の、前記結晶化誘導パターンによって露出される領域を保護することを特徴とする請求項18に記載の薄膜トランジスタの製造方法。
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Cited By (4)
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JP2005159307A (ja) * | 2003-11-22 | 2005-06-16 | Samsung Sdi Co Ltd | 金属誘導側面結晶化方法を用いた薄膜トランジスター及びその製造方法 |
JP2010021556A (ja) * | 2008-07-14 | 2010-01-28 | Samsung Mobile Display Co Ltd | 薄膜トランジスタ、その製造方法及びこれを含む有機発光ダイオード表示装置 |
KR101283008B1 (ko) | 2010-12-23 | 2013-07-05 | 주승기 | 트렌치형상의 구리 하부 게이트 구조를 갖는 다결정 실리콘 박막 트랜지스터의 제조방법 |
JP2014179465A (ja) * | 2013-03-14 | 2014-09-25 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
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KR100686442B1 (ko) * | 2004-06-30 | 2007-02-23 | 네오폴리((주)) | 부식 방지층을 이용한 금속유도측면결정화법에 의한 박막 트랜지스터의 제조방법 |
KR100624427B1 (ko) * | 2004-07-08 | 2006-09-19 | 삼성전자주식회사 | 다결정 실리콘 제조방법 및 이를 이용하는 반도체 소자의제조방법 |
KR100776362B1 (ko) * | 2004-12-03 | 2007-11-15 | 네오폴리((주)) | 비정질 실리콘 박막의 결정화 방법 및 이를 이용한 다결정 실리콘 박막 트랜지스터의 제조방법 |
KR100703467B1 (ko) * | 2005-01-07 | 2007-04-03 | 삼성에스디아이 주식회사 | 박막트랜지스터 |
KR100875432B1 (ko) * | 2007-05-31 | 2008-12-22 | 삼성모바일디스플레이주식회사 | 다결정 실리콘층의 제조 방법, 이를 이용하여 형성된박막트랜지스터, 그의 제조방법 및 이를 포함하는유기전계발광표시장치 |
KR100889626B1 (ko) * | 2007-08-22 | 2009-03-20 | 삼성모바일디스플레이주식회사 | 박막트랜지스터, 그의 제조방법, 이를 구비한유기전계발광표시장치, 및 그의 제조방법 |
KR100889627B1 (ko) | 2007-08-23 | 2009-03-20 | 삼성모바일디스플레이주식회사 | 박막트랜지스터, 그의 제조방법, 및 이를 구비한유기전계발광표시장치 |
KR100982310B1 (ko) | 2008-03-27 | 2010-09-15 | 삼성모바일디스플레이주식회사 | 박막트랜지스터, 그의 제조방법, 및 이를 포함하는유기전계발광표시장치 |
KR100989136B1 (ko) | 2008-04-11 | 2010-10-20 | 삼성모바일디스플레이주식회사 | 박막트랜지스터, 그의 제조방법, 및 이를 포함하는유기전계발광표시장치 |
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CN102751200B (zh) * | 2012-06-29 | 2015-06-10 | 京东方科技集团股份有限公司 | 薄膜晶体管、阵列基板及其制造方法 |
CN113454792A (zh) * | 2018-12-27 | 2021-09-28 | 深圳市柔宇科技股份有限公司 | 一种功能器件及其制造方法 |
CN112420849A (zh) * | 2020-11-09 | 2021-02-26 | 昆山龙腾光电股份有限公司 | 金属氧化物薄膜晶体管及其制作方法 |
JP2022087756A (ja) * | 2020-12-01 | 2022-06-13 | 株式会社ジャパンディスプレイ | 表示装置 |
WO2023184095A1 (zh) * | 2022-03-28 | 2023-10-05 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制备方法、显示基板、显示装置 |
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KR100378259B1 (ko) * | 2001-01-20 | 2003-03-29 | 주승기 | 결정질 활성층을 포함하는 박막트랜지스터 제작 방법 및장치 |
TW546846B (en) * | 2001-05-30 | 2003-08-11 | Matsushita Electric Ind Co Ltd | Thin film transistor and method for manufacturing the same |
KR100776362B1 (ko) * | 2004-12-03 | 2007-11-15 | 네오폴리((주)) | 비정질 실리콘 박막의 결정화 방법 및 이를 이용한 다결정 실리콘 박막 트랜지스터의 제조방법 |
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Cited By (6)
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JP2005159307A (ja) * | 2003-11-22 | 2005-06-16 | Samsung Sdi Co Ltd | 金属誘導側面結晶化方法を用いた薄膜トランジスター及びその製造方法 |
US7714391B2 (en) | 2003-11-22 | 2010-05-11 | Samsung Mobile Display Co., Ltd. | Thin film transistor and method for fabricating the same |
JP2010021556A (ja) * | 2008-07-14 | 2010-01-28 | Samsung Mobile Display Co Ltd | 薄膜トランジスタ、その製造方法及びこれを含む有機発光ダイオード表示装置 |
JP2013048267A (ja) * | 2008-07-14 | 2013-03-07 | Samsung Display Co Ltd | 薄膜トランジスタ、その製造方法及びこれを含む有機発光ダイオード表示装置 |
KR101283008B1 (ko) | 2010-12-23 | 2013-07-05 | 주승기 | 트렌치형상의 구리 하부 게이트 구조를 갖는 다결정 실리콘 박막 트랜지스터의 제조방법 |
JP2014179465A (ja) * | 2013-03-14 | 2014-09-25 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
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KR100611224B1 (ko) | 2006-08-09 |
CN1645630A (zh) | 2005-07-27 |
KR20050049684A (ko) | 2005-05-27 |
US7202501B2 (en) | 2007-04-10 |
CN100388508C (zh) | 2008-05-14 |
JP4202987B2 (ja) | 2008-12-24 |
US20050110022A1 (en) | 2005-05-26 |
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