JP4026009B2 - 多結晶シリコン膜形成方法とこれを利用した薄膜トランジスタの製造方法 - Google Patents
多結晶シリコン膜形成方法とこれを利用した薄膜トランジスタの製造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 81
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- 239000010409 thin film Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010410 layer Substances 0.000 claims description 113
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 70
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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Description
−−第1実施例−−
本発明は基板の1方向に相互離隔された電極を構成して一次で結晶化を進めて、前記電極を一次結晶化工程とは垂直な方向で構成して結晶化を進めることを特徴とする。
−−第2実施例−−
本発明の第2実施例は、非晶質先行膜の上/下と左/右方向に同時に電極を接触して高電圧を印加して結晶化工程を進めることを特徴とする。
まず、図7Aに示したように、バッファ層302が形成された基板300上に前述したような結晶化工程を通して結晶化された多結晶シリコン膜をパターニングして、アイランド状のアクティブ層314を形成する。
前述したような工程を通して本発明による多結晶薄膜トランジスタを製作することができる。
Claims (18)
- 基板上部に非晶質シリコン層を形成する段階と;
前記非晶質シリコン層の上部に触媒金属を蒸着する段階と;
前記触媒金属が蒸着された非晶質シリコン層の一側と他側に前記非晶質シリコン層と接触して第1方向に相互離隔された第1及び2電極を配置する段階と;
前記非晶質シリコン層を第1温度で加熱しながら同時に前記第1及び2電極に第1電圧を印加して一次結晶化された非晶質シリコン層を形成する段階と;
前記一次結晶化された非晶質シリコン層の上部に前記第1方向と垂直な第2方向に相互離隔された第3及び4電極を配置する段階と;
前記一次結晶化された非晶質シリコン層を第2温度で加熱しながら同時に前記第3及び4電極に第2電圧を印加して二次結晶化された非晶質シリコン層を形成する段階とを含む多結晶シリコン層の形成方法。 - 前記第1及び2温度各々は、500℃〜550℃の範囲であることを特徴とする請求項1に記載の多結晶シリコン層の形成方法。
- 基板上部に非晶質シリコン層を形成する段階と;
前記非晶質シリコン層の上部に触媒金属を蒸着する段階と;
前記触媒金属が蒸着された非晶質シリコン層上部に前記非晶質シリコン層と接触して第1方向に相互離隔された第1及び2電極と前記第1方向と垂直な第2方向に相互離隔された第3及び4電極を配置する段階と;
前記非晶質シリコン層を第1温度で加熱しながら同時に前記第1及び2電極に第1電圧を印加して前記第3及び4電極に第2電圧を印加する段階とを含む多結晶シリコン層の形成方法。 - 前記第1電圧は、第1電源から前記第1及び2電極に印加されて、前記第2電圧は、第2電源から前記第3及び4電極に印加されることを特徴とする請求項3に記載の多結晶シリコン層の形成方法。
- 前記第1及び2電圧は、同一電圧であることを特徴とする請求項3に記載の多結晶シリコン層の形成方法。
- 前記第1及び第2電圧は、前記第1ないし4電極に連結された同一な電源から印加されることを特徴とする請求項5に記載の多結晶シリコン層の形成方法。
- 前記第1温度は、500℃〜550℃の範囲であることを特徴とする請求項3に記載の多結晶シリコン層の形成方法。
- 基板上部に非晶質シリコン層を形成する段階と;
前記非晶質シリコン層の上部に触媒金属を蒸着する段階と;
前記触媒金属が蒸着された非晶質シリコン層の一側と他側に前記非晶質シリコン層と接触して第1方向に相互離隔された第1及び2電極を配置する段階と;
前記非晶質シリコン層を第1温度で加熱しながら同時に前記第1及び2電極に第1電圧を印加して一次結晶化された非晶質シリコン層を形成する段階と;
前記一次結晶化された非晶質シリコン層の上部に前記第1方向と垂直な第2方向に相互離隔された第3及び4電極を配置する段階と;
前記一次結晶化された非晶質シリコン層を第2温度で加熱しながら同時に前記第3及び4電極に第2電圧を印加して多結晶シリコン層を形成する段階と;
前記多結晶シリコン層をパターンしてアクティブ層を形成する段階と;
前記アクティブ層上にゲート絶縁膜を形成する段階と;
前記アクティブ層上部のゲート絶縁膜上にゲート電極を形成する段階と;
前記アクティブ層に不純物をドーピングしてソース及びドレイン領域を形成する段階と;
前記ゲート電極上部にソース領域を露出する前記ソースコンタクトホールと前記ドレイン領域を露出するドレインコンタクトホールを有する層間絶縁膜を形成する段階と;
前記層間絶縁膜上部に前記ソースコンタクトホールを通して前記ソース領域と連結されるソース電極と前記ドレインコンタクトホールを通してドレイン領域と連結されるドレイン電極を形成する段階とを含む多結晶シリコン薄膜トランジスタの製造方法。 - 前記基板と非晶質シリコン層間にバッファ層を形成する段階をさらに含むことを特徴とする請求項8に記載の多結晶シリコン薄膜トランジスタの製造方法。
- 前記バッファ層は、シリコン酸化膜(SiO2 )でなることを特徴とする請求項9に記載の多結晶シリコン薄膜トランジスタの製造方法。
- 前記第1及び2温度各々は、500℃〜550℃の範囲であることを特徴とする請求項8に記載の多結晶シリコン薄膜トランジスタの製造方法。
- 基板上部に非晶質シリコン層を形成する段階と;
前記非晶質シリコン層の上部に触媒金属を蒸着する段階と;
前記触媒金属が蒸着された非晶質シリコン層上部に前記非晶質シリコン層と接触して第1方向に相互離隔された第1及び2電極と前記第1方向と垂直な第2方向に相互離隔された第3及び4電極を配置する段階と;
前記非晶質シリコン層を第1温度で加熱しながら同時に前記第1及び2電極に第1電圧を印加して前記第3及び4電極に第2電圧を印加して多結晶シリコン層を形成する段階と;
前記多結晶シリコン層をパターンしてアクティブ層を形成する段階と;
前記アクティブ層上にゲート絶縁膜を形成する段階と;
前記アクティブ層上部のゲート絶縁膜上にゲート電極を形成する段階と;
前記アクティブ層に不純物をドーピングしてソース及びドレイン領域を形成する段階と;
前記ゲート電極上部にソース領域を露出する前記ソースコンタクトホールと前記ドレイン領域を露出するドレインコンタクトホールを有する層間絶縁膜を形成する段階と;
前記層間絶縁膜上部に前記ソースコンタクトホールを通して前記ソース領域と連結されるソース電極と前記ドレインコンタクトホールを通してドレイン領域と連結されるドレイン電極を形成する段階とを含むことを特徴とする多結晶シリコン薄膜トランジスタの製造方法。 - 前記基板と非晶質シリコン層間にバッファ層を形成する段階をさらに含むことを特徴とする請求項12に記載の多結晶シリコン薄膜トランジスタの製造方法。
- 前記バッファ層は、シリコン酸化膜(SiO2 )でなることを特徴とする請求項13に記載の多結晶シリコン薄膜トランジスタの製造方法。
- 前記第1電圧は、第1電源から前記第1及び2電極に印加されて、前記第2電圧は第2電源から前記第3及び4電極に印加されることを特徴とする請求項12に記載の多結晶シリコン薄膜トランジスタの製造方法。
- 前記第1及び2電圧は、同一電圧であることを特徴とする請求項12に記載の多結晶シリコン薄膜トランジスタの製造方法。
- 前記第1及び第2電圧は、前記第1ないし4電極に連結された同一な電源から印加されることを特徴とする請求項16に記載の多結晶シリコン薄膜トランジスタの製造方法。
- 前記第1温度は、500℃〜550℃の範囲であることを特徴とする請求項12に記載の多結晶シリコン薄膜トランジスタの製造方法。
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KR1020020067881A KR100930362B1 (ko) | 2002-11-04 | 2002-11-04 | 다결정 실리콘막 형성방법과 이를 포함한박막트랜지스터의 제조방법 |
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KR100543717B1 (ko) * | 2003-05-27 | 2006-01-23 | 노재상 | 실리콘 박막의 어닐링 방법 및 그로부터 제조된 다결정실리콘 박막 |
KR100623693B1 (ko) * | 2004-08-25 | 2006-09-19 | 삼성에스디아이 주식회사 | 박막트랜지스터 제조 방법 |
TW200739731A (en) * | 2006-03-03 | 2007-10-16 | Jae-Sang Ro | Method for crystallization of amorphous silicon by joule heating |
WO2007145873A2 (en) * | 2006-06-05 | 2007-12-21 | Cohen Philip I | Growth of low dislocation density group-iii nitrides and related thin-film structures |
KR100811282B1 (ko) * | 2006-12-27 | 2008-03-07 | 주식회사 테라세미콘 | 다결정 실리콘 제조방법 |
KR100818287B1 (ko) * | 2007-01-10 | 2008-03-31 | 삼성전자주식회사 | 폴리 실리콘의 형성방법, 이 폴리 실리콘을 구비하는 박막트랜지스터 및 그 제조방법 |
WO2010123262A2 (ko) * | 2009-04-21 | 2010-10-28 | 주식회사 엔씰텍 | 다결정 실리콘 박막 제조장치 및 방법 |
KR101043788B1 (ko) * | 2009-04-21 | 2011-06-22 | 주식회사 엔씰텍 | 다결정 실리콘막의 제조방법 및 이를 포함하는 박막트랜지스터의 제조방법 |
KR101031882B1 (ko) * | 2009-05-08 | 2011-05-02 | 주식회사 엔씰텍 | 다결정 실리콘 박막 제조장치 및 방법 |
KR101084232B1 (ko) * | 2009-12-15 | 2011-11-16 | 삼성모바일디스플레이주식회사 | 박막 트랜지스터 제조 장치 |
CN102956710A (zh) * | 2011-08-23 | 2013-03-06 | 广东中显科技有限公司 | 掩膜金属诱导晶化的多晶硅薄膜晶体管 |
JP5995698B2 (ja) * | 2012-12-06 | 2016-09-21 | 富士フイルム株式会社 | 薄膜トランジスタ及びその製造方法、結晶性酸化物半導体薄膜及びその製造方法、表示装置、並びにx線センサ |
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DE69428387T2 (de) | 1993-02-15 | 2002-07-04 | Semiconductor Energy Lab | Herstellungsverfahren für eine kristallisierte Halbleiterschicht |
JP3193803B2 (ja) | 1993-03-12 | 2001-07-30 | 株式会社半導体エネルギー研究所 | 半導体素子の作製方法 |
US5624851A (en) | 1993-03-12 | 1997-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Process of fabricating a semiconductor device in which one portion of an amorphous silicon film is thermally crystallized and another portion is laser crystallized |
US5501989A (en) | 1993-03-22 | 1996-03-26 | Semiconductor Energy Laboratory Co., Ltd. | Method of making semiconductor device/circuit having at least partially crystallized semiconductor layer |
US5612250A (en) | 1993-12-01 | 1997-03-18 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device using a catalyst |
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US6309951B1 (en) * | 1998-06-10 | 2001-10-30 | Lg. Philips Lcd Co., Ltd. | Method for crystallizing amorphous silicon |
US6558986B1 (en) * | 1998-09-03 | 2003-05-06 | Lg.Philips Lcd Co., Ltd | Method of crystallizing amorphous silicon thin film and method of fabricating polysilicon thin film transistor using the crystallization method |
US6294442B1 (en) * | 1999-12-10 | 2001-09-25 | National Semiconductor Corporation | Method for the formation of a polysilicon layer with a controlled, small silicon grain size during semiconductor device fabrication |
KR20020035909A (ko) * | 2000-11-07 | 2002-05-16 | 한민구 | 다결정 실리콘 박막 트랜지스터의 제조방법 |
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CN1319123C (zh) | 2007-05-30 |
US20040203218A1 (en) | 2004-10-14 |
US6849525B2 (en) | 2005-02-01 |
KR100930362B1 (ko) | 2009-12-08 |
JP2004158850A (ja) | 2004-06-03 |
CN1499574A (zh) | 2004-05-26 |
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