JP3686318B2 - 半導体記憶装置の製造方法 - Google Patents

半導体記憶装置の製造方法 Download PDF

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Publication number
JP3686318B2
JP3686318B2 JP2000262160A JP2000262160A JP3686318B2 JP 3686318 B2 JP3686318 B2 JP 3686318B2 JP 2000262160 A JP2000262160 A JP 2000262160A JP 2000262160 A JP2000262160 A JP 2000262160A JP 3686318 B2 JP3686318 B2 JP 3686318B2
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JP
Japan
Prior art keywords
gate electrode
insulating film
region
forming
active region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000262160A
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English (en)
Japanese (ja)
Other versions
JP2002076149A5 (enExample
JP2002076149A (ja
Inventor
文彦 野呂
正気 小椋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2000262160A priority Critical patent/JP3686318B2/ja
Priority to TW090121501A priority patent/TW502451B/zh
Priority to US09/942,948 priority patent/US6558997B2/en
Publication of JP2002076149A publication Critical patent/JP2002076149A/ja
Priority to US10/366,481 priority patent/US6791139B2/en
Publication of JP2002076149A5 publication Critical patent/JP2002076149A5/ja
Application granted granted Critical
Publication of JP3686318B2 publication Critical patent/JP3686318B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2000262160A 2000-08-31 2000-08-31 半導体記憶装置の製造方法 Expired - Fee Related JP3686318B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000262160A JP3686318B2 (ja) 2000-08-31 2000-08-31 半導体記憶装置の製造方法
TW090121501A TW502451B (en) 2000-08-31 2001-08-30 Semiconductor memory and method for fabrication the same
US09/942,948 US6558997B2 (en) 2000-08-31 2001-08-31 Method for fabricating the control and floating gate electrodes without having their upper surface silicided
US10/366,481 US6791139B2 (en) 2000-08-31 2003-02-14 Semiconductor memory and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000262160A JP3686318B2 (ja) 2000-08-31 2000-08-31 半導体記憶装置の製造方法

Publications (3)

Publication Number Publication Date
JP2002076149A JP2002076149A (ja) 2002-03-15
JP2002076149A5 JP2002076149A5 (enExample) 2004-08-19
JP3686318B2 true JP3686318B2 (ja) 2005-08-24

Family

ID=18749880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000262160A Expired - Fee Related JP3686318B2 (ja) 2000-08-31 2000-08-31 半導体記憶装置の製造方法

Country Status (3)

Country Link
US (2) US6558997B2 (enExample)
JP (1) JP3686318B2 (enExample)
TW (1) TW502451B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20250102644A (ko) 2023-12-28 2025-07-07 엘티메탈 주식회사 다층구조 애노드 다공막 제조방법 및 이를 이용하여 제조된 애노드 다공막

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770933B2 (en) * 2002-12-11 2004-08-03 Texas Instruments Incorporated Single poly eeprom with improved coupling ratio
JP4541220B2 (ja) * 2005-04-13 2010-09-08 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP5086626B2 (ja) * 2006-12-15 2012-11-28 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置及びその製造方法
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
KR20100076227A (ko) * 2008-12-26 2010-07-06 주식회사 동부하이텍 반도체 소자 및 그 제조 방법
RU2641916C2 (ru) 2012-10-02 2018-01-23 Байер Кропсайенс Аг Гетероциклические соединения в качестве пестицидов
US11101277B2 (en) * 2019-03-20 2021-08-24 Greenliant Ip, Llc. Process for manufacturing NOR memory cell with vertical floating gate

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3059442B2 (ja) * 1988-11-09 2000-07-04 株式会社日立製作所 半導体記憶装置
JP2664685B2 (ja) * 1987-07-31 1997-10-15 株式会社東芝 半導体装置の製造方法
US5587332A (en) * 1992-09-01 1996-12-24 Vlsi Technology, Inc. Method of making flash memory cell
JPH06151780A (ja) * 1992-11-12 1994-05-31 Nippon Precision Circuits Kk 半導体装置
SE515560C2 (sv) * 1995-04-03 2001-08-27 Ericsson Telefon Ab L M Optiskt nät samt anordning och förfarande i detta
JP3149937B2 (ja) * 1997-12-08 2001-03-26 日本電気株式会社 半導体装置およびその製造方法
US6051860A (en) * 1998-01-16 2000-04-18 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit
JP3161408B2 (ja) 1998-03-03 2001-04-25 日本電気株式会社 半導体装置及びその製造方法
JP3175705B2 (ja) * 1998-09-18 2001-06-11 日本電気株式会社 不揮発性半導体記憶装置の製造方法
JP4212178B2 (ja) * 1999-03-12 2009-01-21 株式会社東芝 半導体集積回路の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20250102644A (ko) 2023-12-28 2025-07-07 엘티메탈 주식회사 다층구조 애노드 다공막 제조방법 및 이를 이용하여 제조된 애노드 다공막

Also Published As

Publication number Publication date
US6791139B2 (en) 2004-09-14
US20030116789A1 (en) 2003-06-26
TW502451B (en) 2002-09-11
US20020031018A1 (en) 2002-03-14
JP2002076149A (ja) 2002-03-15
US6558997B2 (en) 2003-05-06

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