JP3544895B2 - 樹脂封止型半導体装置及びその製造方法 - Google Patents
樹脂封止型半導体装置及びその製造方法 Download PDFInfo
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- JP3544895B2 JP3544895B2 JP21610899A JP21610899A JP3544895B2 JP 3544895 B2 JP3544895 B2 JP 3544895B2 JP 21610899 A JP21610899 A JP 21610899A JP 21610899 A JP21610899 A JP 21610899A JP 3544895 B2 JP3544895 B2 JP 3544895B2
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21610899A JP3544895B2 (ja) | 1999-07-30 | 1999-07-30 | 樹脂封止型半導体装置及びその製造方法 |
US09/536,405 US6538317B1 (en) | 1999-07-30 | 2000-03-28 | Substrate for resin-encapsulated semiconductor device, resin-encapsulated semiconductor device and process for fabricating the same |
TW089105702A TW454274B (en) | 1999-07-30 | 2000-03-28 | Substrate for resin-encapsulated semiconductor device, resin-encapsulated semiconductor device and process for fabricating the same |
KR1020000028322A KR100339473B1 (ko) | 1999-07-30 | 2000-05-25 | 수지 캡슐화된 반도체 장치용 기판, 수지 캡슐화된 반도체장치 및 이들의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21610899A JP3544895B2 (ja) | 1999-07-30 | 1999-07-30 | 樹脂封止型半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001044324A JP2001044324A (ja) | 2001-02-16 |
JP3544895B2 true JP3544895B2 (ja) | 2004-07-21 |
Family
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JP21610899A Expired - Fee Related JP3544895B2 (ja) | 1999-07-30 | 1999-07-30 | 樹脂封止型半導体装置及びその製造方法 |
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US (1) | US6538317B1 (zh) |
JP (1) | JP3544895B2 (zh) |
KR (1) | KR100339473B1 (zh) |
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Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6617680B2 (en) * | 2001-08-22 | 2003-09-09 | Siliconware Precision Industries Co., Ltd. | Chip carrier, semiconductor package and fabricating method thereof |
US20070045807A1 (en) * | 2005-09-01 | 2007-03-01 | Micron Technology, Inc. | Microelectronic devices and methods for manufacturing microelectronic devices |
CN101530011A (zh) * | 2006-11-30 | 2009-09-09 | 株式会社德山 | 金属化陶瓷基板芯片的制造方法 |
SG143098A1 (en) * | 2006-12-04 | 2008-06-27 | Micron Technology Inc | Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices |
JP5543058B2 (ja) | 2007-08-06 | 2014-07-09 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置の製造方法 |
JP2010021288A (ja) * | 2008-07-09 | 2010-01-28 | Elpida Memory Inc | 半導体装置の製造方法及び基板母体 |
JP5557439B2 (ja) | 2008-10-24 | 2014-07-23 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
JP5579982B2 (ja) * | 2008-12-15 | 2014-08-27 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置の中間構造体及び中間構造体の製造方法 |
JP2010278138A (ja) * | 2009-05-27 | 2010-12-09 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2011228603A (ja) | 2010-04-23 | 2011-11-10 | Elpida Memory Inc | 半導体装置の製造方法および半導体装置 |
JP2012028513A (ja) | 2010-07-22 | 2012-02-09 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP5666211B2 (ja) | 2010-09-01 | 2015-02-12 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 配線基板及び半導体装置の製造方法 |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8105875B1 (en) * | 2010-10-14 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Approach for bonding dies onto interposers |
US8936966B2 (en) | 2012-02-08 | 2015-01-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods for semiconductor devices |
CN103918071B (zh) | 2011-10-31 | 2016-09-21 | 株式会社村田制作所 | 电子部件、集合基板及电子部件的制造方法 |
JP5952032B2 (ja) * | 2012-03-07 | 2016-07-13 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
JP2013191690A (ja) | 2012-03-13 | 2013-09-26 | Shin Etsu Chem Co Ltd | 半導体装置及びその製造方法 |
CN102608811A (zh) * | 2012-03-22 | 2012-07-25 | 深圳市华星光电技术有限公司 | 液晶显示装置及其制造方法 |
JP5969883B2 (ja) | 2012-10-03 | 2016-08-17 | 信越化学工業株式会社 | 半導体装置の製造方法 |
JP2014103176A (ja) | 2012-11-16 | 2014-06-05 | Shin Etsu Chem Co Ltd | 支持基材付封止材、封止後半導体素子搭載基板、封止後半導体素子形成ウエハ、半導体装置、及び半導体装置の製造方法 |
CN103268862B (zh) | 2013-05-03 | 2016-12-28 | 日月光半导体制造股份有限公司 | 半导体封装构造及其制造方法 |
JP6125371B2 (ja) | 2013-08-15 | 2017-05-10 | 信越化学工業株式会社 | 半導体装置の製造方法 |
JP2019054172A (ja) * | 2017-09-15 | 2019-04-04 | 東芝メモリ株式会社 | 半導体装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5976912A (en) * | 1994-03-18 | 1999-11-02 | Hitachi Chemical Company, Ltd. | Fabrication process of semiconductor package and semiconductor package |
JP3127195B2 (ja) * | 1994-12-06 | 2001-01-22 | シャープ株式会社 | 発光デバイスおよびその製造方法 |
US5776798A (en) | 1996-09-04 | 1998-07-07 | Motorola, Inc. | Semiconductor package and method thereof |
JP2975979B2 (ja) * | 1996-12-30 | 1999-11-10 | アナムインダストリアル株式会社 | ボールグリッドアレイ半導体パッケージ用可撓性回路基板 |
US6077757A (en) * | 1997-05-15 | 2000-06-20 | Nec Corporation | Method of forming chip semiconductor devices |
KR100253116B1 (ko) * | 1997-07-07 | 2000-04-15 | 윤덕용 | Le방법을 이용한 칩사이즈 패키지의 제조방법 |
JP3020201B2 (ja) * | 1998-05-27 | 2000-03-15 | 亜南半導体株式会社 | ボールグリッドアレイ半導体パッケージのモールディング方法 |
JP3536728B2 (ja) * | 1998-07-31 | 2004-06-14 | セイコーエプソン株式会社 | 半導体装置及びテープキャリア並びにそれらの製造方法、回路基板、電子機器並びにテープキャリア製造装置 |
JP3556503B2 (ja) * | 1999-01-20 | 2004-08-18 | 沖電気工業株式会社 | 樹脂封止型半導体装置の製造方法 |
-
1999
- 1999-07-30 JP JP21610899A patent/JP3544895B2/ja not_active Expired - Fee Related
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2000
- 2000-03-28 TW TW089105702A patent/TW454274B/zh not_active IP Right Cessation
- 2000-03-28 US US09/536,405 patent/US6538317B1/en not_active Expired - Fee Related
- 2000-05-25 KR KR1020000028322A patent/KR100339473B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
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KR20010066801A (ko) | 2001-07-11 |
KR100339473B1 (ko) | 2002-06-03 |
TW454274B (en) | 2001-09-11 |
US6538317B1 (en) | 2003-03-25 |
JP2001044324A (ja) | 2001-02-16 |
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