JP4497304B2 - 半導体装置及びその製造方法 - Google Patents
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Description
樹脂充填後、所定の温度でキュアーして樹脂を硬化させて樹脂層33を形成する。
(1)半導体チップ2の電極3に厚さ50μm〜100μmの電極板5が接続され、この電極板5、電極3及び半導体チップ2の厚さの和が半導体装置1の高さとなることから、半導体装置1の薄型化が達成できる。
Claims (10)
- 第1の面及び該第1の面の反対側になる第2の面を有する半導体チップと、
それぞれが第1の面及び該第1の面の反対側になる第2の面を有する複数の配線ブロックであって、互いに独立分離している複数の配線ブロックとを有し、
前記半導体チップ及び前記複数の配線ブロックは、それぞれの前記第2の面が同一平面上に位置すると共に、前記半導体チップが前記複数の配線ブロックで挟み込まれるように配置され、かつ前記半導体チップ及び前記配線ブロックはそれぞれの前記第2の面が露出する状態で絶縁性の樹脂からなる封止体で覆われ、
前記複数の配線ブロックの各々は前記第1の面及び前記第2の面にそれぞれ電極を有し、かつ該第1の面及び第2の面の電極は前記配線ブロックを貫通して設けられる導体によって電気的に接続され、
前記複数の配線ブロックの各々の前記第1の面の電極と前記半導体チップの前記第1の面に設けられた電極とは前記封止体内に位置される導電性のワイヤでそれぞれ接続され、
前記半導体チップ及び前記複数の配線ブロックのそれぞれの前記第2の面と、前記封止体の下面は同一平面上に位置していることを特徴とする半導体装置。 - 第1の面及び該第1の面の反対側になる第2の面を有する複数の半導体チップと、
それぞれが第1の面及び該第1の面の反対側になる第2の面を有する複数の配線ブロックであって、互いに独立分離している複数の配線ブロックとを有し、
前記複数の半導体チップ及び前記複数の配線ブロックは、それぞれの前記第2の面が同一平面上に位置すると共に、前記半導体チップが前記複数の配線ブロックで挟み込まれるように配置され、かつ前記半導体チップ及び前記配線ブロックはそれぞれの前記第2の面が露出する状態で絶縁性の樹脂からなる封止体で覆われ、
前記複数の配線ブロックの各々は前記第1の面及び前記第2の面にそれぞれ電極を有し、かつ該第1の面及び第2の面の電極は前記配線ブロックを貫通して設けられる導体によって電気的に接続され、
前記複数の配線ブロックの各々の前記第1の面の電極と前記半導体チップの前記第1の面に設けられた電極とは前記封止体内に位置される導電性のワイヤでそれぞれ接続され、
前記複数の半導体チップ及び前記複数の配線ブロックのそれぞれの前記第2の面と、前記封止体の下面は同一平面上に位置していることを特徴とする半導体装置。 - 前記半導体チップ及び前記配線ブロック並びに前記封止体によって六面体が形成され、前記六面体の側面に前記配線ブロックの1面または2面が露出していることを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記配線ブロックの一部には窪みが設けられ、この窪んだ部分に前記封止体を形成する樹脂が食い込んでいることを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記配線ブロックの一部には前記配線ブロックの前記第1の面から前記第2の面に貫通する貫通孔が設けられ、該貫通孔に前記封止体を形成する樹脂が入り込んでいることを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記配線ブロックの前記第2の面の電極には突起電極が設けられていることを特徴とする請求項1または請求項2に記載の半導体装置。
- 前記配線ブロックの本体は、絶縁体で構成されることを特徴とする請求項1乃至6のいずれか一項に記載の半導体装置。
- 第1の面及び該第1の面の反対側になる第2の面にそれぞれ複数の電極を有し、かつ該第1の面及び第2の面の電極は導体によって電気的に接続されてなる配線ブロックを複数準備する工程と、
テープの所定領域からなる複数の製品形成部の上面にそれぞれ、前記複数の配線ブロックを前記第2の面が下面となる状態で所定パターンに貼り付けるとともに、前記所定パターンで貼り付けられた複数の配線ブロックに挟み込まれる位置に、電極が上面となる状態で半導体チップを貼り付ける工程と、
前記半導体チップの電極と前記複数の配線ブロックの前記第1の面の電極とを導電性のワイヤで電気的に接続する工程と、
前記複数の配線ブロック、前記半導体チップ及び前記ワイヤを覆うように前記テープ上に絶縁性の樹脂層を形成する工程と、
前記樹脂層の表面から前記テープの表面まで到達し、かつ隣接する前記製品形成部を分割する分離溝を形成する工程と、
前記テープを除去する工程と、によって複数の半導体装置を製造することを特徴とする半導体装置の製造方法。 - 前記テープの前記各製品形成部に前記複数の配線ブロックを貼り付ける工程において、前記配線ブロックの前記電極の配列パターンが異なる複数種類の配線ブロックを準備し、一部の前記製品形成部には他の製品形成部と異なる構造に前記半導体チップ及び前記複数の配線ブロックを貼り付けることを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記テープの製品形成部に複数の前記半導体チップ及び複数の前記配線ブロックを貼り付けることを特徴とする請求項8に記載の半導体装置の製造方法。
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US10847405B2 (en) * | 2017-08-31 | 2020-11-24 | Nichia Corporation | Method for manufacturing semiconductor device |
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JP2010114464A (ja) * | 2010-01-18 | 2010-05-20 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US10861895B2 (en) | 2018-11-20 | 2020-12-08 | Ningbo Semiconductor International Corporation | Image capturing assembly and packaging method thereof, lens module and electronic device |
CN111199986B (zh) * | 2018-11-20 | 2022-10-18 | 中芯集成电路(宁波)有限公司 | 摄像组件及其封装方法、镜头模组、电子设备 |
CN111199984B (zh) * | 2018-11-20 | 2022-12-02 | 中芯集成电路(宁波)有限公司 | 摄像组件及其封装方法、镜头模组、电子设备 |
CN111199985B (zh) * | 2018-11-20 | 2023-04-18 | 中芯集成电路(宁波)有限公司 | 摄像组件及其封装方法、镜头模组、电子设备 |
CN111370332B (zh) * | 2018-12-26 | 2023-04-18 | 中芯集成电路(宁波)有限公司 | 摄像组件的封装方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000323528A (ja) * | 1999-05-14 | 2000-11-24 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2001345336A (ja) * | 2000-06-02 | 2001-12-14 | Dainippon Printing Co Ltd | 半導体装置の作製方法と、それに用いられる配線部材 |
JP2002190552A (ja) * | 2000-12-20 | 2002-07-05 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2003133480A (ja) * | 2001-10-30 | 2003-05-09 | Sharp Corp | 半導体装置及び積層型半導体装置並びに半導体装置の製造方法及び積層型半導体装置の製造方法 |
JP2004087894A (ja) * | 2002-08-28 | 2004-03-18 | Ibiden Co Ltd | パッケージ部品およびその製造方法 |
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JP3670371B2 (ja) * | 1995-12-20 | 2005-07-13 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2000323528A (ja) * | 1999-05-14 | 2000-11-24 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2001345336A (ja) * | 2000-06-02 | 2001-12-14 | Dainippon Printing Co Ltd | 半導体装置の作製方法と、それに用いられる配線部材 |
JP2002190552A (ja) * | 2000-12-20 | 2002-07-05 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2003133480A (ja) * | 2001-10-30 | 2003-05-09 | Sharp Corp | 半導体装置及び積層型半導体装置並びに半導体装置の製造方法及び積層型半導体装置の製造方法 |
JP2004087894A (ja) * | 2002-08-28 | 2004-03-18 | Ibiden Co Ltd | パッケージ部品およびその製造方法 |
Cited By (1)
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US10847405B2 (en) * | 2017-08-31 | 2020-11-24 | Nichia Corporation | Method for manufacturing semiconductor device |
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