JP3180740B2 - キャパシタの製造方法 - Google Patents

キャパシタの製造方法

Info

Publication number
JP3180740B2
JP3180740B2 JP30878797A JP30878797A JP3180740B2 JP 3180740 B2 JP3180740 B2 JP 3180740B2 JP 30878797 A JP30878797 A JP 30878797A JP 30878797 A JP30878797 A JP 30878797A JP 3180740 B2 JP3180740 B2 JP 3180740B2
Authority
JP
Japan
Prior art keywords
amorphous silicon
silicon layer
hsg
impurity concentration
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30878797A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11145389A (ja
Inventor
秀二 藤原
俊幸 廣田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP30878797A priority Critical patent/JP3180740B2/ja
Priority to TW087118536A priority patent/TW408480B/zh
Priority to JP10318536A priority patent/JPH11214661A/ja
Priority to KR1019980048108A priority patent/KR100281262B1/ko
Priority to CNB981244823A priority patent/CN1151545C/zh
Priority to US09/190,023 priority patent/US6218230B1/en
Publication of JPH11145389A publication Critical patent/JPH11145389A/ja
Application granted granted Critical
Publication of JP3180740B2 publication Critical patent/JP3180740B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/75Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335Making a connection between the transistor and the capacitor, e.g. plug

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP30878797A 1997-11-11 1997-11-11 キャパシタの製造方法 Expired - Fee Related JP3180740B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP30878797A JP3180740B2 (ja) 1997-11-11 1997-11-11 キャパシタの製造方法
TW087118536A TW408480B (en) 1997-11-11 1998-11-06 The manufacture method of capacitor with semi-sphere shaped grain
JP10318536A JPH11214661A (ja) 1997-11-11 1998-11-10 Hsgを含むキャパシタの製造方法
KR1019980048108A KR100281262B1 (ko) 1997-11-11 1998-11-11 반구 그레인을 구비한 캐패시터의 제조 방법
CNB981244823A CN1151545C (zh) 1997-11-11 1998-11-11 带半球形晶粒的电容器下电极的制造方法
US09/190,023 US6218230B1 (en) 1997-11-11 1998-11-12 Method for producing capacitor having hemispherical grain

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30878797A JP3180740B2 (ja) 1997-11-11 1997-11-11 キャパシタの製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP10318536A Division JPH11214661A (ja) 1997-11-11 1998-11-10 Hsgを含むキャパシタの製造方法

Publications (2)

Publication Number Publication Date
JPH11145389A JPH11145389A (ja) 1999-05-28
JP3180740B2 true JP3180740B2 (ja) 2001-06-25

Family

ID=17985309

Family Applications (2)

Application Number Title Priority Date Filing Date
JP30878797A Expired - Fee Related JP3180740B2 (ja) 1997-11-11 1997-11-11 キャパシタの製造方法
JP10318536A Pending JPH11214661A (ja) 1997-11-11 1998-11-10 Hsgを含むキャパシタの製造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP10318536A Pending JPH11214661A (ja) 1997-11-11 1998-11-10 Hsgを含むキャパシタの製造方法

Country Status (5)

Country Link
US (1) US6218230B1 (zh)
JP (2) JP3180740B2 (zh)
KR (1) KR100281262B1 (zh)
CN (1) CN1151545C (zh)
TW (1) TW408480B (zh)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100363083B1 (ko) * 1999-01-20 2002-11-30 삼성전자 주식회사 반구형 그레인 커패시터 및 그 형성방법
JP3466102B2 (ja) * 1999-03-12 2003-11-10 沖電気工業株式会社 半導体装置及び半導体装置の製造方法
JP3246476B2 (ja) * 1999-06-01 2002-01-15 日本電気株式会社 容量素子の製造方法、及び、容量素子
US6420190B1 (en) 1999-06-04 2002-07-16 Seiko Epson Corporation Method of manufacturing ferroelectric memory device
KR20010005040A (ko) * 1999-06-30 2001-01-15 김영환 반도체 메모리소자의 커패시터 전하저장전극 형성방법
JP2001203334A (ja) 1999-11-10 2001-07-27 Mitsubishi Electric Corp キャパシタを有する半導体装置およびその製造方法
TW423153B (en) * 1999-11-18 2001-02-21 Taiwan Semiconductor Mfg Manufacturing method of the bottom electrode of DRAM capacitor
KR100606382B1 (ko) * 1999-12-28 2006-07-31 주식회사 하이닉스반도체 엠피에스를 이용한 실린더형 캐패시터 형성 방법 및 그를구비하는 반도체 소자
KR100338822B1 (ko) * 1999-12-30 2002-05-31 박종섭 반도체장치의 스토리지노드 전극 제조방법
KR100319170B1 (ko) * 1999-12-30 2001-12-29 박종섭 반도체소자의 캐패시터 형성방법
KR100345675B1 (ko) * 1999-12-30 2002-07-24 주식회사 하이닉스반도체 선택적 반구형 실리콘 그레인을 사용한 반도체 소자의전하저장 전극 형성방법
KR20010059998A (ko) * 1999-12-31 2001-07-06 박종섭 반도체소자의 캐패시터 형성방법
KR100351455B1 (ko) * 1999-12-31 2002-09-09 주식회사 하이닉스반도체 반도체장치의 스토리지노드 전극 형성방법
KR100379331B1 (ko) * 2000-01-25 2003-04-10 주식회사 하이닉스반도체 커패시터 하부 전극 및 그 제조 방법
KR100587046B1 (ko) * 2000-05-31 2006-06-07 주식회사 하이닉스반도체 반도체 소자의 전하저장 전극 제조 방법
DE10034005A1 (de) * 2000-07-07 2002-01-24 Infineon Technologies Ag Verfahren zum Erzeugen von Mikro-Rauhigkeiten auf einer Oberfläche
TW475207B (en) * 2000-07-24 2002-02-01 United Microelectronics Corp Method to improve hump phenomenon on surface of doped polysilicon layer
JP2002043547A (ja) * 2000-07-28 2002-02-08 Nec Kyushu Ltd 半導体装置およびその製造方法
KR100407987B1 (ko) * 2000-12-21 2003-12-01 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조 방법
KR20020061064A (ko) * 2001-01-12 2002-07-22 동부전자 주식회사 반도체장치의 스토리지노드 전극 제조방법
KR20020082544A (ko) * 2001-04-24 2002-10-31 주식회사 하이닉스반도체 반도체 소자의 캐패시터 하부 전극 형성방법
JP2003282733A (ja) 2002-03-26 2003-10-03 Oki Electric Ind Co Ltd 半導体記憶装置及びその製造方法
KR100429373B1 (ko) * 2002-04-24 2004-04-29 주식회사 하이닉스반도체 반도체소자의 커패시터 형성방법
KR100940112B1 (ko) * 2002-12-03 2010-02-02 매그나칩 반도체 유한회사 반도체소자의 아날로그 커패시터 제조방법
CN100414686C (zh) * 2003-12-03 2008-08-27 茂德科技股份有限公司 去除深沟槽结构中半球形晶粒硅层的方法
KR100620660B1 (ko) * 2004-06-17 2006-09-14 주식회사 하이닉스반도체 반도체 소자의 저장전극 제조 방법
US7538006B1 (en) * 2008-05-24 2009-05-26 International Business Machines Corporation Annular damascene vertical natural capacitor
US20100271962A1 (en) * 2009-04-22 2010-10-28 Motorola, Inc. Available backhaul bandwidth estimation in a femto-cell communication network
KR100992800B1 (ko) 2010-05-14 2010-11-08 주식회사 지씨에이치앤피 미량의 진세노사이드 성분이 증가된 신규한 가공인삼 또는 가공인삼추출물의 제조방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3039173B2 (ja) 1993-01-06 2000-05-08 日本電気株式会社 スタックト型dramのストレージノード電極の形成方法
JPH0714993A (ja) 1993-06-18 1995-01-17 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR0131744B1 (ko) * 1993-12-28 1998-04-15 김주용 반도체 소자의 캐패시터 제조방법
US5418180A (en) 1994-06-14 1995-05-23 Micron Semiconductor, Inc. Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon
JP2833545B2 (ja) 1995-03-06 1998-12-09 日本電気株式会社 半導体装置の製造方法
JP2827958B2 (ja) 1995-04-27 1998-11-25 日本電気株式会社 半導体記憶装置の容量素子の製造方法
JPH09298284A (ja) * 1996-05-09 1997-11-18 Nec Corp 半導体容量素子の形成方法
TW420871B (en) * 1999-01-08 2001-02-01 Taiwan Semiconductor Mfg Process for improving the characteristics of stack capacitors

Also Published As

Publication number Publication date
KR100281262B1 (ko) 2001-02-01
CN1217568A (zh) 1999-05-26
US6218230B1 (en) 2001-04-17
TW408480B (en) 2000-10-11
CN1151545C (zh) 2004-05-26
JPH11214661A (ja) 1999-08-06
KR19990045180A (ko) 1999-06-25
JPH11145389A (ja) 1999-05-28

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