JP2021119628A5 - Semiconductor devices, electronic devices, portable information terminals - Google Patents
Semiconductor devices, electronic devices, portable information terminals Download PDFInfo
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- JP2021119628A5 JP2021119628A5 JP2021077350A JP2021077350A JP2021119628A5 JP 2021119628 A5 JP2021119628 A5 JP 2021119628A5 JP 2021077350 A JP2021077350 A JP 2021077350A JP 2021077350 A JP2021077350 A JP 2021077350A JP 2021119628 A5 JP2021119628 A5 JP 2021119628A5
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- 239000004065 semiconductor Substances 0.000 title claims 7
- 238000006243 chemical reaction Methods 0.000 claims 42
- 229910052710 silicon Inorganic materials 0.000 claims 8
- 239000010703 silicon Substances 0.000 claims 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 4
- 229910052802 copper Inorganic materials 0.000 claims 4
- 239000010949 copper Substances 0.000 claims 4
Claims (6)
シリコンを有する第２の光電変換素子と、
ソースまたはドレインの一方が前記第１の光電変換素子のカソードと電気的に接続される第１のトランジスタと、
ソースまたはドレインの一方が前記第２の光電変換素子のカソードと電気的に接続される第２のトランジスタと、
ゲートが第１の導電層を介して前記第１のトランジスタのソースまたはドレインの他方、及び、前記第２のトランジスタのソースまたはドレインの他方と電気的に接続される第３のトランジスタと、
ソースまたはドレインの一方が前記第３のトランジスタのソースまたはドレインの一方と電気的に接続される第４のトランジスタと、
を有し、
前記第１の光電変換素子のアノードは、第２の導電層を介して第３の導電層と電気的に接続され、
前記第３のトランジスタのソースまたはドレインの他方は、第４の導電層と電気的に接続され、
前記第４のトランジスタのソースまたはドレインの他方は、信号を出力する配線として機能する第５の導電層と電気的に接続され、
前記第１の導電層、前記第２の導電層、前記第３の導電層、前記第４の導電層、及び、前記第５の導電層は、銅を有し、
前記第１の導電層及び前記第２の導電層は、第１の絶縁層に接して配置され、
前記第２の導電層及び前記第３の導電層は、前記第１の光電変換素子の受光面側とは逆側に配置され、
前記第１の光電変換素子の受光面側に配置された第２の絶縁層は、前記第１の光電変換素子の側面を覆う領域を有し、
平面視において、前記第１の導電層が延伸する方向は、前記第３の導電層が延伸する方向と交差し、
平面視において、前記第３の導電層が延伸する方向は、前記第４の導電層が延伸する方向と交差し、
平面視において、前記第１の導電層は、前記第１の絶縁層を介して前記第３の導電層と重なりを有し、
平面視において、前記第１の絶縁層に設けられ、前記第２の導電層と前記第３の導電層を電気的に接続するコンタクトホールは、前記第１の光電変換素子の受光面側に配置された遮光層と重なりを有する、半導体装置。 The first photoelectric conversion element having silicon and
A second photoelectric conversion element having silicon and
A first transistor in which one of the source and drain is electrically connected to the cathode of the first photoelectric conversion element.
A second transistor in which one of the source and drain is electrically connected to the cathode of the second photoelectric conversion element.
A third transistor in which the gate is electrically connected to the other of the source or drain of the first transistor and the other of the source or drain of the second transistor via a first conductive layer.
A fourth transistor in which one of the source or drain is electrically connected to one of the source or drain of the third transistor.
Have,
The anode of the first photoelectric conversion element is electrically connected to the third conductive layer via the second conductive layer.
The other of the source or drain of the third transistor is electrically connected to the fourth conductive layer.
The other of the source or drain of the fourth transistor is electrically connected to a fifth conductive layer that functions as a wiring that outputs a signal.
The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer have copper.
The first conductive layer and the second conductive layer are arranged in contact with the first insulating layer.
The second conductive layer and the third conductive layer are arranged on the side opposite to the light receiving surface side of the first photoelectric conversion element.
The second insulating layer arranged on the light receiving surface side of the first photoelectric conversion element has a region covering the side surface of the first photoelectric conversion element.
In a plan view, the direction in which the first conductive layer is stretched intersects with the direction in which the third conductive layer is stretched.
In a plan view, the direction in which the third conductive layer is stretched intersects with the direction in which the fourth conductive layer is stretched.
In a plan view, the first conductive layer has an overlap with the third conductive layer via the first insulating layer.
In a plan view, a contact hole provided in the first insulating layer and electrically connecting the second conductive layer and the third conductive layer is arranged on the light receiving surface side of the first photoelectric conversion element. A semiconductor device having an overlap with the light-shielding layer.
シリコンを有する第２の光電変換素子と、
ソースまたはドレインの一方が前記第１の光電変換素子のカソードと電気的に接続される第１のトランジスタと、
ソースまたはドレインの一方が前記第２の光電変換素子のカソードと電気的に接続される第２のトランジスタと、
ゲートが第１の導電層を介して前記第１のトランジスタのソースまたはドレインの他方、及び、前記第２のトランジスタのソースまたはドレインの他方と電気的に接続される第３のトランジスタと、
ソースまたはドレインの一方が前記第３のトランジスタのソースまたはドレインの一方と電気的に接続される第４のトランジスタと、
を有し、
前記第１の光電変換素子のアノードは、第２の導電層を介して第３の導電層と電気的に接続され、
前記第３のトランジスタのソースまたはドレインの他方は、第４の導電層と電気的に接続され、
前記第４のトランジスタのソースまたはドレインの他方は、信号を出力する配線として機能する第５の導電層と電気的に接続され、
前記第１の導電層、前記第２の導電層、前記第３の導電層、前記第４の導電層、及び、前記第５の導電層は、銅を有し、
前記第１の導電層及び前記第２の導電層は、第１の絶縁層に接して配置され、
前記第２の導電層及び前記第３の導電層は、前記第１の光電変換素子の受光面側とは逆側に配置され、
前記第１の光電変換素子の受光面側に配置された第２の絶縁層は、前記第１の光電変換素子の側面を覆う領域を有し、
平面視において、前記第１の導電層が延伸する方向は、前記第３の導電層が延伸する方向と交差し、
平面視において、前記第３の導電層が延伸する方向は、前記第４の導電層が延伸する方向と交差し、
平面視において、前記第１の導電層は、前記第１の絶縁層を介して前記第３の導電層と重なりを有し、
平面視において、前記第１の絶縁層に設けられ、前記第２の導電層と前記第３の導電層を電気的に接続するコンタクトホールは、前記第１の光電変換素子の受光面側に配置された遮光層と重なりを有し、
平面視において、前記コンタクトホールは、前記第１の光電変換素子のカソードと重ならないように配置される、半導体装置。 The first photoelectric conversion element having silicon and
A second photoelectric conversion element having silicon and
A first transistor in which one of the source and drain is electrically connected to the cathode of the first photoelectric conversion element.
A second transistor in which one of the source and drain is electrically connected to the cathode of the second photoelectric conversion element.
A third transistor in which the gate is electrically connected to the other of the source or drain of the first transistor and the other of the source or drain of the second transistor via a first conductive layer.
A fourth transistor in which one of the source or drain is electrically connected to one of the source or drain of the third transistor.
Have,
The anode of the first photoelectric conversion element is electrically connected to the third conductive layer via the second conductive layer.
The other of the source or drain of the third transistor is electrically connected to the fourth conductive layer.
The other of the source or drain of the fourth transistor is electrically connected to a fifth conductive layer that functions as a wiring that outputs a signal.
The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer have copper.
The first conductive layer and the second conductive layer are arranged in contact with the first insulating layer.
The second conductive layer and the third conductive layer are arranged on the side opposite to the light receiving surface side of the first photoelectric conversion element.
The second insulating layer arranged on the light receiving surface side of the first photoelectric conversion element has a region covering the side surface of the first photoelectric conversion element.
In a plan view, the direction in which the first conductive layer is stretched intersects with the direction in which the third conductive layer is stretched.
In a plan view, the direction in which the third conductive layer is stretched intersects with the direction in which the fourth conductive layer is stretched.
In a plan view, the first conductive layer has an overlap with the third conductive layer via the first insulating layer.
In a plan view, the contact hole provided in the first insulating layer and electrically connecting the second conductive layer and the third conductive layer is arranged on the light receiving surface side of the first photoelectric conversion element. It has an overlap with the light-shielding layer,
A semiconductor device in which the contact hole is arranged so as not to overlap the cathode of the first photoelectric conversion element in a plan view.
シリコンを有する第２の光電変換素子と、
ソースまたはドレインの一方が前記第１の光電変換素子のカソードと電気的に接続される第１のトランジスタと、
ソースまたはドレインの一方が前記第２の光電変換素子のカソードと電気的に接続される第２のトランジスタと、
ゲートが第１の導電層を介して前記第１のトランジスタのソースまたはドレインの他方、及び、前記第２のトランジスタのソースまたはドレインの他方と電気的に接続される第３のトランジスタと、
ソースまたはドレインの一方が前記第３のトランジスタのソースまたはドレインの一方と電気的に接続される第４のトランジスタと、
を有し、
前記第１の光電変換素子のアノードは、第２の導電層を介して第３の導電層と電気的に接続され、
前記第３のトランジスタのソースまたはドレインの他方は、第４の導電層と電気的に接続され、
前記第４のトランジスタのソースまたはドレインの他方は、信号を出力する配線として機能する第５の導電層と電気的に接続され、
前記第１の導電層、前記第２の導電層、前記第３の導電層、前記第４の導電層、及び、前記第５の導電層は、銅を有し、
前記第１の導電層及び前記第２の導電層は、第１の絶縁層に接して配置され、
前記第２の導電層及び前記第３の導電層は、前記第１の光電変換素子の受光面側とは逆側に配置され、
前記第１の光電変換素子の受光面側に配置された第２の絶縁層は、前記第１の光電変換素子の側面を覆う領域を有し、
平面視において、前記第１の導電層が延伸する方向は、前記第３の導電層が延伸する方向と交差し、
平面視において、前記第３の導電層が延伸する方向は、前記第４の導電層が延伸する方向と交差し、
平面視において、前記第１の導電層は、前記第１の絶縁層を介して前記第３の導電層と重なりを有し、
平面視において、前記第１の絶縁層に設けられ、前記第２の導電層と前記第３の導電層を電気的に接続するコンタクトホールは、前記第１の光電変換素子の受光面側に配置された遮光層と重なりを有し、
平面視において、前記第１の光電変換素子のカソードの全体は、前記第１の光電変換素子のアノードと重なるように配置される、半導体装置。 The first photoelectric conversion element having silicon and
A second photoelectric conversion element having silicon and
A first transistor in which one of the source and drain is electrically connected to the cathode of the first photoelectric conversion element.
A second transistor in which one of the source and drain is electrically connected to the cathode of the second photoelectric conversion element.
A third transistor in which the gate is electrically connected to the other of the source or drain of the first transistor and the other of the source or drain of the second transistor via a first conductive layer.
A fourth transistor in which one of the source or drain is electrically connected to one of the source or drain of the third transistor.
Have,
The anode of the first photoelectric conversion element is electrically connected to the third conductive layer via the second conductive layer.
The other of the source or drain of the third transistor is electrically connected to the fourth conductive layer.
The other of the source or drain of the fourth transistor is electrically connected to a fifth conductive layer that functions as a wiring that outputs a signal.
The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer have copper.
The first conductive layer and the second conductive layer are arranged in contact with the first insulating layer.
The second conductive layer and the third conductive layer are arranged on the side opposite to the light receiving surface side of the first photoelectric conversion element.
The second insulating layer arranged on the light receiving surface side of the first photoelectric conversion element has a region covering the side surface of the first photoelectric conversion element.
In a plan view, the direction in which the first conductive layer is stretched intersects with the direction in which the third conductive layer is stretched.
In a plan view, the direction in which the third conductive layer is stretched intersects with the direction in which the fourth conductive layer is stretched.
In a plan view, the first conductive layer has an overlap with the third conductive layer via the first insulating layer.
In a plan view, the contact hole provided in the first insulating layer and electrically connecting the second conductive layer and the third conductive layer is arranged on the light receiving surface side of the first photoelectric conversion element. It has an overlap with the light-shielding layer,
A semiconductor device in which the entire cathode of the first photoelectric conversion element is arranged so as to overlap the anode of the first photoelectric conversion element in a plan view.
シリコンを有する第２の光電変換素子と、
ソースまたはドレインの一方が前記第１の光電変換素子のカソードと電気的に接続される第１のトランジスタと、
ソースまたはドレインの一方が前記第２の光電変換素子のカソードと電気的に接続される第２のトランジスタと、
ゲートが第１の導電層を介して前記第１のトランジスタのソースまたはドレインの他方、及び、前記第２のトランジスタのソースまたはドレインの他方と電気的に接続される第３のトランジスタと、
ソースまたはドレインの一方が前記第３のトランジスタのソースまたはドレインの一方と電気的に接続される第４のトランジスタと、
を有し、
前記第１の光電変換素子のアノードは、第２の導電層を介して第３の導電層と電気的に接続され、
前記第３のトランジスタのソースまたはドレインの他方は、第４の導電層と電気的に接続され、
前記第４のトランジスタのソースまたはドレインの他方は、信号を出力する配線として機能する第５の導電層と電気的に接続され、
前記第１の導電層、前記第２の導電層、前記第３の導電層、前記第４の導電層、及び、前記第５の導電層は、銅を有し、
前記第１の導電層及び前記第２の導電層は、第１の絶縁層に接して配置され、
前記第２の導電層及び前記第３の導電層は、前記第１の光電変換素子の受光面側とは逆側に配置され、
前記第１の光電変換素子の受光面側に配置された第２の絶縁層は、前記第１の光電変換素子の側面を覆う領域を有し、
平面視において、前記第１の導電層が延伸する方向は、前記第３の導電層が延伸する方向と交差し、
平面視において、前記第３の導電層が延伸する方向は、前記第４の導電層が延伸する方向と交差し、
平面視において、前記第１の導電層は、前記第１の絶縁層を介して前記第３の導電層と重なりを有し、
平面視において、前記第１の絶縁層に設けられ、前記第２の導電層と前記第３の導電層を電気的に接続するコンタクトホールは、前記第１の光電変換素子の受光面側に配置された遮光層と重なりを有し、
平面視において、前記コンタクトホールは、前記第１の光電変換素子のカソードと重ならないように配置され、
平面視において、前記第１の光電変換素子のカソードの全体は、前記第１の光電変換素子のアノードと重なるように配置される、半導体装置。 The first photoelectric conversion element having silicon and
A second photoelectric conversion element having silicon and
A first transistor in which one of the source and drain is electrically connected to the cathode of the first photoelectric conversion element.
A second transistor in which one of the source and drain is electrically connected to the cathode of the second photoelectric conversion element.
A third transistor in which the gate is electrically connected to the other of the source or drain of the first transistor and the other of the source or drain of the second transistor via a first conductive layer.
A fourth transistor in which one of the source or drain is electrically connected to one of the source or drain of the third transistor.
Have,
The anode of the first photoelectric conversion element is electrically connected to the third conductive layer via the second conductive layer.
The other of the source or drain of the third transistor is electrically connected to the fourth conductive layer.
The other of the source or drain of the fourth transistor is electrically connected to a fifth conductive layer that functions as a wiring that outputs a signal.
The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer have copper.
The first conductive layer and the second conductive layer are arranged in contact with the first insulating layer.
The second conductive layer and the third conductive layer are arranged on the side opposite to the light receiving surface side of the first photoelectric conversion element.
The second insulating layer arranged on the light receiving surface side of the first photoelectric conversion element has a region covering the side surface of the first photoelectric conversion element.
In a plan view, the direction in which the first conductive layer is stretched intersects with the direction in which the third conductive layer is stretched.
In a plan view, the direction in which the third conductive layer is stretched intersects with the direction in which the fourth conductive layer is stretched.
In a plan view, the first conductive layer has an overlap with the third conductive layer via the first insulating layer.
In a plan view, the contact hole provided in the first insulating layer and electrically connecting the second conductive layer and the third conductive layer is arranged on the light receiving surface side of the first photoelectric conversion element. It has an overlap with the light-shielding layer,
In a plan view, the contact hole is arranged so as not to overlap the cathode of the first photoelectric conversion element.
A semiconductor device in which the entire cathode of the first photoelectric conversion element is arranged so as to overlap the anode of the first photoelectric conversion element in a plan view.
前記半導体装置を有する、電子機器。 In any one of claims 1 to 4,
An electronic device having the semiconductor device.
前記半導体装置とＣＰＵとアンテナとを有する、携帯型情報端末。 In any one of claims 1 to 4,
A portable information terminal having the semiconductor device, a CPU, and an antenna.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010190239 | 2010-08-27 | ||
| JP2010190239 | 2010-08-27 | ||
| JP2011107813 | 2011-05-13 | ||
| JP2011107813 | 2011-05-13 | ||
| JP2021008392A JP7174784B2 (en) | 2010-08-27 | 2021-01-22 | semiconductor equipment |
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| JP2021008392A Division JP7174784B2 (en) | 2010-08-27 | 2021-01-22 | semiconductor equipment |
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| JP2021119628A JP2021119628A (en) | 2021-08-12 |
| JP6934124B2 JP6934124B2 (en) | 2021-09-08 |
| JP2021119628A5 true JP2021119628A5 (en) | 2021-09-24 |
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| JP2011182218A Expired - Fee Related JP5763474B2 (en) | 2010-08-27 | 2011-08-24 | Optical sensor |
| JP2015117169A Expired - Fee Related JP6153966B2 (en) | 2010-08-27 | 2015-06-10 | Optical sensor |
| JP2017107335A Withdrawn JP2017216453A (en) | 2010-08-27 | 2017-05-31 | Photosensor |
| JP2019222826A Active JP6771083B2 (en) | 2010-08-27 | 2019-12-10 | Semiconductor device |
| JP2020009893A Active JP6871443B2 (en) | 2010-08-27 | 2020-01-24 | Semiconductor device |
| JP2020161687A Active JP6829790B2 (en) | 2010-08-27 | 2020-09-28 | Semiconductor device |
| JP2021008392A Active JP7174784B2 (en) | 2010-08-27 | 2021-01-22 | semiconductor equipment |
| JP2021077350A Active JP6934124B2 (en) | 2010-08-27 | 2021-04-30 | Semiconductor devices, electronic devices, portable information terminals |
| JP2022177828A Active JP7407891B2 (en) | 2010-08-27 | 2022-11-07 | semiconductor equipment |
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| JP2015117169A Expired - Fee Related JP6153966B2 (en) | 2010-08-27 | 2015-06-10 | Optical sensor |
| JP2017107335A Withdrawn JP2017216453A (en) | 2010-08-27 | 2017-05-31 | Photosensor |
| JP2019222826A Active JP6771083B2 (en) | 2010-08-27 | 2019-12-10 | Semiconductor device |
| JP2020009893A Active JP6871443B2 (en) | 2010-08-27 | 2020-01-24 | Semiconductor device |
| JP2020161687A Active JP6829790B2 (en) | 2010-08-27 | 2020-09-28 | Semiconductor device |
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| JP2009295908A (en) * | 2008-06-09 | 2009-12-17 | Mitsubishi Electric Corp | Photosensor, and method of manufacturing the same |
| JP5371330B2 (en) * | 2008-08-29 | 2013-12-18 | キヤノン株式会社 | Solid-state imaging device |
| JP2010062276A (en) * | 2008-09-03 | 2010-03-18 | Brother Ind Ltd | Oxide thin-film transistor and method of manufacturing the same |
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| JP5587592B2 (en) * | 2008-11-07 | 2014-09-10 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| JP5231179B2 (en) | 2008-11-12 | 2013-07-10 | ペンタックスリコーイメージング株式会社 | Image sensor |
| TWI585955B (en) * | 2008-11-28 | 2017-06-01 | 半導體能源研究所股份有限公司 | Photosensor and display device |
| JP5029624B2 (en) * | 2009-01-15 | 2012-09-19 | ソニー株式会社 | Solid-state imaging device and electronic apparatus |
| JP5109999B2 (en) | 2009-02-05 | 2012-12-26 | セイコーエプソン株式会社 | Display device, electronic apparatus, and driving method of display device |
| JP4798232B2 (en) * | 2009-02-10 | 2011-10-19 | ソニー株式会社 | Solid-state imaging device, manufacturing method thereof, and electronic apparatus |
| KR102180761B1 (en) * | 2009-09-24 | 2020-11-19 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Oxide semiconductor film and semiconductor device |
| WO2011040213A1 (en) * | 2009-10-01 | 2011-04-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| KR101645680B1 (en) * | 2009-11-06 | 2016-08-04 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| JP5763474B2 (en) | 2010-08-27 | 2015-08-12 | 株式会社半導体エネルギー研究所 | Optical sensor |
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2011
- 2011-08-24 JP JP2011182218A patent/JP5763474B2/en not_active Expired - Fee Related
- 2011-08-25 US US13/217,553 patent/US8928053B2/en active Active
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- 2015-06-10 JP JP2015117169A patent/JP6153966B2/en not_active Expired - Fee Related
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2017
- 2017-05-31 JP JP2017107335A patent/JP2017216453A/en not_active Withdrawn
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- 2019-12-10 JP JP2019222826A patent/JP6771083B2/en active Active
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- 2020-01-24 JP JP2020009893A patent/JP6871443B2/en active Active
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