JP4666383B2 - Amplification type solid-state imaging device and electronic information device - Google Patents

Description

  The present invention relates to an amplification type solid-state imaging device such as an APS type image sensor in which a charge amplification unit capable of sequentially amplifying signal charges from a plurality of photoelectric conversion units is provided in common to the plurality of photoelectric conversion units, and The present invention relates to digital information cameras, such as digital video cameras and digital still cameras, and electronic information devices such as image input cameras, scanners, facsimiles, and camera-equipped mobile phone devices that use this amplification type solid-state imaging device as an image input device in an imaging unit. .

  Conventionally, this type of amplification type solid-state imaging device has a pixel portion having a signal charge amplification function and a scanning circuit provided around the pixel portion, and the scanning circuit provides pixel data from the pixel portion. An amplification-type solid-state imaging device for reading out the image has been proposed. In particular, there is known an APS (Active Pixel Sensor) type image sensor constituted by CMOS (Complementary Metal Oxide Semiconductor) which is advantageous for integrating a pixel configuration with a peripheral driving circuit and a signal processing circuit.

  In this APS type image sensor, it is usually necessary to form a photoelectric conversion unit, an amplification unit, a pixel selection unit, and a reset unit in one pixel unit. For this reason, in the APS type image sensor, three to four MOS transistors are usually used in addition to the photoelectric conversion unit made of a photodiode.

  However, if 3 to 4 MOS transistors are required per pixel portion, it becomes a restriction for reducing the pixel size. For example, in Patent Document 1, the number of transistors per pixel portion is reduced. A method has been proposed.

  FIG. 12 is a circuit diagram illustrating a configuration example of a main part of a conventional amplification type solid-state imaging device disclosed in Patent Document 1. In FIG. Note that FIG. 12 shows only the i-th column of the (m, 1) -th row and the (m, 2) -th row among the pixel portions arranged in a matrix in a plurality of rows and columns. However, m and i are natural numbers.

  In FIG. 12, a conventional amplification type solid-state imaging device 100 includes a photodiode 101 as a photoelectric conversion element, a transfer transistor 102, an amplification transistor 103, a reset transistor 104, and a selection transistor 105. Yes.

  It is known that the photodiode 101 is a buried type, and if the signal charge transfer from the photodiode 101 is completely performed, it is possible to obtain a high-quality image with extremely low noise.

  The transfer transistor 102 is composed of an N-channel MOS transistor, and is controlled by a driving pulse φT supplied to the gate to transfer the signal charge accumulated in the photodiode 101. Here, two transfer transistors 102 in the (m, 1) th row and the i-th column and the (m, 2) th row and the i-th column adjacent to each other in the vertical direction are respectively connected to the drive pulse φT (m, 1) and φT (m, 2) is supplied. A signal charge storage unit 106 is connected in common to the output sides of these two transfer transistors 102.

  The amplification transistor 103 is composed of an N-channel MOS transistor, the gate is connected to the signal charge storage unit 106, the source is connected to the signal line 107 via the selection transistor 105, and the drain is connected to the potential supply line 108. The source follower circuit is configured together with the constant current load transistor 109 connected between the signal line 107 and the ground potential GND.

  The reset transistor 104 is composed of an N-channel MOS transistor, and the signal charge storage unit 106 is connected to the source, the potential supply line 108 is connected to the drain, and the charge is controlled by the drive pulse φR supplied to the gate. The potential of the storage unit 106 is reset with the potential of the potential supply line 108.

  The selection transistor 105 is an N-channel MOS transistor, is connected between the source of the amplification MOS transistor 103 and the signal line 107, and is selected and controlled by a drive pulse φS supplied to the gate. A signal corresponding to the signal charge from the pixel portion is read out to the signal line 107.

  The operation of the conventional amplification type solid-state imaging device 100 having the above configuration will be described in detail with reference to FIG.

  FIG. 13 shows signal waveforms of the drive pulses φS (m), φR (m), φT (m, 1) and φT (m, 2) of the conventional amplification type solid-state imaging device 100 of FIG. FIG. 6 is a timing chart showing potentials of the charge storage unit 106 and the signal line 107, respectively.

  As shown in FIG. 13, first, in the period T1, the voltage is applied to the gate of the reset transistor 104 common to the two pixel portions of the (m, 1) th row and the i-th column and the (m, 2) th row and the i-th column. The drive pulse φR (m) to be driven becomes high level, the reset transistor 104 is turned on, and the potential potential under the gate rises. This causes a charge transfer from the signal charge storage unit 106 common to the two pixel units of the (m, 1) th row and the i-th column and the (m, 2) th row and the i-th column to the drain side of the reset transistor 104. The potential of the signal charge storage unit 106 is reset to the power supply potential Vdd.

  Next, in the period T2, a driving pulse φR (applied to the gate of the reset transistor 104 common to the two pixel portions of the (m, 1) th row and the i-th column and the (m, 2) th row and the i-th column. m) becomes a low level, and the reset transistor 104 is turned off. However, the drive pulse φS (m) applied to the gate of the selection transistor 105 common to the two pixel portions of the (m, 1) th row and the i-th column and the (m2, 2) th row and the i-th column is high. Since the selection transistor 105 is in the ON state, the reset level is common to the two pixel portions of the (m, 1) th row and the i-th column and the (m, 2) th row and the i-th column. Data is read out to the signal line 107 through the amplifying transistor 103. At this time, the amplification transistor 103 and the constant current load transistor 109 form a source follower circuit. Accordingly, the potential of the signal line 107 becomes a high voltage Vsig (i) in the periods T1 and T2.

  Further, in the period T3, the drive pulse φT (m, 1) applied to the gates of the transfer transistors 102 in the (m, 1) th row becomes high level, and the transfer transistors 102 in the (m, 1) th row are turned on. Since the potential potential under the gate rises, the signal charge accumulated in the photodiodes 101 in the (m, 1) th row is transferred to the signal charge accumulation unit 106 through the transfer transistor 102. As a result, the potential of the signal charge storage unit 106 decreases by the amount of the transferred signal charge, and the signal amplified by the amplification transistor 103 in accordance with the decreased potential of the signal charge storage unit 106 is selected. To the signal line 107 and the potential of the signal line 107 also decreases.

  Subsequently, in the period T4, the drive pulse φT (m, 1) applied to the gates of the transfer transistors 102 in the (m, 1) th row becomes a low level, and the transfer transistors 102 in the (m, 1) th row become low. Turns off. As a result, the common signal charge storage unit 106 holds the potential at the time of signal charge transfer, and the signal level of the pixel unit in the (m, 1) -th row is the (m, 1) -th row and the i-th column. m, 2) The signal amplified by the amplifying transistor 103 common to the two pixel portions in the row and i-th column is read out to the signal line 107 via the selection transistor 105.

  After the period T4, the drive pulse φS (m) applied to the gate of the common selection transistor 105 is at a low level, and the selection transistor 105 is turned off, so that the potential of the signal line 107 is at a low level. Become.

  After one horizontal scanning period (1H), signal charges from the photodiodes 101 in the (m, 2) -th row are transferred to the (m, 2) -th row with respect to the pixel portion in the next (m, 2) -th row. Reset transistor 104, amplifying transistor 103, and selection transistor common to the two pixel portions of (m, 1) th row and i-th column and (m, 2) th row and i-th column. The operation similar to that in the period T1 to T4 is repeatedly performed.

In the conventional amplification type solid-state imaging device 100, when the signal charge accumulation unit 106, the amplification transistor 103, the reset transistor 104, and the selection transistor 105 that are common to every two pixel units are provided, a photo as a photoelectric conversion element Since the diode 101 and the transfer transistor 102 are provided for each pixel portion, 2.5 transistors are required for each pixel portion. Accordingly, the number of transistors per pixel portion can be reduced. Further, for example, when the signal charge storage unit 106, the amplification transistor 103, the reset transistor 104, and the selection transistor 105 that are common to every four pixel units are provided, 1.75 transistors are provided for each pixel unit. Needed. Therefore, the number of transistors per pixel portion can be further reduced.
Japanese Patent Laid-Open No. 9-46596

  However, the conventional amplification type solid-state imaging device has the following problems.

The charge-voltage conversion efficiency η for converting the signal charge ΔQsig from the photodiode 101 into the voltage signal ΔVsig is as follows:
η = G × ΔVsig / ΔQsig = G / CFD
It becomes. In the above equation, G is the gain of the source follower circuit constituted by the amplifying transistor 103 and the constant current load transistor 109, and normally shows a value (˜0.9) slightly smaller than “1”. In order to increase the charge-voltage conversion efficiency η, it is necessary to reduce the capacitance CFD of the signal charge storage unit 106.

  The capacitance CFD of the signal charge storage unit 106 includes a drain side junction capacitance of the transfer transistor 102 connected to the signal charge storage unit 106, a gate capacitance of the amplification transistor 103, a junction capacitance with the substrate, and coupling between wirings. Total capacity. Accordingly, there is a problem that the charge-voltage conversion rate η decreases as the number of photodiodes 101 and transfer transistors 102 connected to the common signal charge storage unit 106 increases.

  The present invention solves the above-described conventional problems, and a signal charge storage unit is shared by a plurality of pixel units to reduce the pixel size and increase the charge-voltage conversion rate to obtain a high-quality image. It is an object of the present invention to provide an amplification type solid-state imaging device capable of performing the above and an electronic information device using the amplification type solid-state imaging device as an image input device in an imaging unit.

  The amplification type solid-state imaging device of the present invention is an amplification type solid-state imaging device provided with a common charge amplification unit so that signal charges from a plurality of photoelectric conversion units can be sequentially amplified. A feedback circuit that feeds back the potential to the potential supply line of the charge amplifying unit is provided, thereby achieving the above object.

The amplification type solid-state imaging device of the present invention includes, for each pixel unit, a photoelectric conversion unit including a photoelectric conversion unit and a charge transfer unit for transferring a signal charge from the photoelectric conversion unit,
A charge amplifying unit that is provided in common for each of the plurality of pixel units and amplifies each signal charge from the photoelectric conversion transfer unit and can read the signal charge to the signal line, and the potential of the signal line is the potential of the charge amplifying unit And a feedback circuit for feeding back to the supply line, whereby the above object is achieved.

  Preferably, the photoelectric conversion unit in the amplification type solid-state imaging device of the present invention is constituted by an embedded photodiode.

  Further preferably, the charge amplifying unit in the amplification type solid-state imaging device of the present invention has an input unit connected to a signal charge storage unit provided in common on the output side of the signal charge from the photoelectric conversion unit and outputs the same. Is connected to a signal line, supplied with a potential from the potential supply line, amplified according to the amount of signal charge stored in the signal charge storage section, and the output potential read out to the signal line.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the charge amplification unit is an amplification in which the signal charge storage unit is connected to the gate as the input unit, and the signal line is connected to the source as the output unit. Transistor.

  Further, preferably, a source follower circuit is configured by the amplification transistor in the amplification type solid-state imaging device of the present invention and the constant current load transistor connected between the signal line and the ground potential.

  Further preferably, in the amplification type solid-state imaging device according to the present invention, the charge amplification unit includes a selection transistor connected between the source of the amplification transistor and the signal line, and a source connected to the signal charge storage unit. The amplifying transistor and each drain of the reset transistor are connected to the potential supply line.

  Further preferably, in the feedback circuit in the amplification type solid-state imaging device of the present invention, the output potential of the charge amplification unit is input to the input unit, and the output potential according to the output potential of the charge amplification unit is output from the output unit to the potential. A transistor circuit output to the supply line;

  Further preferably, in the transistor circuit in the amplification type solid-state imaging device of the present invention, the signal line is connected to the gate as the input unit, and the potential supply line of the charge amplification unit is connected to the source as the output unit. A MOS transistor having a drain grounded, and a constant current load transistor connected between the source of the MOS transistor and a power supply potential.

  Furthermore, it preferably further includes a switch circuit for switching and connecting the potential supply unit and the output unit of the feedback circuit to the potential supply line of the charge amplification unit in the amplification type solid-state imaging device of the present invention.

  Further preferably, the power supply potential is supplied from the potential supply unit in the amplification type solid-state imaging device of the present invention.

  Further preferably, the switch circuit in the amplification type solid-state imaging device of the present invention selects the output unit side of the feedback circuit during the signal charge readout period, and selects the potential supply unit side during the signal charge readout period.

  Further preferably, the switch circuit in the amplification type solid-state imaging device of the present invention has two switching transistors each supplied with a reverse-phase pulse signal to each gate, and one of the switching transistors supplies the potential. And the other switching transistor is connected between the output part of the feedback circuit and the potential supply line of the charge amplification part.

  Further, preferably, the potential of the potential supply line is controlled by controlling and outputting the output potential from the potential supply unit in the amplification type solid-state imaging device of the present invention.

  Further preferably, the charge amplification unit in the amplification type solid-state imaging device of the present invention further includes a reset transistor having a source connected to the signal charge storage unit, and the amplification transistor and the drain of the reset transistor are connected to the potential. Connected to the supply line, the source of the amplifying transistor is connected to the signal line.

  Further preferably, in the amplification type solid-state imaging device of the present invention, by controlling the potential of the potential supply line to a low potential (low voltage that cannot be operated) such that the charge amplification unit does not perform an output operation, The output operation of the charge amplification unit can be stopped by holding the potential of the signal charge storage unit at the low potential. Further, the output operation of the charge amplifying unit may be stopped by setting and controlling the potential of the potential supply line to the ground potential to hold the potential of the signal charge storage unit at the ground potential.

  Further preferably, the switch circuit in the amplification type solid-state imaging device of the present invention includes a CMOS type switch circuit connected between the potential supply unit and a potential supply line of the charge amplification unit, and an output unit of the feedback circuit. A switching transistor connected between the potential supply lines of the charge amplifying unit.

  Furthermore, it preferably further includes a switch circuit for switching and connecting a constant power supply potential and the constant current load circuit to the output section of the charge amplification section in the amplification type solid-state imaging device of the present invention.

  Furthermore, it is preferable that the output operation of the charge amplification unit can be stopped by short-circuiting the input unit and the output unit of the charge amplification unit in the amplification type solid-state imaging device of the present invention.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the charge amplification unit further includes a reset transistor having a source connected to the signal charge storage unit, and the drain of the reset transistor is connected to the amplification transistor. And connected to the potential supply line and to the signal line.

  The electronic information device of the present invention is one in which an image is taken using the amplification type solid-state imaging device of the present invention as an imaging unit, thereby achieving the above object.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, as in the prior art of Patent Document 1, the signal charge accumulating unit and the charge amplifying unit are provided in common for at least two pixels to reduce the number of transistors per pixel unit. The amplification type solid-state imaging device includes a feedback circuit that feeds back the potential of the signal line to the potential supply line of the charge amplification unit. As a result, the potential of the potential supply line of the charge amplifying unit also changes in accordance with the change in potential of the signal line, so that the coupling capacitance between the signal charge storage unit and the potential supply line can be apparently reduced. . As a result, the parasitic capacitance in the signal charge storage unit is reduced, the charge-voltage conversion efficiency is increased, and high sensitivity of the solid-state imaging device can be achieved. In short, since V = Q / C, the charge Q is constant, and the voltage sensitivity of the voltage V can be increased by reducing the capacitance C.

  In addition, by making the photoelectric conversion element an embedded photodiode, the signal charge from the photoelectric conversion element can be completely transferred by the transfer transistor, and a higher-quality image with reduced noise can be obtained. Become.

  Further, the charge amplification unit has a signal charge storage unit connected to the gate as its input unit, and an amplification MOS transistor having a signal line connected to its source as its output unit, and between the signal line and the ground potential. A source follower circuit can be configured with the connected constant current load transistors. The feedback circuit includes a MOS transistor having a signal line connected to a gate as a feedback input unit, a potential supply line of a charge amplification unit connected to a source as a feedback output unit, and a drain grounded, and the MOS A source follower circuit can be configured by a constant current load transistor connected between the source of the transistor and the power supply potential. According to this configuration, since the feedback circuit is a positive feedback with a gain “1” or less, the feedback can be stably controlled when the potential of the signal line is fed back to the potential supply line of the charge amplifying unit. Become.

  Further, a switch circuit for switching and connecting the potential supply terminal and the output part of the feedback circuit to the potential supply line of the charge amplification unit is further provided, and the potential supply line is not operated without operating the feedback circuit except during the readout period. By connecting to the potential supply end and supplying a constant potential from the potential supply end, the operation can be stabilized.

  Further, by controlling the potential of the potential supply end by the potential control mechanism and controlling the potential of the potential supply line, the potential of the charge accumulation unit can be held at a low potential and the operation of the charge amplification unit can be stopped. It becomes possible. This eliminates the need for a selection transistor that is required for selecting a pixel portion in the conventional amplification type solid-state imaging device, and can allocate the area to the photoelectric conversion element. It is possible to achieve higher sensitivity.

  In addition, a switch circuit for switching and connecting a constant potential and a constant current load circuit to the signal line is further provided, and the operation of the charge amplifying unit is controlled by short-circuiting the input unit and the output unit of the charge amplifying unit. It can be stopped. This eliminates the need for a selection transistor that is required for selecting a pixel portion in the conventional amplification type solid-state imaging device, and can allocate the area to the photoelectric conversion element. It is possible to achieve higher sensitivity.

  Furthermore, the power supply potential may change due to external noise or a capacitance portion. In this case as well, since the coupling capacitance between the signal charge storage unit 6 and the potential supply line 8 can be reduced, the power supply noise is reduced. It becomes possible to do. That is, it is possible to improve noise resistance when the power supply potential changes.

  As described above, according to the amplification type solid-state imaging device of the present invention, the signal charge storage unit is provided with a plurality of pixels in order to change the potential of the potential supply line by feeding back the potential change of the signal line to the potential supply line of the charge amplification unit. The pixel size can be reduced by using the common part, the charge-voltage conversion rate can be increased, the noise resistance when the power supply potential changes can be improved, and a high-quality image can be obtained. Thus, the amplification type solid-state imaging device of the present invention is extremely useful for forming a miniaturized and high-performance image sensor.

Hereinafter, a case where the first to fourth embodiments of the amplification type solid-state imaging device of the present invention are applied to a two-dimensional amplification type solid-state imaging device will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a circuit diagram illustrating a configuration example of a main part of an amplification type solid-state imaging device according to Embodiment 1 of the present invention.

  In FIG. 1, an amplification type solid-state imaging device 51 of Embodiment 1 includes a photoelectric conversion transfer unit 10 provided in each of all pixel units (or pixels), and the (m, 1) -th row i in the vertical direction. The charge amplifying unit 11 provided in common for the pixel in the column and the (m, 2) th row and the i-th column, and all the charge amplifying units 11 present in the i-th column are provided in common. The signal output from the charge amplifier 11 is fed back to the charge amplifier 11 by feeding back the potential of the signal line 7 to the constant current load circuit 12 including the constant current load transistor 9 and the potential supply line 8 of the charge amplifier 11. And a feedback circuit 13 to be operated.

  The upper photoelectric conversion transfer unit 10 and the charge amplification unit 11 constitute an upper pixel, and the lower photoelectric conversion transfer unit 10 and the charge amplification unit 11 constitute a lower pixel. In the m-th row and the i-th column, two pixels are provided with the charge amplifying unit 11 in common. As described above, the amplification type solid-state imaging device 51 is commonly provided with the charge amplification unit 11 that can sequentially amplify the signal charges from the plurality (upper and lower two in FIG. 1) of the photoelectric conversion transfer units 10. In FIG. 1, among the pixels arranged in a matrix in a plurality of rows and columns, each pixel in the (m, 1) th row and the i-th column and the (m, 2) -th row and the i-th column. Only shows. However, m and i are natural numbers.

  The photoelectric conversion / transfer unit 10 includes a photodiode 1 as an example of a photoelectric conversion element as a photoelectric conversion unit and a transfer transistor 2 as charge transfer means. If the photodiode 1 is a buried photodiode and signal charge transfer from the photodiode 1 is completely performed, the noise can be extremely reduced and a high-quality image can be obtained. The transfer transistor 2 is an N-channel MOS transistor, and is controlled by a drive pulse φT supplied to the gate to transfer the signal charge accumulated in the photodiode 1. A signal charge storage unit 6 is connected in common to the output sides of these two transfer transistors 2.

  The charge amplifying unit 11 has an input terminal connected to the signal charge storage unit 6 commonly connected to the output side of the transfer transistor 2 in the photoelectric conversion transfer unit 10, and an output terminal connected to the signal line 7. The charge discharge and power supply line are connected to the potential supply line 8. The charge amplifying unit 11 includes an amplifying transistor 3 as an amplifying means for amplifying a signal charge, a reset transistor 4 as a resetting means for discharging charges, and a selection as a pixel selecting means for selecting a pixel. Transistor 5.

  The amplifying transistor 3 is composed of an N-channel MOS transistor, and a signal charge storage unit 6 is connected to a gate (control terminal) as an input end thereof, and a source (one drive terminal) as an output end (output unit) thereof. The signal line 7 is connected via the selection transistor 5, and the potential supply line 8 is connected to the drain (the other drive terminal). The amplifying transistor 3 and the constant current load transistor 9 connected between the signal line 7 and the ground potential GND constitute a drain-grounded source follower circuit.

  The reset transistor 4 is composed of an N-channel MOS transistor, has a signal charge storage unit 6 connected to the source, and a potential supply line 8 connected to the drain. The reset transistor 4 is controlled by a drive pulse φR supplied to the gate, The potential of the storage unit 6 is reset to the potential of the potential supply line 8.

  The selection transistor 5 is composed of an N-channel transistor, is connected between the source of the amplification transistor 3 and the signal line 7, and is selected and controlled by a drive pulse φS supplied to the gate. Is read out to the signal line 7.

  The feedback circuit 13 has a signal line 7 connected to the gate as its input terminal (input part), a potential supply line 8 of the charge amplifier 11 connected to the source and substrate as its output terminal (output part), and a drain. Has a P-channel MOS transistor 131 grounded, and a constant current load transistor 132 connected between the source of the MOS transistor 131 and the power supply potential Vdd. The MOS transistor 131 and the constant current load transistor 132 constitute a source follower circuit.

  The transfer transistor drive signal line 22 is connected to the gate of the transfer transistor 2 in a plurality of photoelectric conversion transfer units 10 (only one is shown in the horizontal direction in FIG. 1) arranged in the row direction (horizontal direction). Yes. The driving pulses φT (m, 1) and φT (m, 2) are respectively connected to the gates of the transfer transistors 2 in the two photoelectric conversion transfer units 10 in the m-th row and the i-th column via the transfer transistor drive signal lines 22 respectively. ) Are applied respectively.

  The reset transistor drive signal line 21 is connected to the gate of each reset transistor 4 in the plurality of charge amplifiers 11 arranged in the row direction (lateral direction). A drive pulse φR (m) is applied to the gate of each reset transistor 4 in the plurality of charge amplification units 11 in the m-th row via the reset transistor drive signal line 21.

  The selection transistor drive signal line 23 is connected to the gate of each selection transistor 5 in the plurality of charge amplification units 11 arranged in the row direction (lateral direction). A drive pulse φS (m) is applied to the gate of each select transistor 5 in the plurality of charge amplifying units 11 in the m-th row via the select transistor drive signal line 23.

  With the above configuration, the operation of the amplification type solid-state imaging device 51 of the first embodiment will be described below in detail with reference to FIG.

FIG. 2 shows signal waveforms of the drive pulses φS (m), φR (m), φT (m, 1), φT (m, 2) in the amplification type solid-state imaging device 51 of Embodiment 1, and the mth FIG. 7 is a timing chart showing the potential of the charge accumulating section (i, m) 6 in the row i column, the potential VD (i) of the potential supply line 8 in the i column, and the potential Vsig (i) of the signal line 7 in the i column. is there.
First, since the drive pulse φS (m) is at a low level in the initial state, the potential of the signal line 7 is at the ground level, and the potential of the potential supply line 8 at that time is equal to the output potential when the input of the feedback circuit 3 is 0V. Become.

  In the period T1, the drive pulse φR (m) applied to the gate of the reset transistor 4 in the charge amplification unit 11 in the m-th row is repeated from low level to high level and low level, and the potential of the charge storage unit 6 is supplied with potential. It becomes the same as the potential of the line 8.

  Since the drive pulse φS (m) applied to the gate of the selection transistor 5 in the charge amplification unit 11 in the period T2 becomes high level, the amplification transistor 3 and the constant current load transistor 9 constitute a drain-grounded source follower circuit. The output signal is output to the signal line 7 via the selection transistor 5. The potential supply line 8 also rises due to the input / output relationship in the feedback circuit.

  The potential supply line 8 is determined by the input / output relationship in the feedback circuit shown in FIG. 3, and becomes the output Vout when the input Vin = the potential of the charge storage unit 6 in the period T2 by the following relational expression (1).

Vout = Vin−Vgs (NchTr3, I = I1) + Vgs (PchTr131, I = I2−I1) (1)
In the above equation (1), Vgs (NchTr3, I = I1) represents a gate-source voltage when the N-channel MOS transistor 3 passes a constant current of I1, and Vgs (PchTr131, I = I2-I1). ) Represents a gate-source voltage when the P-channel MOS transistor 131 passes a constant current of (I2-I1). Of course, I2> I1.

At this time, it is necessary to operate the amplification MOS transistor 3 in the saturation region.
Vout> Vin−Vth (NchTr3) (2)
It is necessary to satisfy this relationship. Therefore,
Vgs (PchTr131, I = I2-I1)> Vgs (NchTr3, I = I1) −Vth (NchTr3) (3)
The P-channel transistor 131 may be designed so as to satisfy this relationship.

  The potential Vsig (i) of the signal line 7 is the reference potential of the pixel in the (m, 1) th row and the i-th column.

  Next, in the period T <b> 3, the signal charge photoelectrically converted by the photodiode 1 is read out to the signal charge storage unit 6. At this time, the drive pulse φT (m, 1) is at a high level and the transfer transistor 2 in the (m, 1) row is turned on, so that the photodiode in the (m, 1) row passes through the transfer transistor 2. The signal charge accumulated in 1 is read out to the signal charge accumulation unit 6.

  After the signal charge accumulated in the photodiode 1 is completely read out to the signal charge accumulation unit 6, in the next period T4, the drive pulse φT (m, 1) becomes low level, and the transfer transistor 2 Turns off. For this reason, the signal charge accumulating unit 6 holds a potential that has changed from the potential in the period T2 according to the amount of transfer of the signal charge, and the held signal level (potential) is the amplification transistor 3 and the constant current load transistor 9. And the output signal is read out to the signal line 7 via the selection transistor 5. The potential Vsig (i) of the signal line 7 obtained in the period T4 is a signal of the pixel in the (m, 1) th row and the i-th column.

At this time, in the feedback circuit shown in FIG.
ΔVout = ΔVin × G (4)
Obtained by. However, in the feedback circuit shown in FIG. 3, the gain of the source follower circuit constituted by the P-channel type transistor 131 and the constant current load transistor 132 is almost “1”, so that G is the amplification transistor 3 and the constant current load transistor. 9 is a gain of the source follower circuit constituted by 9, which is about 0.9. Therefore, in the period T4, the potential VD (i) of the potential supply line 8 also changes by the potential change × G of the signal line 7 due to the transfer of the signal charge, and the signal charge storage section 6 and the potential supply line 8 are coupled. The ring capacitance CFD-VDD is apparently reduced to (1−G) = 0.1 times, which leads to an improvement in the charge voltage conversion efficiency η. Furthermore, since G <1, the amplifying MOS transistor 3 maintains the saturation region, and there is no problem in the operation of the source follower circuit.

  Thereafter, in the period T5, the drive pulse φS (m) applied to the gate of the selection transistor 5 is set to a low level, and the drive pulse φR (m) applied to the gate of the reset transistor 4 is changed between a high level and a low level. As a result, the potential of the signal charge storage unit 6 is reset to the output potential of the feedback circuit 13, and both the potential supply line 8 and the signal charge storage unit 6 are returned to the initial state.

  With the above operation, the difference signal between the potential of the signal line 7 in the period T2 and the potential of the signal line 7 in the period T4 is processed by a subsequent CDS (correlated double sampling) circuit, a differential amplifier circuit, a clamp circuit, or the like. For example, an effective signal component is read for each pixel due to signal charges generated by light incident on the pixels in the (m, 1) row. Note that a CDS circuit, a differential amplifier circuit, a clamp circuit, and the like are well known to those skilled in the art, and thus description thereof is omitted here.

  After one horizontal period, the same driving operation as in the period T1 to T5 is performed, and at that time, the driving pulse φT (m, 2) is set to the high level instead of the driving pulse φT (m, 1). Similarly, the effective signal component can be obtained for each pixel by reading a signal based on signal charges generated by light incident on the pixels in the (m, 2) th row.

  The above describes the operation when the m-th row is the selected row. For the nth row (n is a natural number) that is a non-selected row, the drive pulse φS (n) is at a low level, so that the selection transistor 5 is turned off, and the signal line from the pixel of the nth row that is a non-selected row. No signal is read out in 7.

  As described above, according to the amplification type solid-state imaging device 51 of the first embodiment, the potential of the potential supply line 8 of the charge amplification unit 11 also changes in accordance with the change in potential of the signal line 7. The coupling capacity with the supply line 8 is apparently reduced. As a result, the parasitic capacitance of the signal charge accumulating unit 8 is reduced, and the charge voltage conversion efficiency η when the signal charge ΔQsig is converted into the voltage signal ΔVsig is increased to increase the sensitivity of the solid-state imaging device. Can be achieved. Particularly, as the number of photoelectric conversion / transfer units 10 connected to the common signal charge storage unit 6 increases as the size of the pixel decreases, the effect of reducing the coupling capacitance increases. Nevertheless, high sensitivity can be achieved. That is, since V = Q / C, the charge Q is constant, and the voltage sensitivity of the voltage V can be increased by reducing the capacitance C.

  In addition, by using the embedded photodiode 1 as the photoelectric conversion element of the pixel, it is possible to completely transfer the signal charge from the photodiode 1 and obtain a higher-quality image with lower noise. be able to.

  Further, since the feedback circuit 13 is a positive feedback with a gain of 1 or less, the feedback can be controlled more stably when the potential of the signal line 7 is fed back to the potential supply line 8 of the charge amplifier 11.

Furthermore, the power supply potential may change due to external noise or a capacitance portion. In this case as well, since the capacity of the signal charge storage unit 6 and the potential supply line 8 can be reduced, the power supply potential can be reduced. Noise can be reduced.
(Embodiment 2)
In the first embodiment, the case where the feedback circuit 13 that feeds back the output potential from the charge amplifier 11 to the potential supply line 8 of the charge amplifier 11 has been described. However, in the second embodiment, the potential of the charge amplifier 11 is determined. A case will be described in which the feedback operation is performed on the supply line 8 only during the readout period, and the feedback operation is not performed outside the readout period.

  FIG. 4 is a circuit diagram showing a configuration example of a main part of an amplification type solid-state imaging device according to Embodiment 2 of the present invention. In FIG. 4, the same reference numerals are given to components having the same effects as the components in FIG. 1, and the description thereof is simplified.

  4, the amplification type solid-state imaging device 52 of the second embodiment includes the photoelectric conversion transfer unit 10 provided in each of the pixels, and the (m, 1) th row i-th column and ( m, 2) The charge amplifying unit 11 provided in common for the two pixels in the i-th column and the constant current load transistor provided in common for all the charge amplifying units 11 present in the i-th column The signal (output potential) output by the charge amplifying unit 11 is fed back to the charge amplifying unit 11 by feeding back the potential of the constant current load circuit 12 consisting of 9 and the signal line 7 to the potential supply line 8 of the charge amplifying unit 11. The output of the feedback circuit 13 and the potential supply terminal 140 (the output terminal of the potential supply unit. In FIG. 4, the power supply potential Vdd is output to the feedback circuit 13 and the potential supply line 8 of the charge amplifier 11. And cut Ete and a switch circuit 14 connected.

  The switch circuit 14 has two switching transistors 141 and 142 controlled by a common drive pulse φVd. The switching transistors 141 and 142 are P-channel MOS transistors, and the driving pulse φVd is directly supplied to the gate of one switching transistor 141, and the gate of the other switching transistor 142 is connected via an inverter 143. A reverse-phase drive pulse obtained by inverting the drive pulse φVd is supplied. One switching transistor 141 is connected between the potential supply terminal 140 set to a constant potential Vdd and the potential supply line 8 of the charge amplifying unit 11, and the other switching transistor 142 is connected to the output terminal Vout of the feedback circuit 13. And the potential supply line 8 of the charge amplifying unit 11.

  In order to switch and connect the output terminal Vout of the feedback circuit 13 and a constant potential (power supply potential Vdd; potential of the potential supply terminal 140) to the potential supply line 8, driving is performed via the switch circuit drive signal line 24. A pulse φVd is applied to the gate of the switching transistor 141 of the switch circuit 14, and an inversion driving pulse of the driving pulse φVd is applied to the gate of the switching transistor 142 of the switch circuit 14.

  With the above configuration, the operation of the amplifying solid-state imaging device 52 of Embodiment 2 will be described in detail below with reference to FIG.

  FIG. 5 shows signal waveforms of the drive pulses φS (m), φR (m), φT (m, 1), φT (m, 2), and φVd in the amplification type solid-state imaging device 52 of Embodiment 2. Timing indicating the potential of the charge storage unit (i, m) 6 in the m-th row and the i-th column, the potential VD (i) of the potential supply line 8 in the i-th column and the potential Vsig (i) of the signal line 7 in the i-th column. FIG.

  As shown in FIG. 5, first, in the period T1, the drive pulse φR (m) applied to the gate of the reset transistor 4 in the charge amplifying unit 11 in the m-th row changes from the low level to the high level. Is turned on. Further, since the drive pulse φVd input to the switch circuit 14 is at a low level, both the potential supply line 8 and the charge storage unit 6 are connected to the potential supply terminal 140, and the potential VD (i) of the potential supply line 8 is set. The potential of the charge storage unit 6 becomes the power supply potential Vdd of the potential supply terminal 140 through the reset transistor 4. On the other hand, since the driving pulse φS (m) applied to the gate of the selection transistor 5 in the charge amplifier 11 is at a high level, the amplifying transistor 3 and the constant current load transistor 9 constitute a drain-grounded source follower circuit. The output signal is output to the signal line 7 through the selection transistor 5. Thereafter, the drive pulse φR (m) applied to the gate of the reset transistor 4 is returned to the low level, but the reset level state of the charge storage unit 6 is maintained.

  Next, in the period T2, the drive pulse φVd input to the switch circuit 14 becomes high level, the output terminal Vout (output unit) of the feedback circuit 13 is connected to the potential supply line 8, and the potential of the potential supply line 8 is reached. VD (i) decreases. This potential is determined by the relationship between input and output in the feedback circuit shown in FIG. 3, and Vout when Vin = Vdd is obtained by the following relational expression (1).

Vout = Vin−Vgs (NchTr3, I = I1) + Vgs (PchTr131, I = I2−I1) (1)
In the above equation (1), Vgs (NchTr3, I = I1) represents a gate-source voltage when the N-channel MOS transistor 3 passes a constant current of I1, and Vgs (PchTr131, I = I2-I1). ) Represents a gate-source voltage when the P-channel MOS transistor 131 passes a constant current of (I2-I1). Of course, I2> I1. Further, since it is necessary to operate the amplification MOS transistor 3 in the saturation region,
Vout> Vin−Vth (NchTr3) (2)
It is necessary to satisfy this relationship. Therefore,
Vgs (PchTr131, I = I2-I1)> Vgs (NchTr3, I = I1) −Vth (NchTr3) (3)
The P-channel transistor 131 may be designed so as to satisfy this relationship.

  The potential Vsig (i) of the signal line 7 obtained in the period T2 is the reference potential of the pixel in the (m, 1) th row and the i-th column.

  Next, in the period T <b> 3, the signal charge photoelectrically converted by the photodiode 1 is read out to the signal charge storage unit 6. At this time, the drive pulse φT (m, 1) is at a high level and the transfer transistor 2 in the (m, 1) row is turned on, so that the photodiode in the (m, 1) row passes through the transfer transistor 2. The signal charge accumulated in 1 is read out to the signal charge accumulation unit 6.

  After the signal charge accumulated in the photodiode 1 is completely read out to the signal charge accumulation unit 6, the drive pulse φT (m, 1) becomes low level in the next period T4, and the transfer transistor 2 Turns off. For this reason, the signal charge accumulating unit 6 holds a potential that has changed from the potential in the period T2 according to the amount of transfer of the signal charge, and the held signal level (potential) is the amplification transistor 3 and the constant current load transistor 9. And is output to the signal line 7. The potential Vsig (i) of the signal line 7 obtained in the period T4 is a signal of the pixel in the (m, 1) th row and the i-th column.

At this time, in the feedback circuit shown in FIG.
ΔVout = ΔVin × G (4)
Obtained by. However, in the feedback circuit shown in FIG. 3, the gain of the source follower circuit constituted by the P-channel type transistor 131 and the constant current load transistor 132 is almost “1”, so that G is the amplification transistor 3 and the constant current load transistor. 9 is a gain of the source follower circuit constituted by 9, which is about 0.9. Therefore, in the period T4, the potential VD (i) of the potential supply line 8 also changes by the potential change × G of the signal line 7 due to the transfer of the signal charge, and the signal charge storage section 6 and the potential supply line 8 are coupled. The ring capacitance CFD-VDD is apparently reduced to (1−G) = 0.1 times, which leads to an improvement in charge-voltage conversion efficiency η. Furthermore, since G <1, the amplifying MOS transistor 3 is in the saturation region, and there is no problem in the operation of the source follower circuit.

  Subsequently, in the period T <b> 5, the drive pulse φVd is lowered to a low level, whereby the switch circuit 14 is switched, the potential supply line 8 is connected to the potential supply terminal 140, and the potential VD (i) is supplied from the potential supply terminal 140. It is fixed at a constant potential Vdd. By changing the drive pulse φR (m) applied to the gate of the reset transistor 4 between a high level and a low level, the potential of the signal charge storage unit 8 is reset to a constant potential (in this case, the power supply potential Vdd), Both the potential supply line 8 and the signal charge storage unit 6 are returned to the initial state through the reset transistor 4.

  With the above operation, the difference signal between the potential of the signal line 7 in the period T2 and the potential of the signal line 7 in the period T4 is processed by a subsequent CDS (correlated double sampling) circuit, a differential amplifier circuit, a clamp circuit, or the like. For example, the effective signal component due to the signal charge generated by the light incident on the pixels in the (m, 1) th row is read out.

  After one horizontal period, the same driving operation as in the above-described periods T1 to T5 is repeatedly performed, and at that time, the driving pulse φT (m, 2) is set to the high level instead of the driving pulse φT (m, 1). Similarly, a signal component can be obtained by reading a signal due to signal charges generated by light incident on the pixels in the (m, 2) -th row.

  The above describes the operation when the m-th row is the selected row. For the nth row (n is a natural number) that is a non-selected row, the drive pulse φS (n) is at a low level, so that the selection transistor 5 is turned off, and a signal is output from the pixel of the nth row that is a non-selected row. Not output.

  As described above, according to the amplification type solid-state imaging device 52 of the second embodiment, the potential of the potential supply line 8 of the charge amplifying unit 11 also changes in accordance with the potential change of the signal line 7. The coupling capacity with the supply line 8 is apparently reduced. As a result, the capacitance parasitic on the signal charge storage unit 6 is reduced, and the charge voltage conversion efficiency η when the signal charge ΔQsig is converted into the voltage signal ΔVsig is increased, thereby increasing the sensitivity of the solid-state imaging device. Can be achieved. Particularly, as the number of photoelectric conversion / transfer units 10 connected to the common signal charge storage unit 6 increases as the size of the pixel decreases, the effect of reducing the coupling capacitance increases. Nevertheless, it is possible to achieve high sensitivity.

  In this case, by providing a switch circuit 14 for switching and connecting the potential supply terminal 140 and the output terminal Vout of the feedback circuit 13 to the potential supply line 8 of the charge amplifier 11, the feedback mechanism can be provided except during the readout period. The operation can be stabilized by connecting the potential supply line 8 to the potential supply end 140 and supplying a constant potential from the potential supply end 140 without operating.

Furthermore, the power supply potential may change due to external noise or a capacitance portion. In this case as well, since the capacity of the signal charge storage unit 6 and the potential supply line 8 can be reduced, the power supply potential can be reduced. Noise can be reduced.
(Embodiment 3)
In the first embodiment, the case where the feedback circuit 13 that feeds back the output potential from the charge amplification unit 11 to the potential supply line 8 of the charge amplification unit 11 has been described. However, in the third embodiment, the case of the second embodiment is described. Similarly to the case where the feedback mechanism by the feedback circuit 13 is not operated for the potential supply line 8 of the charge amplifying unit 11 except for the readout period, by controlling the potential of the potential supply line 8 outside the readout period, A case where the selection transistor 5 is omitted from the charge amplifier 11 will be described.

  FIG. 6 is a circuit diagram illustrating a configuration example of a main part of an amplification type solid-state imaging device according to Embodiment 3 of the present invention. In FIG. 4, the same reference numerals are given to components having the same effects as the components in FIG. 1, and the description thereof is simplified.

  In FIG. 6, the amplification type solid-state imaging device 53 according to the third embodiment includes the photoelectric conversion / transfer unit 10 provided in each of the pixels, the (m, 1) th row, the i-th column, and the (th) m, 2) A charge amplifying unit 11A provided in common for the two pixels in the i-th column and a constant current load transistor provided in common for all the charge amplifying units 11A present in the i-th column The signal output to the signal line 7 by the charge amplifying unit 11A is fed back to the charge amplifying unit 11A by feeding back the potential of the constant current load circuit 12 composed of 9 and the signal line 7 to the potential supply line 8 of the charge amplifying unit 11A. And a switch circuit 14A for switching and connecting the output of the feedback circuit 13 and the potential supply terminal 140A to the potential supply line 8 of the charge amplifier 11A.

  The charge amplifier 11 </ b> A has an input terminal connected to the signal charge storage unit 6 commonly connected to the output side of the transfer transistor 2 in each photoelectric conversion transfer unit 10, and an output terminal connected to the signal line 7. The charge discharge and power supply lines are connected to the potential supply line 8. The charge amplifier 11A includes an amplifying transistor 3 for signal charge amplification and a reset transistor 4 for discharging charge. Here, a selection transistor 5 for selecting a pixel is provided. Not.

  The switch circuit 14A includes a switching transistor 144 in parallel with the switching transistor 141 in addition to the two switching transistors 141 and 142 controlled by a common drive pulse φVd.

  The switching transistor 144 is composed of an N-channel MOS transistor, and a reverse phase driving pulse obtained by inverting the driving pulse φVd is supplied to the gate of the switching transistor 144 via the inverter 143. The switching transistors 144 and 141 constitute a CMOS switch circuit, and are connected between the potential supply terminal 140A and the potential supply line 8 of the charge amplifying unit 11A. Furthermore, the potential supply terminal 140A has a potential control mechanism (not shown), and is not a constant potential (power supply potential Vdd) as in the first and second embodiments but a variable DC potential Vod.

  With the above configuration, the operation of the amplifying solid-state imaging device 53 of Embodiment 3 will be described in detail below with reference to FIG.

  FIG. 7 shows the variable DC potential Vod at the potential supply end and the driving pulses φR (m), φT (m, 1), φT (m, 2) and φVd in the amplification type solid-state imaging device 53 of the third embodiment. The signal waveform, the potential of the charge storage unit (i, m) 6 in the m-th row and the i-th column, the potential VD (i) of the potential supply line 8 in the i-th column and the potential Vsig (i) of the signal line 7 in the i-th column. FIG. FIG. 7 shows a case where the m-th row is a selected row.

  As shown in FIG. 7, first, in the period T1, the drive pulse φR (m) applied to the gate of the reset transistor 4 in the charge amplification unit 11A in the m-th row changes from the low level to the high level, so that the reset transistor 4 Is turned on. Further, since the drive pulse φVd input to the switch circuit 14A is at a low level, the potential supply line 8 and the charge storage unit 6 are connected to the potential supply terminal 140A. At this time, since the potential Vod of the potential supply terminal 140A is the power supply potential Vdd, the potential VD (i) of the potential supply line 8 and the potential of the charge storage unit 6 are set to the power supply potential Vdd through the reset transistor 4. The amplifying transistor 3 and the constant current load transistor 9 form a drain-grounded source follower circuit, and a signal from the amplifying transistor 3 is output to the signal line 7. Thereafter, the drive pulse φR (m) applied to the gate of the reset transistor 4 is returned to the low level, but the above state is maintained.

  Next, in the period T2, the drive pulse φVd input to the switch circuit 14A becomes high level, the output terminal Vout from the feedback circuit 13 is connected to the potential supply line 8, and the potential VD (i of the potential supply line 8 is set. ) Decreases in the same manner as in the second embodiment. The potential Vsig (i) of the signal line 7 obtained in this period T2 is the reference potential of the pixel in the (m, 1) th row and the i-th column.

  Further, in the period T3, as in the case of the first embodiment, the drive pulse φT (m, 1) is at a high level and the transfer transistor 2 in the (m, 1) row is turned on. 2, the signal charge accumulated in the photodiodes 1 in the (m, 1) -th row is read out to the signal charge accumulation unit 6.

  After the signal charge accumulated in the photodiode 1 is completely read out to the signal charge accumulation unit 6, in the next period T4, the drive pulse φT (m, 1) becomes low level, and the transfer transistor 2 Turns off. For this reason, the signal charge accumulating unit 6 holds a potential that has changed from the potential in the period T2 in accordance with the amount of transfer of the signal charge, and the held signal level (potential) is the amplification transistor 3 and the constant current load. The signal is amplified by a source follower circuit including the transistor 9 and output from the amplifying transistor 3 to the signal line 7. The potential Vsig (i) of the signal line 7 obtained in this period T4 is a signal of the pixel in the (m, 1) th row and the i-th column.

  In this period T4, in the feedback circuit 13 shown in FIG. 6, as in the first embodiment, the potential of the potential supply line 8 also changes by the amount of change in potential of the signal line 7 × G due to the transfer of signal charges. The coupling capacitance CFD-VDD between the charge storage unit 6 and the potential supply line 8 is apparently reduced to (1−G) = 0.1 times, leading to an improvement in the charge voltage conversion efficiency η. .

  Thereafter, in the period T5, the drive pulse φVd is lowered to a low level, so that the switch circuit 14A operates and the potential VD (i) of the potential supply line 8 is connected to the potential supply terminal 140A. By changing the drive pulse φR (m) applied to the gate of the reset transistor 4 between the high level and the low level while lowering the potential Vod of the potential supply terminal 140A to the low level, the potential of the signal charge storage unit 6 is constant. The potential is reset to the potential (in this case, the ground potential), and both the potential supply line 8 and the signal charge storage unit 6 are returned to the initial state through the reset transistor 4.

  Through the above operation, a difference signal between the potential of the signal line 7 in the period T2 and the potential of the signal line 7 in the period T4 is processed by a subsequent CDS (correlated double sampling) circuit, a differential amplifier circuit, a clamp circuit, or the like. Then, the effective signal component due to the signal charge generated by the light incident on the pixels in the (m, 1) row is read out.

  After this one horizontal period, the same driving operation as in the above-described periods T1 to T5 is repeated, and at that time, the driving pulse φT (m, 2) is set to the high level instead of the driving pulse φT (m, 1). Similarly, a signal component can be obtained by reading a signal due to signal charges generated by light incident on the pixels in the (m, 2) -th row.

  The above describes the operation when the m-th row is the selected row. Next, the operation of the nth row (n is a natural number) which is a non-selected row will be described in detail with reference to FIG.

  FIG. 8 shows the potential Vod of the potential supply terminal 140A in the amplification type solid-state imaging device 53 of the third embodiment and the driving pulses φR (n), φT (n, 1), φT (n, 2) of the n-th row. And φVd, the potential of the charge storage section (i, n) 6 in the n-th row and the i-th column, the potential VD (i) of the potential supply line 8 in the i-th column and the signal line 7 in the i-th column. It is a timing diagram which shows electric potential Vsig (i).

  As shown in FIG. 8, in the n-th row that is a non-selected row, the drive pulses φR (n), φT (n, 1), and φT (n, 2) are all at a low level, so that the signal charge storage unit 6 Maintains the initial state. At this time, since the signal charge storage unit 6 is at the ground level, the amplifying transistor 3 is always in an off state, and no signal is output from the pixel in the n-th row which is a non-selected row. Therefore, in the amplification type solid-state imaging device 53 of the third embodiment, the selection transistor 5 for selecting a row as in the first and second embodiments is not necessary.

  As described above, according to the amplification type solid-state imaging device 53 of the third embodiment, the potential of the potential supply line 8 of the charge amplifying unit 11 </ b> A changes according to the potential change of the signal line 7. And the potential supply line 8 are apparently reduced. As a result, the parasitic capacitance of the signal charge accumulating unit 6 is reduced, and the charge voltage conversion efficiency η when the signal charge ΔQsig is converted into the voltage signal ΔVsig can be increased, thereby increasing the sensitivity of the solid-state imaging device. Can be achieved. Particularly, as the number of photoelectric conversion / transfer units 10 connected to the common signal charge storage unit 6 increases as the size of the pixel decreases, the effect of reducing the coupling capacitance increases. Nevertheless, high sensitivity can be realized.

  Further, by using the embedded photodiode 1 as the photoelectric conversion element of the pixel, the signal charge from the photodiode 1 can be completely transferred, and the image quality is further reduced and the noise is reduced. Can be obtained.

Further, a switch circuit 14A for switching and connecting the potential supply terminal 140A and the output terminal Vout of the feedback circuit 13 to the potential supply line 8 of the charge amplifier 11A is further provided, and the potential supply terminal 140A is connected by the potential control mechanism. By controlling the potential and controlling the potential of the potential supply line 8, the potential of the charge accumulating unit 6 can be held at the ground potential, and the operation of the charge amplifying unit 11A can be stopped. This eliminates the need for the selection transistor 5 that is necessary for selecting a pixel in the conventional amplification type solid-state imaging device, and the area can be allocated to the photodiode 1. A high sensitivity of 53 can be achieved.
(Embodiment 4)
In the first embodiment, the case where the feedback circuit 13 that feeds back the output potential from the charge amplifying unit 11 to the potential supply line 8 of the charge amplifying unit 11 is described. However, in the fourth embodiment, the case of the third embodiment is described. Similarly to the case where the feedback mechanism by the feedback circuit 13 is not operated for the potential supply line 8 of the charge amplifying unit 11 except for the readout period, by controlling the potential of the potential supply line 8 outside the readout period, A case where the selection transistor 5 is omitted from the charge amplifier 11 will be described.

  FIG. 9 is a circuit diagram showing a configuration example of a main part of an amplification type solid-state imaging device 54 according to Embodiment 4 of the present invention. In FIG. 9, the same reference numerals are given to the constituent elements having the same operational effects as the constituent elements in FIG. 1, and the description thereof is simplified.

  In FIG. 9, the amplification type solid-state imaging device 54 of the fourth embodiment includes the photoelectric conversion transfer unit 10 provided in each of the pixels, and the (m, 1) th row i-th column and the (th) m, 2) The charge amplifying unit 11B provided in common for the two pixels in the row and i-th column, and the constant current load transistor provided in common for all the charge amplifying units 11B present in the i-th column 9 and a feedback circuit 13 for feeding back the signal output by the charge amplifier 11B to the charge amplifier 11B by feeding back the potential of the signal line 7 to the potential supply line 8 of the charge amplifier 11B. And a switch circuit 15 for switching and connecting a constant potential (Vdd in FIG. 9) and the constant current load circuit 9 to the signal line 7. Here, as in the second embodiment, the switch circuit 14 is provided to switch and connect the output terminal Vout of the feedback circuit 13 and the potential supply terminal 140B to the potential supply line 8 of the charge amplifier 11B. Not.

  The charge amplifier 11B has an input terminal connected to the signal charge storage unit 6 commonly connected to the output side of the transfer transistor 2 in the photoelectric conversion transfer unit 10, and an output terminal directly connected to the signal line 7. The power supply line is connected to the potential supply line 8. The charge amplifying unit 11B includes an amplifying transistor 3 for signal charge amplification and a reset transistor 4 for discharging electric charge, and for selecting a pixel as in the case of the third embodiment. The transistor 5 is not provided. The reset transistor 4 has a source connected to the signal charge storage unit 6, a drain connected to the signal line 7, and is connected to the potential supply line 8 via the amplification transistor 3.

  The switch circuit 15 includes two switching transistors 151 and 152 that are controlled by a common drive pulse φVd. The switching transistor 151 is composed of an N-channel MOS transistor, and the gate thereof is supplied with a drive pulse φVd from the switch circuit drive signal line 24 and is connected between the signal line 7 and the constant current load circuit 12. The switching transistor 152 is composed of a P-channel MOS transistor, and the gate thereof is supplied with a drive pulse φVd from the switch circuit drive signal line 24 and is connected between the signal line 7 and a constant potential Vdd.

  With the above configuration, the operation of the amplification type solid-state imaging device 54 of the fourth embodiment will be described in detail below with reference to FIG.

  FIG. 10 shows signal waveforms of the drive pulses φR (m), φT (m, 1), φT (m, 2), and φVd in the amplification type solid-state imaging device 54 of Embodiment 4, and the m-th row i. FIG. 10 is a timing chart showing the potential of the charge storage section (i, m) 6 in the column, the potential VD (i) of the potential supply line 8 in the i-th column, and the potential Vsig (i) of the signal line 7 in the i-th column. FIG. 10 shows a case where the m-th row is a selected row.

  As shown in FIG. 10, first, in the period T1, since the drive pulse φVd inputted to the switch circuit 15 is at a low level, the power supply potential Vdd is connected to the signal line 7, and the potential Vsig (i) of the signal line 7 is connected. Becomes the power supply potential Vdd. The drive pulse φR (m) applied to the gate of the reset transistor 4 changes from the high level to the low level, and the reset transistor 4 is turned off, but the charge storage unit 6 is held at the power supply potential Vdd. Further, since the potential of the input terminal of the feedback circuit 13 is Vdd, the transistor 131 is turned off, and the potential VD (i) of the potential supply line 8 is also at the Vdd level.

  Next, in the period T2, the drive pulse φVd input to the switch circuit 15 becomes high level, the signal line 7 is connected to the common constant current load transistor 9, and the amplification transistor 3, the constant current load transistor 9, As a result, a grounded drain type source follower circuit is configured and output from the amplifying transistor 3 to the signal line 7. Further, since the output terminal Vout of the feedback circuit 13 is connected to the potential supply line 8, the potential VD (i) of the potential supply line 8 is lowered as in the case of the second embodiment. The potential Vsig (i) of the signal line 7 obtained in this period T2 is the reference potential of the pixel in the (m, 1) th row and the i-th column.

  Further, in the period T3, as in the case of the second embodiment, the drive pulse φT (m, 1) is at a high level, and the transfer transistor 2 in the (m, 1) row is turned on. 2, the signal charge accumulated in the photodiodes 1 in the (m, 1) -th row is read out to the signal charge accumulation unit 6.

  After the signal charge accumulated in the photodiode 1 is completely read out to the signal charge accumulation unit 6, in the next period T4, the drive pulse φT (m, 1) becomes low level, and the transfer transistor 2 Turns off. For this reason, the signal charge accumulating unit 6 holds a potential that changes in accordance with the amount of signal charge transferred from the potential in the period T2, and the held signal level (potential) is the amplification transistor 3 and the constant current load transistor. 9, the signal from the amplifying transistor 3 is output to the signal line 7. The potential Vsig (i) of the signal line 7 obtained in this period T4 is a signal of the pixel in the (m, 1) th row and the i-th column.

  In this period T4, the feedback circuit 13 shown in FIG. 9 changes the potential of the potential supply line 8 by the amount of change in the potential of the signal line 7 × G due to the transfer of the signal charge, similarly to the case of the second embodiment. The coupling capacitance CFD-VDD between the charge storage unit 6 and the potential supply line 8 is apparently reduced to (1−G) = 0.1 times, leading to an improvement in the charge voltage conversion efficiency η.

  After that, in the period T5, the drive pulse φVd is lowered to a low level, so that the power supply potential Vdd is connected to the signal line 7. Further, when the drive pulse φR (m) applied to the gate of the reset transistor 4 changes from the low level to the high level, the reset transistor 4 is turned on and the signal charge storage unit 6 is reset by the power supply potential Vdd. To return to the initial state.

  Through the above operation, a difference signal between the potential of the signal line 7 in the period T2 and the potential of the signal line 7 in the period T4 is processed by a subsequent CDS (correlated double sampling) circuit, a differential amplifier circuit, a clamp circuit, or the like. Then, the effective signal component due to the signal charge generated by the light incident on the pixels in the (m, 1) row is read out.

  After one horizontal period, the same driving operation as in the periods T1 to T5 is repeated, and at that time, the driving pulse φT (m, 2) is set to the high level instead of the driving pulse φT (m, 1). Similarly, a signal component can be obtained by reading a signal due to signal charges generated by light incident on pixels in the (m, 2) -th row.

  The above describes the operation when the m-th row is the selected row. Next, the operation of the n-th row (n is a natural number) that is a non-selected row will be described in detail with reference to FIG.

  FIG. 11 shows signal waveforms of the drive pulses φR (n), φT (n, 1), φT (n, 2), and φVd in the n-th row in the amplification type solid-state imaging device 54 of Embodiment 4, FIG. 6 is a timing chart showing the potential of the charge storage unit (i, n) in the n-th row and the i-th column, the potential VD (i) of the potential supply line 8 in the i-th column and the potential Vsig (i) of the signal line 7 in the i-th column. is there.

  As shown in FIG. 11, in the n-th row which is a non-selected row, the drive pulse φR (n) is always at a high level, and φT (n, 1) and φT (n, 2) are at a low level. The line 7 and the signal charge storage unit 6 are connected. At this time, since the potential between the gate and the source of the amplifying transistor 3 is the same, the amplifying transistor 3 is always in an off state, and no signal is output from the pixel in the n-th row which is a non-selected row. . Therefore, in the amplification type solid-state imaging device 54 of the fourth embodiment, the selection transistor 5 for selecting a row as in the first and second embodiments is not necessary.

  As described above, according to the amplification type solid-state imaging device 54 of the fourth embodiment, the potential of the potential supply line 8 of the charge amplifying unit 11B also changes in accordance with the potential change of the signal line 7. The coupling capacity with the supply line 8 is apparently reduced. As a result, the parasitic capacitance of the signal charge accumulating unit 6 is reduced, and the charge voltage conversion efficiency η when the signal charge ΔQsig is converted into the voltage signal ΔVsig is increased to increase the sensitivity of the solid-state imaging device. Can be achieved. Particularly, as the number of photoelectric conversion / transfer units 10 connected to the common signal charge storage unit 6 increases as the size of the pixel decreases, the effect of reducing the coupling capacitance increases. Nevertheless, high sensitivity can be realized.

  Further, by using the embedded photodiode 1 as the photoelectric conversion element of the pixel, the signal charge from the photodiode 1 can be completely transferred, and the image quality is further reduced and the noise is reduced. Can be obtained.

  Further, a switch circuit 15 for switching and connecting the constant potential (power supply potential Vdd) and the constant current load circuit 12 to the signal line 7 is further provided to short-circuit the input unit and the output unit of the charge amplification unit 11B. As a result, the operation of the charge amplifier 11B can be stopped. This eliminates the need for the selection transistor 5 that is necessary for selecting a pixel in the conventional amplification type solid-state imaging device, and the area can be allocated to the photodiode 1. A sensitivity of 54 can be achieved.

  Furthermore, the power supply potential may change due to external noise or a capacitance portion. In this case as well, since the coupling capacitance between the signal charge storage unit 6 and the potential supply line 8 can be reduced, the power supply noise is reduced. can do.

  Therefore, according to the first to fourth embodiments, signal charges are transferred from the plurality of photodiodes 1 to the common signal charge storage unit 6 through the transfer transistor 2. The output of the source follower type charge amplifying unit 11 (or 11A or 11B) having the signal charge accumulating unit 6 as an input unit is connected to a signal line 7. The feedback circuit 13 has an input connected to the signal line 7 and an output connected to the potential supply line 8 of the source follower type charge amplifier 11 (or 11A or 11B). The potential is fed back. As a result, the potential change of the signal line 7 is fed back to the potential supply line 8 of the charge amplifying unit 11 (or 11A or 11B) and the potential of the potential supply line 8 also changes. The pixel size can be reduced by common use, and the charge-voltage conversion rate can be increased to obtain a high-quality image.

  In the first to fourth embodiments, the charge amplification unit 11 (or 11A or 11B) and the charge amplification unit 6 are provided in common in two pixels of (m, 1) and (m, 2) rows. The present invention is also applicable to a configuration in which 11 (or 11A or 11B) and the charge amplifying unit 6 are provided in common in pixels of three or more rows (for example, 4 pixels, 6 pixels, or 8 pixels).

  Further, although not particularly described in the first to fourth embodiments, the charge amplifying unit 11 is provided in common so that the signal charges from the two photoelectric conversion units (photodiodes 1) can be sequentially amplified. In the type solid-state imaging device, the signal charge storage unit 6 is configured by a plurality of pixel units by including a feedback circuit 13 that feeds back the output potential from the charge amplification unit 11 to the potential supply line 8 of the charge amplification unit 11. It is possible to achieve the object of the present invention in which the pixel size can be reduced by common use and the charge voltage conversion rate can be increased to obtain a high-quality image. Similarly, a photoelectric conversion transfer unit having a photoelectric conversion unit (photodiode 1) and charge transfer means (transfer transistor 2) for transferring a signal charge from the photoelectric conversion unit for each pixel unit. 10, a charge amplifying unit 11 which is provided in common for each of the plurality of pixel units and amplifies each signal charge from the photoelectric conversion transfer unit 10 and can be read out to the signal line 7; A feedback circuit 13 that feeds back to the potential supply line 8 of the amplifying unit 11 may be provided. Also in this case, the object of the present invention can be achieved in which the pixel size can be reduced and the charge-voltage conversion rate can be increased to obtain a high-quality image. That is, the feedback circuit 13 changes the potential of the potential supply line 8 of the charge amplification unit 11 in accordance with the change in the output potential of the charge amplification unit 11, so that the coupling between the signal charge storage unit 6 and the potential supply line 8 is performed. The capacity can be apparently reduced, and the sensitivity of the solid-state imaging device can be increased by increasing the charge-voltage conversion efficiency.

  In the first to fourth embodiments, the feedback circuit 13 has the signal line 7 connected to the gate as the input unit, the potential supply line 8 of the charge amplification unit 11 connected to the source as the output unit, and the drain grounded. In the above description, the MOS transistor 131 and the constant current load transistor 132 connected between the source of the MOS transistor 131 and the power supply potential Vdd have been described. It is only necessary to have a transistor circuit in which the output potential of the unit 11 is input to the input unit, and the output potential corresponding to the output potential of the charge amplifying unit 11 is output from the output unit to the potential supply line 8.

  Further, in the third embodiment, in FIG. 6, the potential of the signal charge storage unit 6 is held at the ground potential by controlling the potential of the potential supply line 8 from the power supply potential Vdd to the ground potential by the variable DC potential Vod. Thus, the output operation of the charge amplifier 11A can be stopped. However, the present invention is not limited to this ground potential, and may be a low potential other than the ground potential as long as the charge amplifier 11A does not perform an output operation. That is, the selection operation of the charge amplifier 11A can be performed even at a low potential (for example, 0.5 V or the like) in a range where the amplification transistor 3 of the charge amplifier 11A does not operate. Of course, the ground potential can be easily obtained. Even at this low potential, a voltage of 0.3 V to 0.5 V, for example, can be easily obtained from the surrounding voltage generation circuit.

  Furthermore, although not specifically described in the first to fourth embodiments, a digital video camera, a digital still camera, or the like using any one of the solid-state imaging devices 51 to 54 of the first to fourth embodiments as an imaging unit. Electronic information devices with image input devices such as cameras, image input cameras, scanners, facsimiles, camera-equipped mobile phone devices, surveillance cameras, door phone cameras, in-vehicle cameras, television phone cameras, mobile phone cameras, etc. The electronic information device will be described. The electronic information device of the present invention performs high-quality image data obtained by using any of the solid-state imaging devices 51 to 54 of Embodiments 1 to 4 of the present invention as an imaging unit, and performs predetermined signal processing for recording. A memory unit such as a recording medium for recording data, a display means such as a liquid crystal display device that displays the image data on a display screen such as a liquid crystal display screen after performing predetermined signal processing for display, and the image data for communication At least one of a communication unit such as a transmission / reception device that performs communication processing after predetermined signal processing, and an image output unit that prints (prints) and outputs (prints out) the image data. .

  As mentioned above, although this invention has been illustrated using preferable Embodiment 1-4 of this invention, this invention should not be limited and limited to this Embodiment 1-4. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments 1 to 4 of the present invention based on the description of the present invention and the common general technical knowledge. Patents, patent applications, and references cited herein should be incorporated by reference in their entirety as if the contents themselves were specifically described herein. Understood.

  The present invention relates to an amplification type solid-state imaging device such as an APS type image sensor provided with a charge amplification unit for amplifying a signal charge from a photoelectric conversion unit, and the amplification type solid-state imaging device as an image input device for an imaging unit. For example, in the field of digital information cameras such as digital video cameras and digital still cameras, and electronic information devices such as image input cameras, scanners, facsimiles, and camera-equipped mobile phone devices, the potential supply line of the charge amplification unit In order to change the potential of the potential supply line by feedback, the signal charge storage unit is shared by a plurality of pixel units to reduce the pixel size, increase the charge-voltage conversion rate, and the power supply potential changes Noise resistance can be improved, and high-quality images can be obtained. Thus, the amplification type solid-state imaging device of the present invention is extremely useful for forming a miniaturized and high-performance image sensor.

It is a circuit diagram which shows the principal part structural example of the amplification type solid-state imaging device which concerns on Embodiment 1 of this invention. Signal waveforms of the drive pulses φS (m), φR (m), φT (m, 1), φT (m, 2) and the charge accumulation in the m-th row and the i-th column in the amplification type solid-state imaging device of FIG. FIG. 10 is a timing chart showing a potential of a part (i, m), a potential VD (i) of an i-th column potential supply line, and a potential Vsig (i) of a signal line of an i-th column. It is a circuit diagram which shows typically the feedback circuit part in the amplification type solid-state imaging device of FIG. It is a circuit diagram which shows the principal part structural example of the amplification type solid-state imaging device which concerns on Embodiment 2 of this invention. Each drive pulse φS (m), φR (m), φT (m, 1), φT (m, 2) and φVd in the amplification type solid-state imaging device of FIG. FIG. 10 is a timing chart showing a potential of a charge storage unit (i, m), a potential VD (i) of an i-th column potential supply line, and a potential Vsig (i) of a signal line of an i-th column. It is a circuit diagram which shows the principal part structural example of the amplification type solid-state imaging device which concerns on Embodiment 3 of this invention. In the amplification type solid-state imaging device of FIG. 6, in the case where the m-th row is a selected row, the potential Vod at the potential supply end and the drive pulses φR (m), φT (m, 1), φT (m, 2) And φVd, the potential of the charge storage section (i, m) in the m-th row and the i-th column, the potential VD (i) of the potential supply line in the i-th column and the potential Vsig ( It is a timing diagram which shows i). In the amplification type solid-state imaging device of FIG. 6, the potential Vod at the potential supply terminal and the driving pulses φR (n), φT (n, 1), φT (n, 2) ) And φVd, the potential of the charge storage section (i, n) in the nth row and the i th column, the potential VD (i) of the potential supply line in the i th column and the potential Vsig of the signal line in the i th column. It is a timing diagram which shows (i). It is a circuit diagram which shows the principal part structure of the amplification type solid-state imaging device which concerns on Embodiment 4 of this invention. In the amplification type solid-state imaging device of FIG. 9, for the case where the m-th row is a selected row, the signal waveforms of the drive pulses φR (m), φT (m, 1), φT (m, 2), and φVd, FIG. 11 is a timing chart showing the potential of the charge storage section (i, m) in the m-th row and the i-th column, the potential VD (i) of the potential supply line in the i-th column and the potential Vsig (i) of the signal line in the i-th column. . In the amplification type solid-state imaging device of FIG. 9, the signal waveforms of the drive pulses φR (n), φT (n, 1), φT (n, 2), and φVd for the pixels in the n-th row that is not selected. , A timing chart showing the potential of the charge accumulating portion (i, n) in the nth row and the i-th column, the potential VD (i) of the potential supply line in the i-th column and the potential Vsig (i) of the signal line in the i-th column. is there. It is a circuit diagram which shows the principal part structural example of the conventional amplification type solid-state imaging device currently disclosed by patent document 1. FIG. Each of the drive pulses φS (m), φR (m), φT (m, 1) and φT (m, 2) of the conventional amplification type solid-state imaging device of FIG. It is a timing diagram which shows each electric potential of a signal line, respectively.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photodiode 2 Transfer transistor 3 Amplification transistor 4 Reset transistor 5 Selection transistor 6 Signal charge storage part 7 Signal line 8 Potential supply line 9 Constant current load transistor 10 Photoelectric conversion transfer part 11, 11A, 11B Charge amplification part 12 Constant Current load circuit 13 Feedback circuit 14, 14A Potential supply line switch circuit 15 Signal line switch circuit 21 Reset transistor drive signal line 22 Transfer transistor drive signal line 23 Select transistor drive signal line 24 Switch circuit drive signal line 51-54 Amplification type Solid-state imaging device

Claims (21)

  In an amplification type solid-state imaging device in which a charge amplification unit is provided in common so that each signal charge from a plurality of photoelectric conversion units can be sequentially amplified, an output potential from the charge amplification unit is supplied to a potential supply line of the charge amplification unit An amplifying solid-state imaging device having a feedback circuit that feeds back. For each pixel unit, a photoelectric conversion unit having a photoelectric conversion unit and a charge transfer unit for transferring a signal charge from the photoelectric conversion unit,
A charge amplifying unit which is provided in common for each of the plurality of pixel units, and amplifies each signal charge from the photoelectric conversion transfer unit and can read out the signal line;
An amplification type solid-state imaging device comprising: a feedback circuit that feeds back the potential of the signal line to the potential supply line of the charge amplification unit.   The amplification type solid-state imaging device according to claim 1, wherein the photoelectric conversion unit is configured by an embedded photodiode.   The charge amplification unit has an input unit connected to a signal charge storage unit provided in common on the output side of the signal charge from the photoelectric conversion unit and an output unit connected to a signal line. 3. The amplification type solid-state imaging device according to claim 1, wherein a potential is supplied, amplified according to the amount of signal charge accumulated in the signal charge accumulation unit, and the output potential is read out to the signal line.   5. The charge amplification unit according to claim 4, further comprising: an amplification transistor in which the signal charge storage unit is connected to a gate as the input unit, and the signal line is connected to a source as the output unit. Amplification type solid-state imaging device.   6. The amplification type solid-state imaging device according to claim 5, wherein a source follower circuit is configured by the amplification transistor and a constant current load transistor connected between the signal line and a ground potential.   The charge amplification unit further includes a selection transistor connected between a source of the amplification transistor and the signal line, and a reset transistor having a source connected to the signal charge storage unit, the amplification transistor The amplification type solid-state imaging device according to claim 5 or 6, wherein each drain of the transistor and the reset transistor is connected to the potential supply line.   The feedback circuit includes a transistor circuit in which an output potential of the charge amplification unit is input to an input unit, and an output potential corresponding to the output potential of the charge amplification unit is output from the output unit to the potential supply line. Or the amplification type solid-state imaging device according to 2;   The transistor circuit includes a MOS transistor in which the signal line is connected to a gate as the input unit, a potential supply line of the charge amplification unit is connected to a source as the output unit, and a drain is grounded, and the MOS transistor The amplification type solid-state imaging device according to claim 8, further comprising a constant current load transistor connected between the source of the power source and the power supply potential.   The amplification type solid-state imaging device according to claim 1, further comprising a switch circuit that switches and connects the potential supply unit and the output unit of the feedback circuit to the potential supply line of the charge amplification unit.   The amplification type solid-state imaging device according to claim 10, wherein a power supply potential is supplied from the potential supply unit.   The amplification type solid-state imaging device according to claim 10, wherein the switch circuit selects an output unit side of the feedback circuit during a signal charge readout period and selects the potential supply unit side during a period other than the signal charge readout period.   The switch circuit includes two switching transistors each having a reverse-phase pulse signal supplied to each other's gate, and one of the switching transistors is between the potential supply line of the potential supply unit and the charge amplification unit. 13. The amplification type solid-state imaging device according to claim 10, wherein the other switching transistor is connected between an output unit of the feedback circuit and a potential supply line of the charge amplification unit.   The amplification type solid-state imaging device according to claim 10, wherein the potential of the potential supply line is controlled by controlling and outputting an output potential from the potential supply unit.   The charge amplification unit further includes a reset transistor having a source connected to the signal charge storage unit, the amplification transistor and a drain of the reset transistor are connected to the potential supply line, and the source of the amplification transistor is The amplification type solid-state imaging device according to claim 5 or 6 connected to a signal line.   By setting and controlling the potential of the potential supply line to a low potential that does not allow the charge amplification unit to perform an output operation, the potential of the signal charge storage unit is maintained at the low potential and the output operation of the charge amplification unit is performed. The amplification type solid-state imaging device according to claim 14, which can be stopped.   The switch circuit is connected between a CMOS type switch circuit connected between the potential supply section and the potential supply line of the charge amplification section, and between an output section of the feedback circuit and the potential supply line of the charge amplification section. The amplification type solid-state imaging device according to claim 10, further comprising a switching transistor.   The amplification type solid-state imaging device according to claim 1, further comprising a switch circuit that switches and connects a constant power supply potential and the constant current load circuit to the output unit of the charge amplification unit.   The amplification type solid-state imaging device according to claim 18, wherein the output operation of the charge amplification unit can be stopped by short-circuiting the input unit and the output unit of the charge amplification unit.   The charge amplification unit further includes a reset transistor having a source connected to the signal charge storage unit, and a drain of the reset transistor is connected to the potential supply line through the amplification transistor and connected to the signal line The amplification type solid-state imaging device according to any one of claims 5, 6, 18 and 19.   An electronic information device in which an image is taken using the amplification type solid-state imaging device according to any one of claims 1 to 20 as an imaging unit.

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