JP5183356B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

  The present invention relates to a solid-state imaging device and a driving method thereof.

  Patent Document 1 below discloses a problem of shading due to well potential fluctuations and a solution for providing a plurality of well potential supply units. Since a solid-state imaging device of a CMOS sensor generally has an amplifying transistor in a pixel and outputs an amplified signal as a voltage, the pixel output voltage also fluctuates when the pixel well potential fluctuates from a desired value during amplification and output. Resulting in. This well potential fluctuation causes shading of the CMOS sensor output. Patent Document 1 discloses means for fixing a well potential by providing a plurality of well potential supply portions in a pixel area in order to solve the problem.

JP 2001-230400 A

  However, there is a drawback that application is difficult when the pixel size is small. That is, when the pixel size is reduced, it is difficult to secure a space for providing a plurality of well potential supply units.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device capable of preventing the occurrence of shading by reducing the potential fluctuation of the well while reducing the number of well potential supply units in the pixel portion, and a driving method thereof. .

The solid-state imaging device according to the present invention includes a photoelectric conversion element that converts light into electric charge, and amplification that receives supply of a power supply potential from a power supply voltage node, amplifies the electric charge converted by the photoelectric conversion element, and outputs the amplified electric charge to a pixel output line A pixel portion including pixels for two-dimensionally arranged, and when the potential of the pixel output line varies depending on the output of the amplification transistor, the potential of the power supply voltage node and the potential of the pixel output line are And a first control means for controlling the potential of the power supply voltage node so as to fluctuate in opposite phases.

  By providing the pixels with potentials that change in opposite phases, the number of well potential supply portions in the pixel portion can be reduced, the well potential variation can be reduced, and shading can be prevented.

(First embodiment)
FIG. 3 is a block diagram illustrating a configuration example of the solid-state imaging device according to the first embodiment of the present invention, and FIG. 4 is a circuit diagram illustrating a configuration example of the pixel 121. The communication unit 152 transmits / receives a signal to / from the communication terminal and outputs the signal to the timing generation unit 151. The timing generation unit 151 receives the synchronization signal and outputs the timing signal to the scanning unit (first control unit) 142, the line memory unit 131, and the horizontal scanning unit 132.

  The pixel unit 12 includes pixels 121 that are two-dimensionally arranged. The scanning unit 142 outputs a reset signal φrst, a selection signal φsel, and a transfer signal φTx to each pixel 121 via the control line 143, and outputs the reset voltage Vrst and the voltage of the power supply voltage node VDD via the power supply line 144 to each pixel 121. Output to.

  In FIG. 4, a pixel 121 includes a photodiode (photoelectric conversion element) 101, a transfer transistor 102, a reset transistor 103, a selection transistor 104, an amplification transistor 105, and a floating diffusion (hereinafter referred to as FD) 13. Each pixel 121 is connected to the pixel output line 106. Hereinafter, the field effect transistor is simply referred to as a transistor. In this embodiment, the transistors 102 to 105 are n-channel transistors.

  The anode of the photodiode 101 is connected to the node of the back gate potential Vw. The transfer transistor 102 has a drain connected to the cathode of the photodiode 101, a gate connected to the node of the transfer signal φTx, a source connected to the FD 13, and a back gate connected to the node of the potential Vw. The reset transistor 103 has a drain connected to the node of the reset voltage Vrst, a gate connected to the node of the reset signal φrst, a source connected to the FD 13, and a back gate connected to the node of the potential Vw. Selection transistor 104 has a drain connected to power supply voltage node VDD, a gate connected to a node of selection signal φsel, and a back gate connected to a node of potential Vw. The amplifying transistor 105 has a drain connected to the source of the selection transistor 104, a gate connected to the FD 13, a source connected to the pixel output line 106, and a back gate connected to the node of the potential Vw.

  The photodiode 101 converts light into electric charge and accumulates it. The FD 13 has a region where charges can be accumulated. When the reset signal φrst is set to the high level, the reset transistor is turned on, and the FD 13 can be reset. Further, when the transfer signal φTx is set to the high level, the transfer transistor 102 is turned on, and the charge generated by the photodiode 101 can be transferred to the FD 13. In addition, when the selection signal φsel is set to a high level, the pixel 121 is selected in units of rows, and the selection transistor 104 in the pixel 121 is turned on. Then, the amplification transistor 105 enters an active state, amplifies the voltage of the FD 13, and outputs a pixel signal to the pixel output line 106.

  In FIG. 3, the scanning unit 142 sequentially outputs the selection signal φsel to the pixel unit 12 in units of rows. The pixel unit 12 outputs a pixel signal to the pixel output line 106 in units of rows. The vertical signal line 122 is connected to the pixel output line 106 for each column. The line memory unit 131 inputs and stores pixel signals in units of rows via the vertical signal lines 122. The horizontal scanning unit 132 sequentially outputs the pixel signals in the line memory unit 131 to the amplifier 133 in units of pixels. The amplifier 133 amplifies and outputs the pixel signal.

  FIG. 5 is a timing chart showing an operation example of the solid-state imaging device when the power supply voltage node VDD is fixed to the power supply potential Vdd. By setting the reset signal φrst to a high level, the reset transistor 103 is turned on, and the potential of the FD 13 is reset. When the selection signal φsel transitions to a high level at time T1, the selection transistor 104 is turned on and the potential of the pixel output line 106 is increased. This is because the amplification transistor 105 operates as a source follower, and a potential following the reset potential of the FD 13 appears on the pixel output line 106. Next, when the noise signal transfer signal φTn becomes high level, the noise signal based on the reset potential of the FD 13 is stored in the line memory unit 131 via the pixel output line 106. Next, when the transfer signal φTx becomes high level at time T2, the transfer transistor 102 is turned on, the charge of the photodiode 101 is transferred to the FD 13, and a pixel signal (including noise) based on the potential of the FD 13 is output to the pixel. Output on line 106. At time T3, the transfer signal φTx becomes low level. If no light is incident on the photodiode 101, the potential of the pixel output line 106 is the same as the noise signal before time T2, and if light is incident on the photodiode 101, a potential difference S is generated, and the pixel output line The potential at 106 decreases. Next, when the pixel signal transfer signal φTs becomes a high level, the pixel signal based on the potential of the FD 13 is stored in the line memory unit 131 via the pixel output line 106. Thereafter, the amplifier 133 outputs a signal obtained by subtracting the noise signal from the pixel signal stored in the line memory unit 131. Here, at the times T2 and T3, the potential of the FD 13 fluctuates due to the coupling capacitance between the gate of the transfer transistor 102 and the FD 13, and this appears as the potential fluctuation of the pixel output line 106.

  Since the amplification transistor 105 outputs an amplified signal as a voltage, when the well potential of the pixel 121 varies from a desired value during amplification and output, the output voltage of the pixel output line 106 also varies. This well potential fluctuation causes shading of the output of the solid-state imaging device.

  At time T1, when the selection switch 104 is turned on and a noise signal is output to the pixel output line 106, the potential of the n + region of the source of the amplifying transistor 105 varies. Accordingly, the potential of the p-well near the n + diffusion region of the source also fluctuates due to the junction capacitance between the source n + region and the p-well. Further, since the p-well potential of each pixel 121 is the back gate potential Vw of the transistors 102 to 105 of each pixel 121, the fluctuation of the well potential affects the outputs of the transistors 102 to 105. The well potential change not only changes the back gate potential Vw but also directly changes the potential of the FD 13 through the coupling capacitance between the well and the FD 13.

  Further, the potential variation of the pixel output line 106 has a great influence on the well potential variation. This is because the pixel output line 106 is arranged over all the pixels 121, and a coupling capacitance between these wirings and wells exists over the entire area of the pixel portion 12. The signals φrst, φsel, φTx are basically applied only to the pixels in the row to be output, and the coupling capacitance between the gates and wells of the transistors 103, 104, 102 to which the pulses of these signals are applied. The amount of fluctuation in the potential of the well passing through is relatively small.

  From FIG. 5, it can be seen that potential fluctuations in the main well of the pixel 121 are caused at times T1, T2, and T3. Hereinafter, an embodiment for preventing fluctuations in the potential of the well will be described.

  FIG. 1 is a timing chart showing an example of a driving method of the solid-state imaging device according to the first embodiment of the present invention. In the present embodiment, the power supply voltage node VDD is set to the power supply potential Vdd in the period from time T1 to T2 and in the period after time T3. The power supply voltage node VDD is set to a potential Ve lower than the power supply potential Vdd in the period before time T1 and the period from time T2 to T3.

  When the power supply voltage node VDD is set to the low potential Ve and the reset signal φrst is set to the high level, the resetting transistor 103 is turned on, and the potential of the FD 13 is reset. Thereafter, the reset signal φrst becomes low level. Next, when the selection signal φsel is set to the high level at time T1, the selection transistor 104 is turned on, and the potential of the pixel output line 106 is lowered. At that time, the power supply voltage node VDD is raised from the low potential Ve to the power supply potential Vdd. The amplification transistor 105 operates as a source follower, and a potential that follows the reset potential of the FD 13 appears on the pixel output line 106. Next, when the noise signal transfer signal φTn becomes high level, the noise signal based on the reset potential of the FD 13 is stored in the line memory unit 131 via the pixel output line 106. Thereafter, the noise signal transfer signal φTn becomes low level. Next, at time T2, the power supply voltage node VDD is set to the low potential Ve, and the transfer signal φTx is set to the high level. Then, the transfer transistor 102 is turned on, the charge of the photodiode 101 is transferred to the FD 13, and a pixel signal (including noise) based on the potential of the FD 13 is output to the pixel output line 106. At time T3, the power supply voltage node VDD is set to the power supply potential Vdd, and the transfer signal φTx is set to the low level. If no light is incident on the photodiode 101, the potential of the pixel output line 106 is the same as the noise signal before time T2, and if light is incident on the photodiode 101, a potential difference S is generated, and the pixel output line The potential at 106 decreases. Next, when the pixel signal transfer signal φTs becomes a high level, the pixel signal based on the potential of the FD 13 is stored in the line memory unit 131 via the pixel output line 106. Thereafter, the amplifier 133 outputs a signal obtained by subtracting the noise signal from the pixel signal stored in the line memory unit 131.

  The power supply voltage node VDD has a potential fluctuation that cancels the potential fluctuation of the well in a phase that is opposite to the potential fluctuation in the dark when there is no potential difference S of the pixel output line 106. The reason why the pixel output line 106 and the power supply voltage node VDD are used as a pair of canceling pulses is that the pixel output line 106 is connected to the source of the amplification transistor 105 or the power supply voltage node VDD is connected to the drain of the amplification transistor 105. Because. At this time, the coupling capacitance between the pixel output line 106 and the well and the positions of the power supply voltage node VDD and the well are very close to each other. That is, if the potential fluctuation amplitudes of the pixel output line 106 and the power supply voltage node VDD are equal and the fluctuation directions are opposite, the well potential fluctuations due to the respective wirings cancel each other. As a result, the well potential fluctuations can be reduced. it can.

  Based on such a premise, first, the power supply voltage node VDD plays a role as a power supply source of the amplifying transistor 105. The period during which the amplifying transistor 105 must perform an amplifying operation is a high-level pulse application period of the noise signal transfer signal φTn and the pixel signal transfer signal φTs in which the amplified signal is sampled. At least during this period, the power supply voltage node VDD needs to be at the power supply potential Vdd. Therefore, at time T1, the power supply voltage node VDD is allowed to change only in the rising direction. In order for the potential fluctuation of the pixel output line 106 at time T1 to cancel out the potential fluctuation of the power supply voltage node VDD, the fluctuation of the power supply voltage node VDD rises and the potential of the pixel output line 106 falls. It may be a fluctuation. Therefore, the pixel output line 106 is set to a potential higher than the potential of the noise signal before the time T1, and the power supply voltage node VDD is set to the low potential Ve before the time T1. For example, by using simple means such as a switch transistor (second control means) for switching the potential of the pixel output line 106 in the pixel output line 106, the potential of the pixel output line 106 before time T1. Can be controlled.

  In the period from time T2 to time T3, the power supply voltage node VDD is set to the low potential Ve so as to cancel the potential fluctuation of the pixel output line 106 in the dark, that is, when there is no signal. This is because the fluctuation of the well potential when the pixel signal is small most affects the image quality. Since the output of the amplifying transistor 105 is unnecessary during the period from time T2 to time T3 when the high level pulse of the transfer signal φTx is applied, even if the power supply voltage node VDD deviates from the power supply potential Vdd, inconvenience occurs as the operation of the pixel 121. Absent.

  At time T2, the fall of power supply voltage node VDD and the rise of transfer signal φTx cancel each other's well potential fluctuations. At time T3, the rise of power supply voltage node VDD and the fall of transfer signal φTx cancel each other's well potential fluctuations.

  If the pixel signal output potential in the dark at times T2 to T3 is selected as the potential of the pixel output line 106 before time T1, the potential fluctuations at the times T1, T2, and T3 of the power supply voltage node VDD can be set to be the same. Therefore, the power supply voltage node VDD can be a binary value of the power supply potential Vdd and the low potential Ve. If the potential fluctuation amount of the pixel output line 106 at the times T1, T2, and T3 and the potential fluctuation amount of the power supply voltage node VDD are equalized, the well potential canceling effect is maximized.

  If the potential of the pixel output line 106 set before time T1 can be set to the same level as the noise signal output potential at the reset level output between times T1 and T2, the potential fluctuation of the power supply voltage node VDD at time T1. May be zero. Therefore, power supply voltage node VDD can be set to power supply potential Vdd before time T1.

  1 can be realized, the scanning unit 142 has a switch transistor for switching the potential of the power supply voltage node VDD, or the potential of the power supply voltage node VDD can be switched by controlling. Further, a very simple means such as providing a switch transistor for switching the potential of the pixel output line 106 in the pixel output line 106 may be used. Detailed description is omitted.

  1 is the rising edge of the pulse of the selection signal φsel, but there is a CMOS pixel 121 having a configuration without the selection transistor 104. In that case, the selection operation of the pixel 121 may be the rising or falling edge of the pulse of the reset signal φrst of the FD 13. Also in this case, the well potential fluctuation is canceled by giving the potential fluctuation of the power supply voltage node VDD that cancels the potential fluctuation of the pixel output line 106.

  As described above, according to the present embodiment, the potential fluctuations of the power supply voltage node VDD and the pixel output line 106 are controlled in opposite phases, thereby controlling the potential fluctuations of the two. The fluctuation of the received well potential can be suppressed small. Further, the number of well potential supply units that must be taken in the pixel unit 12 can be reduced, and the image quality can be improved.

(Second Embodiment)
FIG. 2 is a timing chart showing an example of a driving method of the solid-state imaging device according to the second embodiment of the present invention. In this embodiment, the local well fluctuation factor due to the pulse applied only to the signal readout row is suppressed in the drive for suppressing the well potential fluctuation over the entire pixel portion 12 shown in the first embodiment. Added drive for. A pulse applied to the gates of the transistors 102 to 105 changes the well potential through the gate capacitance. In response to this variation, the scanning unit (third control unit) 142 cancels the well variation by applying a reverse polarity pulse to the gates of the other transistors 102 to 105 in the immediate vicinity of the variation source transistors 102 to 105. . Hereinafter, the points of the present embodiment different from the first embodiment will be described.

  In FIG. 2, the reset signal φres is ternary, but since the reset potential of the FD 13 is a high potential close to the normal power supply potential, the reset transistor 103 is sufficiently kept off even at the intermediate potential level of the ternary pulse. ing.

  The reset signal φrst falls from the high level to the intermediate level at time T1, falls from the intermediate level to the low level at time T2, and rises from the low level to the intermediate level at time T3. The selection signal φsel rises from a low level to a high level at time T1. The transfer signal φTx rises from the low level to the high level at time T2, and falls from the high level to the low level at time T3.

  At time T1, the fall of the reset signal φrst and the rise of the selection signal φsel cancel each other's well potential fluctuations. Next, at times T2 and T3, the transfer signal φTx and the reset signal φrst have opposite polarities to cancel the potential fluctuation of the well.

  Compared to the case where the potentials of all the pixel portions 12 are fluctuated at a time like the potential variation of the pixel output line 106, the potential variation that the pulse of the signal applied to only one row basically has on the well as described above. The amplitude is relatively small. However, when the potential fluctuation due to the pixel output line 106 is suppressed by the method as in the first embodiment, local well potential fluctuation due to the pulse of the signal becomes conspicuous. On the other hand, according to the present embodiment, as shown in FIG. 2, fluctuations in well potential due to pulses of these signals can also be suppressed. Therefore, the present embodiment can further reduce the number of well supply units and improve the image quality as compared with the first embodiment.

  Note that, in the second embodiment, as a combination of transistors to which a pulse of a signal that cancels each other's potential variation is applied, it is desirable that the transistors are very close to each other. The closer the position where two pulses of signals having opposite polarities are applied, the more the well potential can be canceled. Further, the pulse of the signal applied for cancellation is supplied so as not to hinder the original signal reading operation.

  Other than the combinations of transistors shown in this embodiment, any combination of transistors to which a pulse of a signal that cancels a potential variation is applied may be used. The transfer transistors 102 in adjacent rows may be combined, and a reverse polarity pulse may be applied to the transfer transistors 102 in the adjacent row simultaneously with the pulse of the transfer signal φTx applied to the signal readout row. In this case, signal reading has already been completed in the adjacent row, and there is no influence on the necessary signal due to the reverse polarity pulse. A reverse polarity pulse may be applied to the reset transistor 103 in the adjacent row as a cancellation pulse for the pulse of the reset signal φrst applied to the signal readout row.

  As described above, in the first and second embodiments, a pulse that cancels the well potential fluctuation is applied to the pixel during the operation that causes the well potential fluctuation performed before the amplification and output operation of the pixel signal. . As a result, the fluctuation potential amplitude of the well can be suppressed to a small value, the well potential supply section in the pixel section 12 can be eliminated, or at least the number of well potential supply sections that must be provided in the pixel section 12 can be reduced. . Therefore, shading can be reduced while causing no increase in pixel defects or at least suppressing the increase. Thereby, a high-quality solid-state imaging device can be provided.

  In the solid-state imaging devices of the first and second embodiments, the pixel unit 12 includes pixels 121 that are two-dimensionally arranged. The pixel 121 includes a photoelectric conversion element (photodiode 101), a transfer transistor 102, a reset transistor 103, a selection transistor 104, and an amplification transistor 105. Here, the configuration of the pixel 121 is not limited to the configuration described in the embodiment. For example, the drain of the amplification transistor 105 is connected to the power supply voltage node VDD, the source of the amplification transistor 105 and the drain of the selection transistor 104 are connected, and the source of the selection transistor 104 is connected to the pixel output line. Also good. Alternatively, the pixel 121 may share the reset transistor 103, the amplification transistor 105, and the selection transistor 104 with the adjacent pixel. Note that the selection transistor 104 is not essential.

  The photoelectric conversion element 101 converts light into electric charge. The amplifying transistor 105 receives supply of the power supply potential from the power supply voltage node VDD, amplifies the charge converted by the photoelectric conversion element 101, and outputs the amplified charge to the pixel output line 106. The resetting transistor 103 resets the gate (FD13) of the amplifying transistor 105 in response to the reset signal φrst. The selection transistor 104 connects the amplification transistor 105 and the power supply voltage node VDD according to the selection signal φsel. The transfer transistor 102 transfers the charge converted by the photoelectric conversion element 101 in accordance with the transfer signal φTx to the gate (FD 13) of the amplification transistor 105.

  In the first embodiment, the scanning unit (first control unit) 142 controls the potential of the power supply voltage node VDD so that the potential of the power supply voltage node VDD and the potential of the pixel output line 106 fluctuate in opposite phases. To do.

  Specifically, the scanning unit 142 changes the potential of the power supply voltage node VDD when at least one of the reset signal φrst, the selection signal φsel, and the transfer signal φTx changes.

  The second control means such as a switch transistor sets the potential of the pixel output line 106 before the connection of the selection transistor 104 (before time T1) after the resetting transistor 103 is reset, after the connection of the selection transistor 104 (time). Control is made to be equal to or higher than the potential of the pixel output line 106 after T1. The scanning unit 142 controls the potential of the power supply voltage node VDD before connection of the selection transistor 104 (before time T1) to be equal to or lower than the power supply potential Vdd, and the power supply voltage after connection of the selection transistor 104 (after time T1). The potential of the node VDD is controlled to the power supply potential Vdd. Here, the means for changing the potential of the power supply voltage node VDD may be a switch transistor controlled by a pulse supplied from a timing generator or the like in addition to the scanning unit 142.

  Further, the scanning unit 142 controls the potential of the power supply voltage node VDD so that the potential of the power supply voltage node VDD is increased when the selection transistor 104 is connected (time T1). The line memory unit 131 controls the potential of the pixel output line 106 before connection of the selection transistor 104 (before time T1) so that the potential of the pixel output line 106 decreases when the selection transistor 104 is connected (time T1). To do.

  In the second embodiment, the scanning unit (third control unit) 142 performs control so that the gate potentials of the first and second transistors provided in the pixel unit 12 fluctuate in opposite phases.

  For example, the first and second transistors are provided in the same pixel. The first and second transistors are a reset transistor 103, a selection transistor 104, or a transfer transistor 102.

The first transistor is provided in one pixel. The second transistor is provided in a pixel in a row adjacent to the row of the one pixel. The first and second transistors are both the reset transistor 103 or the transfer transistor 102.
According to the first and second embodiments, by applying potentials that change in opposite phases to the pixel, the number of well potential supply units in the pixel unit is reduced, the potential variation of the well is reduced, and shading is generated. Can be prevented.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

5 is a timing chart illustrating an example of a driving method of the solid-state imaging device according to the first embodiment of the present invention. 6 is a timing chart illustrating an example of a driving method of a solid-state imaging device according to a second embodiment of the present invention. 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to a first embodiment of the present invention. It is a circuit diagram which shows the structural example of a pixel. It is a timing chart which shows the operation example of a solid-state imaging device when a power supply voltage node is fixed to a power supply potential.

Explanation of symbols

101 Photodiode 102 Transfer transistor 13 Floating diffusion 103 Reset transistor 104 Select transistor 105 Amplify transistor 106 Pixel output line

Claims (16)

A photoelectric conversion element that converts light into electric charge;
A pixel portion in which pixels are two-dimensionally arranged, including an amplifying transistor that receives supply of a power supply potential from a power supply voltage node and amplifies the charge converted by the photoelectric conversion element and outputs the amplified transistor to a pixel output line;
When the potential of the pixel output line varies due to the output of the amplifying transistor, the potential of the power supply voltage node is controlled such that the potential of the power supply voltage node and the potential of the pixel output line vary in opposite phases to each other. A solid-state imaging device comprising: a first control unit. The pixel is
A resetting transistor that resets the gate of the amplification transistor in response to a reset signal;
A transfer transistor that transfers the charge converted by the photoelectric conversion element in response to a transfer signal to the gate of the amplification transistor;
The solid-state imaging device according to claim 1, wherein the first control unit varies the potential of the power supply voltage node when the reset signal or the transfer signal varies. The pixel includes a reset transistor that resets a gate of the amplification transistor in response to a reset signal;
A selection transistor for connecting the amplification transistor and the power supply voltage node or the amplification transistor and a pixel output line in accordance with a selection signal;
A transfer transistor that transfers the charge converted by the photoelectric conversion element in response to a transfer signal to the gate of the amplification transistor;
The said 1st control means changes the electric potential of the said power supply voltage node at the time of the fluctuation | variation of at least any one of the said reset signal, the said selection signal, and the said transfer signal. Solid-state imaging device. The pixel includes a reset transistor that resets a gate of the amplification transistor in response to a reset signal;
A selection transistor that connects the amplification transistor and the power supply voltage node according to a selection signal;
Further, a second control for controlling the potential of the pixel output line after the reset transistor is reset and before the selection transistor is connected to a potential equal to or higher than the potential of the pixel output line after the selection transistor is connected. Having means,
The first control means controls the potential of the power supply voltage node before the connection of the selection transistor to a power supply potential or less, and sets the potential of the power supply voltage node after the connection of the selection transistor to the power supply potential. The solid-state imaging device according to claim 1, wherein The first control means controls the potential of the power supply voltage node so that the potential of the power supply voltage node is increased when the selection transistor is connected,
The second control means controls the potential of the pixel output line before the connection of the selection transistor so that the potential of the pixel output line is lowered at the time of the connection of the selection transistor. Item 5. The solid-state imaging device according to Item 4. The pixel includes a first transistor and a second transistor,
2. The solid-state imaging device according to claim 1, further comprising third control means for controlling the gate potentials of the first transistor and the second transistor to simultaneously change in opposite phases.   The first transistor and the second transistor are a reset transistor that resets a gate of the amplification transistor according to a reset signal, and a selection that connects the amplification transistor and the power supply voltage node according to a selection signal. The solid-state imaging device according to claim 6, wherein the solid-state imaging device is a transfer transistor that transfers a charge converted by the photoelectric conversion element according to a transfer signal to a gate of the amplification transistor. A first transistor provided in one pixel;
A second transistor provided in a pixel in a row adjacent to the row of one pixel;
2. The solid-state imaging device according to claim 1, further comprising third control means for controlling the gate potentials of the first transistor and the second transistor to simultaneously change in opposite phases.   The first transistor and the second transistor both have a reset transistor that resets a gate of the amplification transistor in response to a reset signal, or a charge converted by the photoelectric conversion element in response to a transfer signal. 9. The solid-state imaging device according to claim 8, wherein the solid-state imaging device is a transfer transistor that transfers to the gate of the amplification transistor. A photoelectric conversion element that converts light into electric charge;
A pixel portion in which pixels are two-dimensionally arranged, including an amplifying transistor that receives supply of a power supply potential from a power supply voltage node and amplifies the charge converted by the photoelectric conversion element and outputs the amplified transistor to a pixel output line;
First and second transistors provided in the pixel portion;
Have a third control means for controlling so that the gate potential of the first transistor and the second transistor are simultaneously varied in opposite phase to each other,
The solid-state imaging device, wherein the first transistor is a transfer transistor that transfers a charge converted by the photoelectric conversion element in accordance with a transfer signal to a gate of the amplification transistor .   The solid-state imaging device according to claim 10, wherein the first and second transistors are provided in the same pixel. Before Stories second transistor, the reset transistor for resetting the gate of the amplifying transistor, or, the power supply voltage node and the amplifying transistor in response to the selection signal or the amplifying transistor and the pixel, in response to the reset signal the solid-state imaging device according to claim 11, characterized in that the selection transistor capacitor for connecting the output line. A photoelectric conversion element that converts light into electric charge;
A pixel portion in which pixels are two-dimensionally arranged, including an amplifying transistor that receives supply of a power supply potential from a power supply voltage node and amplifies the charge converted by the photoelectric conversion element and outputs the amplified transistor to a pixel output line;
First and second transistors provided in the pixel portion;
And third control means for controlling the gate potentials of the first transistor and the second transistor to simultaneously change in opposite phases.
The first transistor is provided in one pixel;
The second transistor, the solid-state image sensor you characterized in that provided in the pixel rows adjacent to the row of the one pixel.   The first and second transistors are both a reset transistor that resets the gate of the amplification transistor in response to a reset signal, or a charge that is converted by the photoelectric conversion element in response to a transfer signal. The solid-state imaging device according to claim 13, wherein the solid-state imaging device is a transfer transistor that transfers to the gate of the transistor. A photoelectric conversion element that converts light into electric charge;
An amplifying transistor that receives supply of a power supply potential from a power supply voltage node, amplifies the charge converted by the photoelectric conversion element, and outputs the amplified charge to a pixel output line; A method for driving a solid-state imaging device,
When the potential of the pixel output line varies due to the output of the amplifying transistor, the potential of the power supply voltage node is controlled such that the potential of the power supply voltage node and the potential of the pixel output line vary in opposite phases to each other. A method for driving a solid-state imaging device, comprising a first control step. A photoelectric conversion element that converts light into electric charge;
A pixel portion in which a pixel including a two-dimensional array including an amplifying transistor that receives supply of a power supply potential from a power supply voltage node and amplifies the charge converted by the photoelectric conversion element and outputs the amplified charge to a pixel output line; possess first and second transistors provided in parts, the said first transistor, for transferring to transfer the electric charge converted by the photoelectric conversion element according to the transfer signal to the gate of the amplifying transistor A driving method of a solid-state imaging device which is a transistor ,
A solid-state imaging device driving method comprising: a third control step of controlling the gate potentials of the first transistor and the second transistor so as to simultaneously change in opposite phases.

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