JP2008005155A - Amplified solid-state imaging apparatus, its driving method, and electronic information device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a number of transistors in a pixel of an amplified solid-state imaging apparatus, and at the same time, to largely reduce a number of wiring. <P>SOLUTION: The apparatus includes photoelectric conversion elements 1 arranged in a two dimensional shape, charge transfer transistors 2 which perform charge transfer of signal charge from photoelectric conversion elements 1 to a floating diffusion unit 3, a reset transistor 4 which resets potential of the floating diffusion unit 3, and an amplification transistor 5 which amplifies potential of the floating diffusion unit 3 and reads out as an imaging signal. A pixel unit 11 is composed by commonly connecting a drain of the reset transistor 4 and a drain of the amplification transistor 5 connected to a power line 7 wired in a row direction, and at the same time, connecting a source of the amplification transistor 5 to a signal line 8 wired in a row direction; and the signal line 8 of the n-th row (n is an integer one or more) is shared by each pixel unit 11 (or 11A) of the (2n)th row and (2n+1)th row. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an amplification type solid-state imaging device such as an APS type image sensor having an amplification function in a pixel portion and a driving method thereof, for example, a digital video camera and a digital device using the amplification type solid-state imaging device as an image input device in an imaging portion. The present invention relates to an electronic information device such as a digital camera such as a still camera, an image input camera, a scanner, a facsimile, and a camera-equipped mobile phone.

  In general, this type of conventional amplifying solid-state imaging device includes a pixel unit having an amplification function and a scanning circuit (driving circuit) disposed around the pixel unit, and the pixel unit is formed by the scanning circuit. A configuration in which pixel data is read out from is widely used.

  As an example of such a conventional amplification type solid-state imaging device, the pixel portion is made of CMOS (Complementary Metal Oxide Semiconductor) so as to be advantageous for integrating the pixel portion with a peripheral driving circuit and a signal processing circuit. A configured APS (Active Pixel Sensor) type image sensor is known. Furthermore, in recent years, among the APS type image sensors, a four-transistor type in which four transistors are provided in a pixel unit is becoming mainstream so that high image quality can be obtained. This conventional four-transistor amplification type solid-state imaging device will be described in detail with reference to FIG.

  FIG. 8 is a circuit diagram showing a pixel configuration example in a conventional four-transistor amplification type solid-state imaging device.

  In FIG. 8, a conventional four-transistor amplification type solid-state imaging device includes a photoelectric conversion element 101 that converts subject light into signal charges in a pixel unit 100, and a signal diffusion from the photoelectric conversion elements 101 in a floating diffusion unit. A charge transfer transistor 102 for transferring charge to (FD) 103; a reset transistor 104 for resetting the potential of the floating diffusion portion 103; an amplification transistor 105 for amplifying the potential of the floating diffusion portion 103 and reading data; A selection transistor 106 for selectively reading signals from the pixel unit 100 is provided. Although not shown in FIG. 7, a plurality of such pixel units 100 are arranged in a two-dimensional matrix in the row direction and the column direction.

  The photoelectric conversion element 101 is usually configured by an embedded photodiode as a photoelectric conversion unit (light receiving unit) that converts subject light into signal charges. In this buried photodiode, for example, an N-type layer is formed in a P-type well region on an N-type silicon substrate, and a P + surface layer is formed on the surface portion of the N-type layer to prevent dark current, so that the N-type layer is formed. The layer is embedded.

  The charge transfer transistor 102 has a gate connected to a charge transfer transistor drive line TX provided in the horizontal direction, a drain connected to the photoelectric conversion element 101, and a source connected to the floating diffusion portion 103.

  The reset transistor 104 has its gate connected to the reset transistor drive line RST provided in the horizontal direction, its drain connected to the power supply line 107 provided in the vertical direction, and its source connected to the floating diffusion portion 103. Yes.

  The amplification transistor 105 has a gate connected to the floating diffusion portion 103, a drain connected to the power supply line 107, and a source connected to the drain of the selection transistor 106.

  The selection transistor 106 has its gate connected to the selection transistor drive line SEL provided in the horizontal direction, its source connected to the signal line 108 provided in the vertical direction, and its drain connected to the source of the amplification transistor 105. ing.

  The constant current load 110 is composed of a transistor, and is provided between the terminal of the signal line 108 and the ground. The constant current load 110 is driven and controlled so that a current flows by the control signal VL, and acts as a constant current load.

  With the above configuration, in the conventional four-transistor amplification type solid-state imaging device, first, the signal charge received by the subject light and accumulated in the photoelectric conversion element 101 is transferred to the floating diffusion unit 103 via the charge transfer transistor 102. Transferred.

  In the floating diffusion unit 103, the power supply voltage supplied from the power supply line 107 through the reset transistor 104 before the signal charge from the photoelectric conversion element 101 is transferred to the floating diffusion unit 103 through the charge transfer transistor 102. Is reset to the drain voltage Vd.

  Next, the charge transfer transistor 102 is turned on, and the signal charge is transferred from the photoelectric conversion element 101 to the floating diffusion portion 103 via the charge transfer transistor 102. The potential of the floating diffusion 103 after the reset and after the signal charge transfer is amplified by the amplification transistor 105 and read out to the charge read signal line 108 side via the selection transistor 106, and the end of the charge read signal line 108 is read. A signal is output to the subsequent stage according to the constant current load 110 connected to.

  In the conventional amplification type solid-state imaging device configured as described above, four transistors are required in the pixel unit 100, and in order to reduce the pixel size of the pixel unit 100, transistors in the pixel unit 100 are used. A method of reducing the number has been proposed. For example, Patent Document 1 proposes a method for reducing the number of selection transistors 106. This will be described in detail with reference to FIG.

  FIG. 9 is a circuit diagram illustrating a configuration example of a main part of a conventional amplification type solid-state imaging device disclosed in Patent Document 1. In FIG. In FIG. 9, parts having the same functions as those in FIG. In FIG. 9, a plurality of pixel units constituting a pixel region in a conventional amplification type solid-state imaging device are shown in units of rows, and although not shown here, normally, such units of rows (horizontal direction) are shown. ) Is repeated a plurality of times in the vertical direction (column direction), and a plurality of pixel units are arranged in a two-dimensional matrix in the row direction and the column direction.

  In FIG. 9, in this conventional amplification type solid-state imaging device, each pixel unit 200 is not provided with the selection transistor 106 of FIG. 8, and the reset transistor 104 has a drain provided in the horizontal direction. Connected to the power supply line VRD, the drain of the amplification transistor 105 is connected to the power supply line 107 provided in the vertical direction, and the source of the amplification transistor 105 is connected to the signal line 108 provided in the vertical direction. Furthermore, a constant current load 210 composed of a transistor that is driven and controlled by a control signal VL from a control signal line 211 provided in the horizontal direction is provided at each end of each signal line 108.

  With the above configuration, in this conventional amplification type solid-state imaging device, when reading out signal charges from each pixel unit 200, first, the voltages of the reset power supply line VRD and the reset transistor drive signal line RST are simultaneously set to the high level state. Then, the voltage of the floating diffusion portion 103 (FD) is reset to the high level state.

  Next, the voltage of the reset transistor drive signal line RST is changed to a low level state, and the reset transistor 104 is turned off. As a result, the floating diffusion portion 103 is brought into a floating state, and the potential of the floating diffusion portion 103 at this time is The reset level is read out to the signal line 108 by the amplification transistor 105.

  Thereafter, the voltage of the transfer transistor drive signal line TX is set to the high level state, and the signal charge from the photoelectric conversion element 101 is transferred to the floating diffusion portion 103 via the charge transfer transistor 102. The potential of the floating diffusion portion 103 after this charge transfer is read out to the signal line 108 by the amplification transistor 105 as a signal level.

  Finally, the voltage of the reset transistor drive signal line RST is again set to the high level state, the voltage of the reset power supply line VRD is set to the low level state, and the voltage of the floating diffusion unit 103 is reset to the low level state. . As a result, the floating diffusion portion 103 of the pixel unit 200 that has completed the signal readout operation is held in a low level state.

With the above operation, in the non-selected pixel where no signal is read, the potential of the floating diffusion portion 103 is set to the low level state via the reset transistor 104 by the reset power supply line VRD. On the other hand, in the pixel from which the signal is read (read pixel), the potential of the floating diffusion portion 103 is set to the high level by the reset power supply line VRD. If there is a sufficient potential difference between the low level state of these non-selected pixels and the high level state of the selected pixel, the amplification transistor 105 is selected as the selection transistor without providing the selection transistor 106 of FIG. 7 in the pixel unit 200 of FIG. 106, and only the signal charge from the signal readout pixel is read out to the signal line 108 by the amplification transistor 105.
JP-A-11-112018

  However, the conventional technique of Patent Document 1 has a problem that the number of wirings is large.

  Each pixel unit 200 in FIG. 9 is connected to a power supply line 108 and a signal line 107 in the vertical direction (column direction), and the number of wirings in the vertical direction is large as in the case of the pixel unit 100 in FIG. . In addition, a sufficient potential difference is generated between the low-level potential of the floating diffusion portion 103 of the non-selected pixel from which the signal charge is not read and the high-level potential of the floating diffusion portion 103 of the pixel from which the signal is read. , A reset power supply line VRD connected to the drain of the reset transistor 104 is wired in the horizontal direction. In FIG. 9, the horizontal selection transistor drive signal to which the selection transistor drive signal SEL of FIG. Although there are no lines, the number of reset power supply lines VRD is increased, and the number of wires in the horizontal direction is large as in the case of the pixel unit 100 of FIG.

  The present invention solves the above-described conventional problems, and amplifying solid-state imaging device capable of reducing the number of transistors in each pixel unit by reducing the number of selection transistors and the number of wirings, a driving method thereof, and the amplifying solid To provide an electronic information device such as a digital camera such as a digital video camera and a digital still camera, an image input camera, a scanner, a facsimile machine, a camera-equipped mobile phone device, etc. Objective.

  The amplification type solid-state imaging device according to the present invention is a pixel unit provided with a plurality of two-dimensional arrays in a row direction and a column direction in a light receiving region and amplifying means for amplifying a signal charge from the light receiving region to obtain an imaging signal And a signal readout drive unit that controls the pixel unit to read out and drive an imaging signal from the pixel unit, and sequentially communicates with each other in the column direction by sequentially pairing a plurality of pixel units adjacent in the row direction. The signal readout drive unit is connected to each of the signal lines, and the signal readout drive unit controls the drive so that the imaging signals of all the pixel units in the row direction are sequentially read out in a plurality of times for each of the plurality of pixel units in the pair. This achieves the above object.

  Preferably, in the amplification type solid-state imaging device of the present invention, a signal reading power supply voltage is supplied in a plurality of times for each of the plurality of pixel units in the pair.

  Further preferably, in the amplifying solid-state imaging device of the present invention, two pixel units adjacent in the row direction are sequentially paired and connected to each common signal line in the column direction, and the signal readout drive unit includes: Drive control is performed so that the image pickup signals of all the pixel units in the row direction are sequentially read out twice for each of the two pixel units in the pair.

  Further preferably, in the amplifying solid-state imaging device of the present invention, the power supply voltage for signal readout is supplied in two portions for each of the two paired pixel units.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the power supply voltage is alternately different for every two adjacent pixel units which are shifted by one column in one direction in the row direction from the combination of the paired two pixel units. So that it can be output to the power line.

  Further preferably, the signal readout driving unit in the amplification type solid-state imaging device of the present invention is configured so that the imaging signals of all the pixel units in the row direction are sequentially paired with two pixel units adjacent in the row direction. Each pixel unit corresponding to an odd number of two or common power supply lines and each pair of pixel units corresponding to an even number of two or common power supply lines are read sequentially. To drive control. These reading methods are also possible, but it is more preferable to read every other pixel unit as will be described later.

  Further preferably, the pixel unit in the amplification type solid-state imaging device of the present invention includes a photoelectric conversion element that converts image light into a signal charge, and a charge transfer unit that transfers the signal charge from the photoelectric conversion element to the floating diffusion portion. And a reset means for resetting the potential of the floating diffusion portion, the amplification means amplifies the potential of the floating diffusion portion and can be read out as the imaging signal, and the common signal line is connected to the pair. The output terminals of the amplifying means of a plurality of pixel units are connected in common. This pixel unit includes only the photoelectric conversion element, the charge transfer unit, the reset unit, and the amplification unit, and does not include a selection transistor in addition to the conventional photoelectric conversion element.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the power supply terminals of the reset unit and the amplification unit are commonly connected to a power supply line in the column direction.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the n-th (n is an integer of 1 or more) of the common signal lines is the (2n) -th column (n is an integer of 1 or more) and the (2n + 1) -th column. Are shared by the two pixel units.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the two pixel units in the (2n-1) -th column (n is an integer of 1 or more) and the (2n) -th column are paired, and the (2n + 1) -th column The two pixel units in the (2n + 2) column are paired, and the power supply voltages supplied to the two pairs via the respective power supply lines are respectively selected pixel units, non-selected pixel units, and non-selected pixel units. The selected pixel units are differentiated so as to be sequentially.

  Further preferably, in the amplification type solid-state imaging device of the present invention, a power supply voltage is applied to each of two adjacent pixel units straddling the pair of pixel units and the pair of adjacent pixel units. The selected pixel unit and the non-selected pixel unit, and the non-selected pixel unit and the selected pixel unit are differentiated sequentially.

  Further preferably, the power supply line in the amplification type solid-state imaging device of the present invention is drawn independently for each of the pixel units so that a power supply voltage can be supplied.

  Furthermore, it is preferable that the power supply line in the amplification type solid-state imaging device of the present invention is drawn out in common for each of the two pixel units in the pair so that a power supply voltage can be supplied.

  Further preferably, in the amplification type solid-state imaging device of the present invention, a power output unit capable of switching various power sources to the pixel unit, and an imaging signal from the pixel unit can be output via a common signal line. A signal output unit that controls the pixel unit, the power supply output unit, and the signal output unit to output an imaging signal from the pixel unit, and from the signal output unit. Read drive.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the power output unit switches the low voltage source that outputs a low voltage, the high voltage source that outputs a high voltage, and the high voltage source and the low voltage source. Power supply switching means for enabling.

  Further preferably, the amplification type solid-state imaging device of the present invention further includes first high voltage switch means for controlling on / off of the high voltage and second high voltage switch means for controlling on / off of the high voltage. The power supply switching means includes a first power supply switching means capable of switching between the high voltage via the first high voltage switch means and the low voltage, the high voltage via the second high voltage switch means, and the Second power source switching means capable of switching a low voltage is alternately provided for every two pixel units arranged in the row direction.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the low voltage and the high voltage are supplied to a control terminal of the amplification unit via the reset unit, and the amplification unit selects a non-selected pixel unit or a non-pixel unit. Selection control can be performed by the selected pixel unit.

  Further preferably, the signal output unit in the amplification type solid-state imaging device of the present invention includes an imaging signal output permission unit and a constant current load unit that permit the output of the imaging signal from the pixel unit via the common signal line. The imaging signal output is obtained from the connection point between the imaging signal output permission means and the constant current load means. Since this signal can be extracted from anywhere in the path from the common signal line to the constant current load means, the signal output unit can permit the output of the imaging signal from the pixel unit via the common signal line. A series circuit of imaging signal output permission means and constant current load means.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the power line is commonly connected for each column of a plurality of pixel units, and the signal line corresponds to two pixel units adjacent in one direction of the row direction. The two pixel units are commonly connected in the column direction, and the signal output unit is connected between the terminal portion of the signal line and the ground.

  Further preferably, the signal readout driving unit in the amplification type solid-state imaging device of the present invention outputs a first driving signal to drive and control the first high voltage switch means, and outputs a second driving signal to output the first driving signal. (2) Drive control of the high voltage switch means, output power supply control signal to drive control of the power supply switch means, and turn on the low voltage and the first high voltage switch means or the second high voltage switch means And the high voltage state by selecting the first high voltage switch means or the second high voltage switch means is selected.

  Further preferably, in the high-impedance state in the amplification type solid-state imaging device of the present invention, when the image signals of all the pixel units in the row direction are sequentially read out in two times in two pixel units adjacent in the row direction. In addition, a high voltage when the first high voltage switch means is turned on, a high impedance state when the second high voltage switch means is turned off, a high voltage when the second high voltage switch means is turned on, and the first high voltage A high-impedance state by turning off the switch means is sequentially selected, and the low voltage is selected after reading out the imaging signals of all the pixel units in the row direction. Preferably, in the high-impedance state in the amplification type solid-state imaging device of the present invention, the imaging signals of all the pixel units in the row direction are two pixels obtained by sequentially pairing two pixel units adjacent in the row direction. When sequentially reading in units of two, when the first high voltage switch means is turned on, the high voltage state when the first high voltage switch means is turned off, the high impedance state when the second high voltage switch means is turned off, and the second high voltage switch means A high voltage by turning on and a high impedance state by turning off the first high voltage switching means are sequentially selected, and the low voltage is selected after reading out the imaging signals of all the pixel units in the row direction.

  Further preferably, the signal readout drive unit in the amplification type solid-state imaging device of the present invention outputs a reset drive signal to drive and control the reset unit, and sets the control terminal of the amplification unit to the voltage from the power supply output unit. After resetting, the charge transfer drive signal is output to control the drive of the charge transfer means, and the signal charge of the photoelectric conversion element is transferred to the control terminal of the amplifying means. In response, the imaging signal is read from the output terminal of the amplification means.

  Further preferably, the signal readout drive unit in the amplification type solid-state imaging device of the present invention outputs a load control signal to drive and control the constant current load means, and also captures the imaging signals of all the pixel units in the row direction. Only when two pixel units adjacent in the row direction are sequentially read out, an output permission control signal is output, and the imaging signal output permission means is driven to permit output of the imaging signal. Preferably, the signal readout driving unit in the amplification type solid-state imaging device of the present invention outputs a load control signal to drive and control the constant current load means, and also captures the imaging signals of all the pixel units in the row direction. Only when the pixel units adjacent to each other in the row direction are sequentially paired and read out in two batches, the output permission control signal is output and the imaging signal output permission means is driven and controlled. To permit the output of the imaging signal.

  Further preferably, in the amplification type solid-state imaging device of the present invention, a light receiving set is constituted by each one of the photoelectric conversion element and the charge transfer means, and a plurality of the light receiving sets are arranged in the column direction in the pixel unit. And connected to the common floating diffusion portion.

  Further preferably, the charge transfer means in the amplification type solid-state imaging device of the present invention is constituted by a charge transfer transistor, and a charge for driving and controlling the charge transfer transistor between the light receiving sets arranged in a row direction. A transfer transistor drive line is connected in common to the gate of the charge transfer transistor and connected to the signal read drive unit.

  Further preferably, the reset means in the amplification type solid-state imaging device of the present invention is configured by a reset transistor, and a reset transistor drive line for driving and controlling the reset transistor is provided between the pixel units arranged in the row direction. Commonly connected to the gates of the transistors and connected to the signal readout drive unit.

  Further preferably, the charge transfer means in the amplification type solid-state imaging device of the present invention is constituted by a charge transfer transistor, and the charge transfer transistor drive for driving and controlling the charge transfer transistor between the pixel units arranged in the row direction. A line is commonly connected to the gates of the charge transfer transistors and is connected to the signal read drive unit.

  Further preferably, in the amplification type solid-state imaging device of the present invention, the reset means is constituted by a reset transistor, and the reset transistor is a depletion type MOS transistor.

  Further preferably, the photoelectric conversion element in the amplification type solid-state imaging device of the present invention is a buried type photodiode.

  Further preferably, in the embedded photodiode in the amplification type solid-state imaging device of the present invention, the other conductivity type layer is formed in one conductivity type well region, and one conductivity for preventing dark current is formed on the surface portion of the other conductivity type layer. A mold surface layer is provided and the other conductivity type layer is embedded.

  The driving method of the amplification type solid-state imaging device of the present invention is a driving method of the amplification type solid-state imaging device for driving the amplification type solid-state imaging device of the present invention, and is one power source of two pixel units adjacent in the row direction. A first step of applying a power supply voltage to the line and reading out an imaging signal from one of the pixel units arranged in the row direction from all the common signal lines, and then to the other power supply line of the two pixel units A second step of applying power supply voltage and reading out image signals from the remaining pixel units arranged in the row direction from all the common signal lines, and taking images from all the pixel units arranged in the row direction The signal is driven so as to be read out sequentially in two steps of the first step and the second step, whereby the above object is achieved. The driving method of the amplification type solid-state imaging device of the present invention is a driving method of the amplification type solid-state imaging device for driving the amplification type solid-state imaging device of the present invention, and two pixel units adjacent in the row direction are connected to each other. A power supply voltage is applied to two or common power supply lines that are odd-numbered in order, and image signals from every two pixel units arranged in the row direction are read out from all common signal lines. One step, and then applying a power supply voltage to two or common power supply lines in which the order of pairing is an even number, and imaging signals from every other two pixel units arranged in the row direction A second step of reading from all the common signal lines, and driving to sequentially read out the imaging signals from all the pixel units arranged in the row direction in two steps of the first step and the second step. And so on The purpose is achieved.

  Preferably, in the driving method of the amplification type solid-state imaging device of the present invention, after the first step and the second step, all power lines in the row direction are set to a low voltage and all the row direction power sources are set. A third step of setting a common signal line in a high impedance state, setting the reset unit in the row direction to a drive state, and resetting the floating diffusion portion in the row direction to a low potential;

  Further preferably, in the driving method of the amplification type solid-state imaging device of the present invention, before the first step, all the power supply lines in the row direction are connected to a high voltage and all the common signal lines in the row direction are set to the high voltage. A fourth step of bringing the reset means in the row direction into a driving state by setting the impedance state, and resetting the floating diffusion portion in the row direction to a high potential;

  An electronic information device according to the present invention uses the amplification type solid-state imaging device according to the present invention as an imaging unit, thereby achieving the above object.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, a plurality of pixel units adjacent in the row direction are sequentially paired and connected to each common signal line in the column direction, and the signal readout drive unit captures all the pixel units in the row direction. The drive control is performed so that the signals are sequentially read out in a plurality of times for each of the plurality of pixel units as a pair. This reduces the number of signal lines in each pixel unit.

  As described above, the signal lines are commonly connected to a plurality of columns of adjacent pixel units, for example, the second column (the (2n) column and the (2n + 1) column), and shifted by one column from the combination of, for example, two columns of this pixel unit. Power supply lines are independently connected to two columns (for example, the (2n-1) th column and the (2n) th column) of two adjacent pixel units. As a result, the number of signal lines in the column direction can be reduced from 1 to 0.5 per pixel unit. In addition, if the power supply lines are commonly connected to two columns (for example, the (2n-1) th column and the (2n) th column) of the two pixel units, the number of wirings of each power supply line in the column direction is further increased. It is possible to reduce the number from 1 to 0.5 per pixel unit.

  Further, the drive ends of the reset means and the amplifying means are commonly connected to a power supply line wired in the column direction. This eliminates the need for a reset power supply line as in the prior art disclosed in Patent Document 1, and prevents an increase in the number of lines in the row direction. Note that the drive ends of the reset means and the amplifying means may be separately connected to power supply lines wired in the column direction. In this case, however, resetting as in the prior art disclosed in Patent Document 1 is possible. Power supply lines are required, and the number of wirings in the row direction increases accordingly.

  Furthermore, in the present invention, a plurality of light receiving sets each including a photoelectric conversion element and a transfer transistor are provided in the column direction in one pixel unit, and are connected to a common floating diffusion section (control end of the amplifying means). By doing so, the floating diffusion part, the reset means and the amplification means are shared by the plurality of photoelectric conversion elements. Therefore, the number of elements (transistors) per photoelectric conversion element can be reduced, and the ratio of the photoelectric conversion element area within the pixel area, that is, the aperture ratio can be further improved.

  Furthermore, the reset unit drive lines are commonly connected between the pixel units arranged in the row direction, and the number of wirings in the row direction can be reduced by operating the pixel units in units of rows in the row direction. Become.

  Furthermore, the charge transfer means drive lines are connected in common between the pixel units arranged in the row direction or between the light receiving sets, and by operating the pixel units or the light receiving sets in units of rows in the row direction, wiring in the row direction is performed. The number can be reduced.

  When driving the amplifying solid-state imaging device of the present invention, the power supply voltage VD is applied to the power supply line in which the order in which two pixel units adjacent in the row direction are sequentially paired is an odd number, and arranged in the row direction. After the imaging signals from every other two pixel units are read out from all the signal lines, the power supply voltage VD is applied to the power supply line in which the order in which two pixel units adjacent in the row direction are sequentially paired is an even number Thus, it is possible to read out the imaging signals from the remaining every two pixel units arranged in the row direction from all the signal lines. As a result, even if there is one signal line for each pixel unit in two columns, it is possible to read out signals from every two pixel units in two steps.

  Furthermore, after reading out the imaging signals from all the pixel units arranged in the row direction, all the power lines are set to a low potential (low voltage Va), and all the signal lines are set to a high impedance state so that the horizontal lines It is also possible to reset the floating diffusion portion (control end of the amplifying means) of the row to a low potential by turning on the reset transistor.

  Further, after the signal readout from the pixel unit is completed, until the next readout operation is started, all the power lines in the row direction are connected to the power supply voltage VD, and all the signal lines in the row direction are set high. It is preferable to be in an impedance state. As a result, since the power supply line is fixed at a high potential during photoelectric conversion accumulation operation in which signal reading from the pixel unit is not performed, excess signal charge generated by excessive incident light in the photoelectric conversion element Even if it flows into the power source, it is discharged to the power supply line side through the reset transistor, and the blooming phenomenon can be prevented. The above operation is more effective if the reset transistor as the reset means is a depletion type.

  Furthermore, by making the photoelectric conversion element an embedded photodiode, it becomes easy to transfer charges completely from the photoelectric conversion element to the detection unit (floating diffusion unit), and further, the dark current generated in the photoelectric conversion element is reduced. It is also possible to reduce the image quality, and a high-quality image can be obtained.

  As described above, according to the present invention, the number of selection transistors is reduced in order to reduce the pixel size, and the number of signal lines in the column direction is reduced from 1 to 0.5 per pixel unit. Since the number of wires is also reduced, the number of wires can be greatly reduced and the device configuration can be simplified. Furthermore, the number of transistors per photoelectric conversion element can be greatly reduced by providing a plurality of light receiving sets each consisting of one photoelectric conversion element and one transfer transistor in the pixel unit in the vertical direction and connecting them to a common floating diffusion. Thus, the aperture ratio can be further improved.

Embodiments 1 to 3 of the amplification type solid-state imaging device and the driving method thereof according to the present invention will be described below in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a circuit diagram illustrating a configuration example of a main part of an amplification type solid-state imaging device according to Embodiment 1 of the present invention.

  In FIG. 1, an amplification type solid-state imaging device 10 of Embodiment 1 includes a plurality of pixel units 11 arranged in a two-dimensional matrix in a row direction and a column direction in a light receiving region, and various power sources for each pixel unit 11. Each pixel unit 11 is driven and controlled for each of a plurality of pixel units 11 for one line in the row direction, a power output unit 12 that enables switching, and the like, a signal output unit 13 that outputs an imaging signal from each pixel unit 11 Then, the image signal from each pixel unit 11 is read out sequentially via the vertical drive unit 14 which is a signal readout drive unit for reading and driving the signal and the signal output unit 13 every one or several lines in the row direction. A horizontal reading unit 15 for temporarily holding each image pickup signal and sequentially reading it is provided.

  The pixel unit 11 includes a photoelectric conversion element 1 that converts subject light into signal charge, and a charge transfer transistor as charge transfer means for transferring the signal charge from the photoelectric conversion element 1 to the floating diffusion portion (FD) 3. 2, a reset transistor 4 as reset means for resetting the potential of the floating diffusion section 3, and an amplification transistor 5 as amplification means for amplifying the potential of the floating diffusion section 3 and reading out signal charges Have.

  The photoelectric conversion element 1 is configured by, for example, an embedded photodiode as a photoelectric conversion unit (light receiving unit) that converts subject light into signal charges. For example, as shown in FIG. 2, the embedded photodiode has an N-type layer 1a of the other conductivity type layer formed in a P-type well region of one conductivity type on an N-type silicon substrate of the other conductivity type. A P + surface layer 1b, which is a one-conductive type surface layer, is formed on the surface portion of the layer 1a to prevent dark current, and an N-type layer 1a is embedded therein.

  The charge transfer transistor 2 has a gate connected to a charge transfer transistor drive line 2 a provided in the horizontal direction, a drain connected to the photoelectric conversion element 1, and a source connected to the floating diffusion portion 3. In addition, the gates of the transfer transistors 2 between the pixel units 11 in the row direction (horizontal direction) are commonly connected to a transfer transistor drive line 2a provided in the horizontal direction.

  The reset transistor 4 has a gate connected to a reset transistor drive line 4 a provided in the horizontal direction, a drain connected to a power supply line 7 provided in the vertical direction, and a source connected to the floating diffusion portion 3. Yes. Further, the gates of the reset transistors 4 between the pixel units 11 in the row direction (horizontal direction) are commonly connected to a reset transistor drive line 4a provided in the horizontal direction.

  The amplifying transistor 5 has a gate connected to the floating diffusion section 3, a drain connected to the power supply line 7, and a source (output terminal of the amplifying means) connected to a common signal line 8 (hereinafter simply referred to as a signal line 8). It is connected.

  The transfer transistor 2, the reset transistor 4 and the amplification transistor 5 are constituted by, for example, N-type MOS transistors, and the reset transistor 4 is desirably a depletion type MOS transistor.

  The power supply line 7 is connected in common to the drains (power supply ends) of the reset transistor 4 and the amplification transistor 5 and is arranged in the vertical direction (column direction), and supplies a power supply voltage to each pixel unit 11 arranged in the row direction. Has been pulled out for.

  The power supply output unit 12 includes, for example, a low voltage source (not shown) that outputs a low voltage Va such as 0.5 V, and a high voltage source (not shown) that is a device power supply that outputs a power supply voltage VD (high voltage). And a PMOS transistor 121 as a first high voltage switch means for enabling power supply to every other pixel unit 11 by controlling on / off of the power supply voltage VD by the transistor drive signal PAo, and a power supply voltage by the transistor drive signal PAe. The PMOS transistor 122 as the second high voltage switching means capable of supplying power to every other pixel unit 11 by controlling the VD on / off, and the power supply voltage VD side via the PMOS transistor 121 or the PMOS transistor 122 And switch means 123 as power supply switching means that can be switched to either the low voltage Va side. Yes.

  These PMOS transistors 121 and PMOS transistors 122 are alternately arranged. For example, in FIG. 1, each of the pixel units 11 in the (2n-1) th column and the (2n + 1) th column (n is an integer of 1 or more). Each PMOS transistor 121 can be connected via the switching means 123, and each PMOS transistor 122 can be connected to each pixel unit 11 in the (2n) th column and (2n + 2) th column via the switching means 123. It is said that. That is, the power supply voltage supplied from the power output unit 12 via the power supply line 7 alternately to each pixel unit in the odd-numbered column and each pixel unit in the even-numbered column is supplied to the selected pixel unit and the non-selected pixel unit. The selected pixel unit and the selected pixel unit are differentiated sequentially. To explain further, such different power supply voltages are alternately applied to the selected pixel unit and the non-selected pixel unit, and the non-selected pixel unit and the selected pixel unit, respectively, to the odd-numbered pixel unit 11 and the even-numbered pixel unit 11. Are respectively supplied to the power lines 7. In this case, the power supply line 7 is drawn independently for each pixel unit 11 and can supply various power supply voltages.

  The switch means 123 is constituted by a semiconductor switch or the like that is selectively controlled to either the power supply voltage VD or the low potential Va connected via the PMOS transistor 121 or the PMOS transistor 122 by the switch control signal PH. When the switch means 123 is selected to the power supply voltage VD side, either the high impedance state when the PMOS transistor 121 or the PMOS transistor 122 is turned off, or the power supply voltage VD output state when the PMOS transistor 121 or the PMOS transistor 122 is turned on Selected.

  Therefore, the switch unit 123 has a low voltage Va, a power supply voltage VD when the PMOS transistor 121 or the PMOS transistor 122 is turned on, and a high impedance state when the PMOS transistor 121 or the PMOS transistor 122 is turned off with respect to each pixel unit 11. It can be switched to either. The switch unit 123 includes a first switch unit 123 serving as a first power source switching unit capable of switching between a high voltage and a low voltage via the PMOS transistor 121, and a high voltage (VD) and a low voltage via the PMOS transistor 122. Second switch means 123 serving as second power supply switching means capable of switching the voltage (Va) is alternately provided for every two pixel units arranged in the row direction. Note that these low voltage (Va) or high voltage (VD) is supplied to the gate of the amplification transistor 5 through the reset transistor 4, and the amplification transistor 5 is driven or stopped so as to select or not select the pixel unit. The pixel unit can be selectively controlled.

  The signal line 8 (Vsig) is an adjacent pixel unit 11, the pixel unit 11 in the (2n−1) -th column (n is an integer of 1 or more) and the pixel in the (2n) -th column arranged in the row direction. The sources (outputs of the amplification means) of the amplification transistors 5 of the unit 11 are connected in common and wired as the nth column in the vertical direction. Similarly, the (2 + 1) th column pixel unit 11 and the (2n + 2) th column pixel unit 11 arranged in the row direction share the (n + 1) th column signal line 8.

  That is, the pixel units 11 adjacent in the row direction are sequentially paired and connected to the respective common signal lines 8 in the column direction, and the respective signal output units 13 are connected to the respective common signal lines 8 respectively. The vertical drive unit 14 performs drive control so that one and the other imaging signals of each pair of pixel units 11 are sequentially read out from the common signal line 8. The common signal line 8 is sequentially commonly connected for each source of the amplification transistors 5 of the two pixel units 11 to be paired, and the n-th signal line 8 (n is an integer of 1 or more) is (2n−). It is shared by the pixel units 11 in the 1) row and the (2n) row.

  The signal output unit 13 includes a transistor 131 as a constant current load means that is driven and controlled as a constant current load by a control signal VL from a control signal line 131a provided in the horizontal direction at the end of the signal line 8, and a horizontal direction. A series circuit with a transistor 132 as an imaging signal output permission means that is ON / OFF controlled by a control signal PL from a control signal line 132a provided in the pixel unit 11 and that allows the output of an imaging signal from the pixel unit 11 via the signal line 8. Is provided. An imaging signal output is obtained from a connection point between the transistor 131 and the transistor 132.

  In FIG. 1, four pixel units 11 constituting the pixel region are exemplarily shown in row units. However, a plurality of pixel units 11 are also provided in the column direction, and a plurality of pixel units 11 in the column direction (vertical direction) are provided. Connection of the power supply line 7 and the signal line 8 to the pixel unit 11 will be described with reference to FIG.

  In FIG. 3, a power supply line 7 is provided for each column with respect to each pixel unit 11 (each drain of the reset transistor 4 and the amplification transistor 5) in the first line (first row) to the third line (third row). A common signal line 8 is connected between each line to a common connection line that is connected and commonly connected to the source of each adjacent amplification transistor 5 in one direction, and between the terminal portion of the signal line 8 and the ground, A signal output unit 13 composed of a series circuit of a transistor 131 and a transistor 132 is connected. That is, the power supply line 7 is connected to each column of the plurality of pixel units 11, and the signal line 8 is commonly connected in the column direction every two columns with the adjacent pixel unit 11 in the row direction.

  The vertical driver 14 outputs a transistor drive signal PAo to drive and control the PMOS transistor 121, outputs a transistor drive signal PAe to drive and control the PMOS transistor 122, and outputs a switch control signal PH to switch the switch means 123. Drive control is performed, the reset transistor drive signal RST is output to the reset transistor drive line 4a to control the drive of the reset transistor 4, and the charge transfer transistor drive signal TX is output to the charge transfer transistor drive line 2a to drive the charge transfer transistor 2. By controlling, driving the transistor 131 as a constant current load by outputting the control signal VL and controlling the drive of the transistor 132 by outputting the control signal PL, each pixel for each line in the row direction (horizontal direction) Read each image signal sequentially from unit 11 To drive.

  Therefore, in the configuration of the conventional amplification type solid-state imaging device shown in FIG. 9, two power supply lines 108 and one signal line 107 are required for each pixel unit 200 in the vertical direction. In contrast, in the configuration of the amplification solid-state imaging device 10 according to the first embodiment shown in FIG. 1, the signal line 8 is shared by the pixel units 11 in two columns, and the signal line 8 is equal to 0. Since five lines are sufficient, the number of wirings in the vertical power supply line 108 and the signal line 107 can be reduced from two to 1.5.

  Further, in the configuration of the conventional amplification type solid-state imaging device shown in FIG. 9, the potential of the floating diffusion portion in the pixel unit 200 that has finished the readout operation of the imaging signal is held at a low level, and the floating diffusion portion of the readout pixel is Since it is necessary to provide a potential difference between the read row and the non-read row by setting the potential to the high level state, it is necessary to wire the reset power supply line VRD of FIG. 9 in the horizontal direction. On the other hand, in the configuration of the amplification type solid-state imaging device 10 according to the first embodiment shown in FIG. 1, the drain of the reset transistor 4 and the drain of the amplification transistor 5 are connected in common. VRD is no longer necessary, and the number of wires in the horizontal direction can be reduced by the amount of the reset power supply line VRD.

  The photoelectric conversion element 1 is desirably an embedded photodiode. In this case, when charge is transferred from the photoelectric conversion element 1 to the floating diffusion portion 3 via the transfer transistor 2, it becomes easy to completely transfer the charge and no afterimage is generated. Further, the generation of dark current on the surface of the photodiode is suppressed, the dark current is reduced, and a high-quality image can be obtained.

  Hereinafter, a driving method of the amplification type solid-state imaging device 10 according to the first embodiment will be described in detail with reference to FIG.

  FIG. 4 is a signal waveform diagram showing an example of operation timing in the amplification type solid-state imaging device 10 of FIG. 1 and showing the timing of each drive signal from the vertical drive unit 14 of FIG.

  As shown in FIG. 4, first, in the period t1, the switch control signal PH is in the high level state, the transistor drive signals PAo and PAe are both in the low level state, and all the power supply lines 7 in the row direction are respectively connected to the power supply voltage lines. Side (power supply voltage VD). At the same time, a low-level control signal PL is output to the transistor 132 at the terminal portion of the signal line 8 to turn it off, so that a high impedance state in which no current flows through the signal line 8 is obtained. In this high impedance state, the reset transistor 4 is turned on (driving state) by the reset transistor driving signal RST, whereby each pixel unit 11 for each line, that is, each pixel unit 11 in all the columns of the row is In both cases, the potential of the floating diffusion portion 3 is reset to the power supply voltage VD. At this time, the charge transfer transistor drive signal TX is at a low level, the charge transfer transistor 2 is in an off state, no charge transfer is performed, and no current flows through the signal line 8. The influence of sharing the signal line 8 does not appear in this reset operation.

  That is, before the image signals are sequentially read out in two steps from all the pixel units arranged in the row direction, all the power lines in the row direction are connected to a high voltage and all the common signal lines in the row direction are connected. Is set to a high impedance state, the reset transistor 4 in the row direction is turned on, and the floating diffusion portion 3 in the row direction is reset to a high potential.

  Next, in the period t2, the power supply voltage VD side is selected while the switch control signal PH remains in the high level state, the PMOS transistor 121 maintains the on state while the transistor drive signal PAo remains in the low level state, The potential VDo of the power supply line 7 in the odd-numbered column in which the two pixel units 11 adjacent in the row direction are sequentially paired is set to the power supply voltage VD through the switch means 123, and the transistor drive signal PAe is in the high level state. The PMOS transistor 122 is turned off, and the potential VDe of the power supply line 8 in the even-numbered column in which the two pixel units 11 adjacent in the row direction are sequentially paired is in an open state (high impedance state) as shown by a dotted line in FIG. ). For example, referring to FIG. 1, the potential of the power supply line 7 to the pixel units 11 in the (2n-1) and (2n + 1) columns which are odd columns becomes the power supply voltage VD, and the (2n) column and (2n + 2) which are even columns. ) The potential of the power supply line 7 to the pixel units 11 in the column is open. At this time, a high-level control signal PL is output to the transistor 132 at the terminal portion of the signal line 8 to turn it on, and a current flows through the signal line 8. Thereby, the reset level Reset (o) is read out from each pixel unit 11 in the odd-numbered column paired in the period t2.

  In the period t3, the power supply voltage VD side is selected while the switch control signal PH remains in the high level state, the transistor drive signal PAe becomes the low level, the PMOS transistor 122 is turned on, and the even number column is set (2n). The potential VDe of the power supply line 7 of the pixel unit of the column and the (2n + 2) column is set to the power supply voltage VD through the switch means 123, and the transistor drive signal PAo is in the high level state, so that the PMOS transistor 121 is turned off. The potential VDo of the power supply line 7 of the pixel units in the (2n-1) and (2n + 1) columns is set to an open state (high impedance state) as indicated by a dotted line in FIG. Also at this time, the high-level control signal PL is still output to the transistor 132 at the terminal portion of the signal line 8, and this is turned on, and a current flows through the signal line 8. As a result, the reset level Reset (e) is read from each pixel unit 11 in the even-numbered column at time t3. In this manner, in each pixel unit 11 arranged in the row direction, the reset level is read out alternately every other two times.

  Thereafter, in the period t4, the switch control signal PH is in the high level state and the transistor drive signals PAo and PAe are both in the low level state, and all the power supply lines 7 in the row direction are connected to the power supply voltage lines (power supply voltage VD). To do. As a result, the potentials of the power supply lines 7 in all columns in the row direction become the power supply voltage VD. Further, the charge transfer transistor drive signal TX becomes high level, the charge transfer transistor 2 is turned on, and the signal charges from the photoelectric conversion elements 1 are transferred to the floating diffusion portion 3 in all columns. At this time, since the transistor control signal PL becomes a low level and the transistor 132 is turned off, the signal line 8 is in a high impedance state in which no current flows. Therefore, the influence of sharing the signal line 8 is charge transfer. Does not appear in action.

  In the period t5, the power supply voltage VD side is selected while the switch control signal PH remains in the high level state, and the PMOS transistor 121 maintains the on state while the transistor drive signal PAo remains in the low level state. The potential VDo of the power supply line 7 of the pixel units in the (2n-1) and (2n + 1) columns is set to the power supply voltage VD through the switch means 123, and the transistor drive signal PAe becomes a high level state so that the PMOS transistor 122 The potential VDe of the power supply lines 8 of the pixel units in the (2n) and (2n + 2) columns, which are even columns, is turned into an open state (high impedance state) as shown by a dotted line in FIG. At this time, a high-level control signal PL is output to the transistor 132 at the terminal portion of the signal line 8 to turn it on, and a current flows through the signal line 8. Thereby, in period 5, the signal level Signal (o) of the imaging signal after charge transfer is read from the pixel units 11 in the odd-numbered columns.

In the period t6, the power supply voltage VD side is selected while the switch control signal PH remains in the high level state, the transistor drive signal PAe becomes the low level, the PMOS transistor 122 is turned on, and the even number column is set (2n). The potential VDe of the power supply line 7 of the pixel unit of the column and the (2n + 2) column is set to the power supply voltage VD through the switch means 123, and the transistor drive signal PAo is in the high level state, so that the PMOS transistor 121 is turned off. The potential VDo of the power supply line 7 of the pixel units in the (2n-1) and (2n + 1) columns is set to an open state (high impedance state) as indicated by a dotted line in FIG. Also at this time, the high-level control signal PL is still output to the transistor 132 at the terminal portion of the signal line 8, and this is turned on, and a current flows through the signal line 8. Thereby, in the period t6, the signal level Signal (e) of the imaging signal after the charge transfer is read out from each pixel unit 11 in the even-numbered column. In this way, in each pixel unit 11 arranged in the row direction, the signal level of the imaging signal is read out alternately every other two times.
At this time, the charge transfer transistor drive signal TX is at a low level, the charge transfer transistor 2 is in an off state, and no charge transfer operation is performed.

  In this way, in the periods t5 and t6, the power supply voltage is applied to the two power supply lines 7 in which the order in which the two pixel units 11 adjacent in the row direction are sequentially paired is an odd number, and arranged in this row direction. A step of reading out the image pickup signals from every other two pixel units 11 from all the common signal lines, and then applying a power supply voltage to the two power supply lines 7 in which the paired order is an even number. And reading out the imaging signals from every other two pixel units 11 arranged in the direction from all the signal lines 8, so that the imaging signals are obtained twice from all the pixel units 11 arranged in the row direction. It can be driven so as to be read out sequentially.

  Finally, in the period t7, the switch control signal PH is in the low level state, and the transistor drive signals PAo and PAe are both in the low level state, and all the power supply lines 7 in the row direction are set to the low power supply voltage lines (low voltage Va). Connect to. As a result, the potentials of the power supply lines 7 in all the columns are fixed to the low voltage Va. At this time, the transistor control signal PL becomes a low level and the transistor 132 is turned off, so that the signal line 8 is in an open state (high impedance state). In this high impedance state, the reset transistor drive signal RST becomes high level and the reset transistor 4 is turned on, so that the pixel units 11 in all the columns of the row all set the potential of the floating diffusion portion 3 to the low voltage Va. Reset to. By this operation, all the pixel units 11 in the row can be set to the non-read mode (non-selected pixel unit).

  As described above, in the period t7, after sequentially reading the imaging signals from all the pixel units 11 arranged in the row direction in two steps, all the power lines in the row direction are set to the low voltage Va and the row direction is set. All the signal lines 8 in a high impedance state (the transistor 132 is in an off state), the row direction reset transistor 4 is in a driving state (an on state), and the row direction floating diffusion portion 3 is reset to a low potential. have.

As described above, even if the number of wirings is reduced by using one signal line 8 per two columns of pixel units 11, the image signals from the pixel units 11 of all columns are divided into two every two. Can be read easily and accurately.
(Embodiment 2)
In the first embodiment, the light receiving set is configured by one each of the photoelectric conversion element 1 and the charge transfer transistor 2, and one light receiving set is arranged in the column direction in the pixel unit 11. In the second embodiment, a case where two light receiving sets are arranged in the column direction and connected to the common floating diffusion portion 3 (control end of the amplification transistor 5) in the pixel unit 11 will be described.

  FIG. 5 is a circuit diagram showing a main configuration of an amplification type solid-state imaging device according to Embodiment 2 of the present invention. In FIG. 5, in the amplification type solid-state imaging device 10A, the plurality of pixel units 11A constituting the pixel region are shown only in row units (horizontal direction), and are not shown here, but usually in such row units. Is repeated a plurality of times in the column direction (vertical direction), and a plurality of pixel units 11A are arranged in a two-dimensional matrix in the row direction and the column direction. Note that members having the same operational effects as the constituent members of FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

  In FIG. 5, in the amplification type solid-state imaging device 10A, a light receiving set 20 is configured by one each of the photoelectric conversion element 1 and the transfer transistor 2, and two light receiving sets 20 are arranged in the column direction (vertical direction) in the pixel unit 11A. Are connected to a common floating diffusion section 3 (control end of the amplification transistor 5). Further, between the light receiving sets 20 arranged in the row direction (horizontal direction), the charge transfer transistor drive lines TX1 and TS2 are commonly connected to the gates of all the charge transfer transistors 2 in the row direction (horizontal direction). . The signal charge controlled by the charge transfer transistor drive line TX1 via the charge transfer transistor 2 and the charge controlled by the charge transfer transistor drive line TX2 via the charge transfer transistor 2 are sequentially read out separately. It is.

  Hereinafter, a driving method of the amplification type solid-state imaging device 10A according to the second embodiment will be described in detail with reference to FIGS. 6 and 7.

  6 shows an example of operation timing of the m-th line in the amplification type solid-state imaging device 10A of FIG. 5, and FIG. 7 shows an example of operation timing of the (m + 1) -th line of the amplification-type solid-state imaging device 10A of FIG. FIG. 6 is a signal waveform diagram showing the timing of each drive signal from the vertical drive unit 14A of FIG. The operation timing of the amplification type solid-state imaging device 10A shown in FIGS. 6 and 7 corresponds to one period in the blanking period in one horizontal scanning period.

  As the operation timing of the m-th line (m is an integer equal to or greater than 1; here m = 1) in the amplification type solid-state imaging device 10A, as shown in FIG. 6, first, in the period t1, the switch control signal PH is at a high level. The transistor drive signals PAo and PAe are both in the low level state, and all the power supply lines 7 in the row direction are connected to the power supply voltage line side (power supply voltage VD). At the same time, a low-level control signal PL is output to the transistor 132 at the terminal portion of the signal line 8 to turn it off, so that a high impedance state in which no current flows through the signal line 8 is obtained. In this high impedance state, when the reset transistor 4 is turned on (driven state) by the reset transistor drive signal RST, each pixel unit 11A for each line, that is, each pixel unit 11A in all the columns of the row is set. In both cases, the potential of the floating diffusion portion 3 is reset to the power supply voltage VD. At this time, the charge transfer transistor drive signal TX1 is at a low level, the charge transfer transistor 2 is in an off state, no charge transfer is performed, and no current flows through the signal line 8, so that the adjacent pixel unit 11A is in a high impedance state. The influence of sharing the signal line 8 does not appear in this reset operation.

  Next, in the period t2, the power supply voltage VD side is selected while the switch control signal PH remains in the high level state, the PMOS transistor 121 maintains the on state while the transistor drive signal PAo remains in the low level state, The potential VDo of the power supply line 7 in the odd-numbered column in which the two pixel units 11A adjacent in the row direction are sequentially paired is set to the power supply voltage VD through the switch means 123, and the transistor drive signal PAe is in the high level state. The PMOS transistor 122 is turned off, and the potential VDe of the power supply line 8 in the even-numbered column in which the two pixel units 11A adjacent in the row direction are sequentially paired is in an open state (high impedance state) as shown by a dotted line in FIG. ). For example, referring to FIG. 5, the potential of the power supply line 7 to the pixel units 11A in the (2n-1) and (2n + 1) columns which are odd columns becomes the power supply voltage VD, and the (2n) column and (2n + 2) which are even columns. ) The potential of the power supply line 7 to the pixel unit 11A in the column is open. At this time, a high-level control signal PL is output to the transistor 132 at the terminal portion of the signal line 8 to turn it on, and a current flows through the signal line 8. As a result, in the period t2, the reset level Reset (o) is read out from each pixel unit 11A in the odd-numbered column in which two are paired.

  In the period t3, the power supply voltage VD side is selected while the switch control signal PH remains in the high level state, the transistor drive signal PAe becomes the low level, the PMOS transistor 122 is turned on, and the even number column is set (2n). The potential VDe of the power supply line 7 of the pixel unit of the column and the (2n + 2) column is set to the power supply voltage VD through the switch means 123, and the transistor drive signal PAo is in the high level state, so that the PMOS transistor 121 is turned off. The potential VDo of the power supply line 7 of the pixel units in the (2n-1) and (2n + 1) columns is set to an open state (high impedance state) as indicated by a dotted line in FIG. Also at this time, the high-level control signal PL is still output to the transistor 132 at the terminal portion of the signal line 8, and this is turned on, and a current flows through the signal line 8. As a result, the reset level Reset (e) is read from each pixel unit 11A in the even-numbered column at time t3. In this way, in each pixel unit 11A arranged in the row direction, the reset level is read out alternately every other two times.

  Thereafter, in the period t4, the switch control signal PH is in the high level state and the transistor drive signals PAo and PAe are both in the low level state, and all the power supply lines 7 in the row direction are connected to the power supply voltage lines (power supply voltage VD). To do. As a result, the potentials of the power supply lines 7 in all columns in the row direction become the power supply voltage VD. Further, the charge transfer transistor drive signal TX1 becomes high level, the charge transfer transistor 2 is turned on, and the signal charges from the photoelectric conversion elements 1 are transferred to the floating diffusion portion 3 in all columns. At this time, since the transistor control signal PL becomes a low level and the transistor 132 is turned off, the signal line 8 is in a high impedance state in which no current flows. Therefore, the influence of sharing the signal line 8 is charge transfer. Does not appear in action.

  In the period t5, the power supply voltage VD side is selected while the switch control signal PH remains in the high level state, and the PMOS transistor 121 maintains the on state while the transistor drive signal PAo remains in the low level state. The potential VDo of the power supply line 7 of the pixel units in the (2n-1) and (2n + 1) columns is set to the power supply voltage VD through the switch means 123, and the transistor drive signal PAe becomes a high level state so that the PMOS transistor 122 The potential VDe of the power supply lines 8 of the pixel units in the (2n) and (2n + 2) columns, which are even columns, is turned into an open state (high impedance state) as shown by a dotted line in FIG. At this time, a high-level control signal PL is output to the transistor 132 at the terminal portion of the signal line 8 to turn it on, and a current flows through the signal line 8. Thereby, in period 5, the signal level Signal (o) of the imaging signal after charge transfer is read out from each pixel unit 11A in the odd-numbered column paired with two.

  In the period t6, the power supply voltage VD side is selected while the switch control signal PH remains in the high level state, the transistor drive signal PAe becomes the low level, the PMOS transistor 122 is turned on, and the even number column is set (2n). The potential VDe of the power supply line 7 of the pixel unit of the column and the (2n + 2) column is set to the power supply voltage VD through the switch means 123, and the transistor drive signal PAo is in the high level state, so that the PMOS transistor 121 is turned off. The potential VDo of the power supply line 7 of the pixel units in the (2n-1) and (2n + 1) columns is set to an open state (high impedance state) as indicated by a dotted line in FIG. Also at this time, the high-level control signal PL is still output to the transistor 132 at the terminal portion of the signal line 8, and this is turned on, and a current flows through the signal line 8. Thereby, in the period t6, the signal level Signal (e) of the imaging signal after the charge transfer is read from each of the even-numbered pixel units 11A. In this way, in each pixel unit 11 arranged in the row direction, the signal level of the imaging signal is read out alternately every other two times. At this time, the charge transfer transistor drive signal TX1 is at a low level, the charge transfer transistor 2 is in an off state, and no charge transfer operation is performed.

  Finally, in the period t7, the switch control signal PH is in the low level state, and the transistor drive signals PAo and PAe are both in the low level state, and all the power supply lines 7 in the row direction are set to the low power supply voltage lines (low voltage Va). Connect to. As a result, the potentials of the power supply lines 7 in all the columns are fixed to the low voltage Va. At this time, the transistor control signal PL becomes a low level and the transistor 132 is turned off, so that the signal line 8 is in an open state (high impedance state). In this high impedance state, the reset transistor drive signal RST becomes a high level and the reset transistor 4 is turned on, so that the pixel units 11A in all the columns of the row all set the potential of the floating diffusion portion 3 to the low voltage Va. Reset to. By this operation, all the pixel units 11A in the row can be set to the non-read mode (non-selected pixel unit).

  Next, after the blanking period of the first horizontal scanning period of the first line is finished, in the blanking period of the first horizontal scanning period of the second line, the (m + 1) th line in the amplification type solid-state imaging device 10A of the second embodiment. Although the operation timing of (m + 1 = 2 here) is shown in FIG. 7, it is substantially the same as the case of FIG. 6 from the period t1 to the period t7. Here, only the period t4 will be described.

  In the period t4 after the end of the period t1 to the period t3, as shown in FIG. 7, the switch control signal PH is in the high level state and the transistor drive signals PAo and PAe are both in the low level state. 7 is connected to a power supply voltage line (power supply voltage VD). As a result, the potentials of the power supply lines 7 in all columns in the row direction become the power supply voltage VD. Further, the charge transfer transistor drive signal TX2 becomes high level, the charge transfer transistor 2 is turned on, and the signal charges from the photoelectric conversion elements 1 are transferred to the floating diffusion portion 3 in all columns. At this time, since the transistor control signal PL becomes a low level and the transistor 132 is turned off, the signal line 8 is in a high impedance state in which no current flows. Therefore, the influence of sharing the signal line 8 is charge transfer. Does not appear in action. Thereafter, when the period t5 to the period t7 ends, the operation timing of the pixel unit 11A in the second row is repeated as described above.

  According to the above configuration, the floating diffusion unit 3, the reset transistor 4, and the amplification transistor 5 are shared by the plurality of photoelectric conversion elements 1. As an imaging device, one pixel is constituted by one photoelectric conversion element 1, so that the number of transistors per pixel can be reduced, and the area ratio of the photoelectric conversion element 1 within the pixel area can be effectively expanded. This is advantageous for increasing the light receiving sensitivity.

In the second embodiment, in the pixel unit 11A, the two light receiving sets 20 are arranged in the column direction (vertical direction) and connected to the common floating diffusion portion 3 (control end of the amplification transistor 5). However, the present invention is not limited to this, and in the pixel unit 11A, three or four or more light receiving sets 20 are arranged in the column direction (vertical direction), and the common floating diffusion unit 3 (the control terminal of the amplification transistor 5). ) May be connected. The light receiving set 20 has a configuration in which three or more of the light receiving sets 20 are arranged in the column direction (vertical direction), and the plurality of charge transfer transistors 2 in the row direction are commonly connected to the charge transfer transistor drive lines TX1, TX2, TX3, TX4,. You can also
(Embodiment 3)
In the first embodiment, the case where the power supply line 7 is drawn independently for each pixel unit 11 and the power supply voltage can be supplied has been described. However, in the third embodiment, the power supply line 7 is paired. A case where the power supply voltage can be supplied by being drawn in common to the two pixel units 11 will be described.

  FIG. 10 is a circuit diagram showing a configuration example of a main part of an amplification type solid-state imaging device according to Embodiment 3 of the present invention. Note that members having the same operational effects as the constituent members of FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

  In FIG. 10, the amplification type solid-state imaging device 10B according to the third embodiment is connected in common to each signal line 8 in the column direction by sequentially pairing the signal output ends of two pixel units 11 adjacent in the row direction. In addition, a power line 7 is commonly connected to two adjacent pixel units 11 that are shifted by one column in one direction in the row direction from the combination of the two pixel units 11 that form a pair. For each pixel unit 11, for example, output is possible such that the power supply voltage is alternately different, such as a high voltage VD and a low voltage Va. Also in this case, the power supply terminals of the reset transistor 4 and the amplification transistor 5 are commonly connected to the power supply line 7 in the column direction.

  Specifically, the n-th signal line 8 (n is an integer of 1 or more) is shared by the two pixel units 11 in the (2n-1) -th column (n is an integer of 1 or more) and the (2n) -th column. The n-th power supply line 7 (n is an integer of 1 or more) is paired with the two pixel units 11 in the (2n-2) -th column and the (2n-1) -th column. The (n + 1) th row of 7 is paired with the two pixel units 11 in the (2n) th row and the (2n + 1) th row. The power supply voltage supplied to each of these two pairs via the respective power supply lines 7 is made to be different sequentially for the selected pixel unit and the non-selected pixel unit, and the non-selected pixel unit and the selected pixel unit obtained by inverting the selected pixel unit. Yes.

  Also in the third embodiment, the vertical drive unit 14 as the signal readout drive unit has an odd order in which the imaging signals of all the pixel units 11 in the row direction are sequentially paired with two pixel units 11 adjacent in the row direction. The pixel unit 11 corresponding to the second common power line 7 and the pixel unit 11 corresponding to the common power line 7 corresponding to the even numbered common power line 7 are sequentially read in two times. Control.

  With the above configuration, the driving method of the amplification type solid-state imaging device 10B according to the third embodiment is also the same as in the case of FIG.

  Therefore, the number of signal lines 8 in the column direction can be reduced from 1 to 0.5 per pixel unit 11, and two columns (for example, (2n-2) columns of two pixel units 11 can be used. Since the power supply lines 7 are commonly connected to the (2n-1) th column), the number of power supply lines 7 in the column direction is also reduced from one to 0.5 per pixel unit 11. Can do.

  Although not specifically described in Embodiment 3, the light receiving set 20 is applied to the pixel unit 11 of the amplification type solid-state imaging device of Embodiment 3 as the pixel unit 11A of Embodiment 2 (FIG. 5). This can also reduce the number of transistor elements. Also in this case, each of the photoelectric conversion element 1 and the charge transfer transistor 2 constitutes the light receiving set 20, and in the pixel unit 11A, a plurality of light receiving sets 20 are arranged in the column direction (for example, two) and are shared. It is connected to the floating diffusion part 3.

  Further, as in the third embodiment, when the power supply line 7 is commonly connected to every two pixel units 11 that form a pair, in order to prevent a current path from the two pixel units 11 that form an adjacent pair. A rectifying element such as a diode may be added, or a voltage that does not become a selected pixel unit may be applied.

  As described above, according to the first to third embodiments, the two-dimensionally arranged photoelectric conversion elements 1, the charge transfer transistor 2 that transfers the signal charges from the photoelectric conversion element 1 to the floating diffusion unit 3, and the floating A reset transistor 4 that resets the potential of the diffusion unit 3 and an amplification transistor 5 that amplifies the potential of the floating diffusion unit 3 and reads it as an imaging signal. The drain of the reset transistor 4 and the drain of the amplification transistor 5 are arranged in the column direction. The pixel unit 11 is configured by being commonly connected to the wired power supply line 7 and the source of the amplification transistor 5 being connected to the signal line 8 wired in the column direction, and the (2n-1) th column (n is 1). The nth column signal line 8 is shared by each pixel unit 11 (or 11A) in the (2n) th column. In addition, in the third embodiment, the power line 5 of the nth column is shared by the pixel units 11 of the (2n-2) th column and the (2n-1) th column. As a result, the number of transistors in the pixel of the amplification type solid-state imaging device can be reduced and the number of wirings can be greatly reduced.

  Although not particularly described in the first to third embodiments, two pixel units 11 adjacent to each other in the row direction are sequentially paired, and the two power supply lines 7 are commonly used from the paired pixel units 11 respectively. The common signal line 8 is connected to each of the two adjacent pixel units 11 that are shifted by one column in the row direction from the combination of the two pixel units 11 that form a pair. Two pixel units 11 adjacent in the row direction are sequentially paired and connected to each common signal line 8 in the column direction, and image signals of all the pixel units in the row direction are connected to the two pixel units in the pair. The drive control may be performed so that the data is sequentially read out twice every 11 times. In this case, it is possible to output to the power supply line 7 so that the power supply voltage is alternately different for every two adjacent pixel units 11 that are shifted by one column in one direction in the row direction from the combination of the two pixel units 11 in the pair. Also good. In addition, the imaging signal may be sequentially read out in two times, the imaging signal may be sequentially read out in three times, the imaging signal may be sequentially read out in four times, or divided into a plurality of times. You may read an imaging signal sequentially.

  That is, a plurality of pixel units 11 adjacent in the row direction are sequentially paired and connected to each common signal line 8 in the column direction, and the vertical drive unit 14 captures image signals of all the pixel units 11 in the row direction. The drive control is performed so as to sequentially read out a plurality of times for each of a plurality of pairs of pixel units 11.

  In the first to third embodiments, the case where the drains of the reset transistor 4 and the amplification transistor 5 of the same pixel unit 11 are commonly connected to the power supply line 7 wired in the column direction has been described. Instead, the drains of the reset transistor 4 and the amplifying transistor 5 may be connected to the power supply line 7 wired in the column direction and other reset power supply lines VRD as in the prior art of FIG.

  Furthermore, in Embodiments 1 to 3 described above, reading is performed every other pixel unit. However, the present invention is not limited to this, and one column is shifted in one direction in the row direction from the combination of two pixel units that form a pair of signal lines. It may be possible to output to the power supply line so that the power supply voltage is alternately different for every two adjacent pixel units. In this case, the signal readout driving unit in the amplification type solid-state imaging device of the present invention has an odd order in which the imaging signals of all the pixel units in the row direction are sequentially paired with two pixel units adjacent in the row direction. The pixel units corresponding to the two or common power supply lines and the pixel units corresponding to the two or common power supply lines corresponding to the two or common power supply lines that are even in order are sequentially read in two steps. You may make it drive-control. Although such a reading method is also possible, it is more preferable to read every other pixel unit as in the first to third embodiments.

  Further, although not particularly described in the first to third embodiments, a digital camera such as a digital video camera or a digital still camera using the solid-state imaging device 10, 10A, or 10B of the first to third embodiments as an imaging unit. An electronic information device having an image input device such as an image input camera, a scanner, a facsimile, or a camera-equipped mobile phone will be described. The electronic information device according to the present invention performs high-quality image data obtained by using the solid-state imaging device 10, 10A, or 10B according to any of the first to third embodiments of the present invention as an imaging unit, and then performs predetermined signal processing for recording. A memory unit such as a recording medium for recording, a display means such as a liquid crystal display device for displaying the image data on a display screen such as a liquid crystal display screen after performing predetermined signal processing for display, and the image data for communication It has at least one of a communication unit such as a transmission / reception device that performs communication processing after performing predetermined signal processing, and an image output unit that prints (prints) and outputs (prints out) the image data.

  As mentioned above, although this invention has been illustrated using preferable Embodiment 1-3 of this invention, this invention should not be limited and limited to this Embodiment 1-3. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments 1 to 3 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to an amplification type solid-state imaging device such as an APS type image sensor having an amplification function in a pixel portion and a driving method thereof, for example, a digital video camera and a digital device using the amplification type solid-state imaging device as an image input device in an imaging portion. In the field of electronic information equipment such as digital cameras such as still cameras, image input cameras, scanners, facsimiles, and camera-equipped mobile phone devices, the number of select transistors is reduced to reduce the pixel size, and the signal in the column direction Since the number of lines is reduced from 1 to 0.5 per pixel unit and the number of lines in the horizontal direction is also reduced, the number of lines can be greatly reduced and the device configuration can be simplified. Furthermore, the number of transistors per photoelectric conversion element can be greatly reduced by providing a plurality of light receiving sets each consisting of one photoelectric conversion element and one transfer transistor in the pixel unit in the vertical direction and connecting them to a common floating diffusion. Thus, the aperture ratio can be further improved.

It is a circuit diagram which shows the principal part structural example of the amplification type solid-state imaging device which concerns on Embodiment 1 of this invention. It is a principal part longitudinal cross-sectional view in case the photoelectric conversion element of FIG. 1 is an embedded type. FIG. 2 is a circuit diagram showing a connection state between each pixel unit arranged in a column direction, a power supply line, and a signal line in the amplification type solid-state imaging device of FIG. 1. It is a signal waveform diagram which shows the example of operation timing in the amplification type solid-state imaging device of FIG. It is a circuit diagram which shows the principal part structural example of the amplification type solid-state imaging device which concerns on Embodiment 2 of this invention. FIG. 6 is a signal waveform diagram illustrating an example of operation timing in the amplification type solid-state imaging device of FIG. 5. FIG. 6 is a signal waveform diagram illustrating an example of operation timing in the amplification type solid-state imaging device of FIG. 5. It is a circuit diagram which shows the pixel structural example of the conventional amplification type solid-state imaging device. It is a circuit diagram which shows the example of a principal part structure of the other conventional amplification type solid-state imaging device. It is a circuit diagram which shows the principal part structural example of the amplification type solid-state imaging device which concerns on Embodiment 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photoelectric conversion element 2 Charge transfer transistor (charge transfer means)
3 Floating diffusion part (control end of amplification means)
4 Reset transistor (reset means)
5 Amplifying transistor (amplifying means)
Reference Signs List 7 power line 8 signal line 10, 10A, 10B amplification type solid-state imaging device 11, 11A pixel unit 12 power output unit 121 PMOS transistor (first high voltage switch means)
122 PMOS transistor (second high voltage switching means)
123 switch means (power switching means)
13 Signal output unit 131, 132 Transistor 131a, 132a Control signal line 14, 14A Vertical drive unit (signal read drive unit)
15 Horizontal readout unit 20 Light receiving set PH Switch control signal (Power switch control signal)
PAo transistor drive signal (first drive signal)
PAe Transistor drive signal (second drive signal)
Va Low voltage VD High voltage VDo, VDe Power line potential PL, VL Transistor control signal RST Reset transistor drive signal TX, TX1, TX2 Charge transfer transistor drive signal

Claims (30)

A plurality of two-dimensional arrangements in the light receiving region in the row direction and the column direction, and a pixel unit provided with amplification means for amplifying the signal charge from the light receiving region to obtain an imaging signal, and controlling the pixel unit, A signal readout drive unit that reads out and drives an imaging signal from the pixel unit;
A plurality of pixel units adjacent in the row direction are sequentially paired and connected to each common signal line in the column direction, and the signal readout driving unit forms the pair of image signals from all the pixel units in the row direction. An amplification type solid-state imaging device that performs drive control so as to sequentially read out a plurality of times for each of a plurality of pixel units.   The amplification type solid-state imaging device according to claim 1, wherein a power supply voltage for signal reading is supplied in a plurality of times for each of the plurality of pixel units as a pair.   Two pixel units adjacent to each other in the row direction are sequentially paired and connected to each common signal line in the column direction, and the signal readout drive unit receives the imaging signals of all the pixel units in the row direction. The amplification type solid-state imaging device according to claim 1, wherein drive control is performed so that each of the two pixel units is sequentially read in two steps.   The amplification type solid-state imaging device according to claim 3, wherein the power supply voltage for signal readout is supplied in two times for each of the two pixel units that form a pair.   The pixel unit includes a photoelectric conversion element that converts image light into a signal charge, a charge transfer unit that transfers a signal charge from the photoelectric conversion element to a floating diffusion unit, and a reset unit that resets the potential of the floating diffusion unit And the amplifying means amplifies the potential of the floating diffusion section so that it can be read out as the imaging signal, and the common signal line is provided for each output terminal of the amplifying means of the plurality of pixel units to be paired. The amplification type solid-state imaging device according to claim 1, which is commonly connected.   The amplification type solid-state imaging device according to claim 5, wherein power supply ends of the reset unit and the amplification unit are commonly connected to a power line in a column direction.   The amplification type solid-state imaging device according to claim 5, wherein the pixel unit includes only the photoelectric conversion element, the charge transfer unit, the reset unit, and the amplification unit.   5. The n-th common signal line (n is an integer of 1 or more) is shared by two pixel units in a (2n) -th column (n is an integer of 1 or more) and a (2n + 1) -th column. The amplification type solid-state imaging device described in 1. 9. The amplification type solid-state imaging device according to claim 6, wherein the power supply line is independently drawn for each of the pixel units so that a power supply voltage can be supplied.   The signal readout drive unit further includes a power output unit capable of switching various power sources to the pixel unit, and a signal output unit capable of outputting an imaging signal from the pixel unit via a common signal line. The amplification according to claim 1, wherein the pixel unit, the power output unit, and the signal output unit are controlled to output an imaging signal from the pixel unit and read out and drive from the signal output unit. Type solid-state imaging device.   The power supply output unit includes: a low voltage source that outputs a low voltage; a high voltage source that outputs a high voltage; and a power supply switching unit that enables switching between the high voltage source and the low voltage source. The amplification type solid-state imaging device described.   The first high voltage switch means for controlling on / off of the high voltage and the second high voltage switch means for controlling on / off of the high voltage are further included, and the power supply switching means includes the first high voltage switch means. A first power supply switching means capable of switching between the high voltage via the low voltage and the low voltage, and a second power supply switching means capable of switching between the high voltage via the second high voltage switch means and the low voltage, The amplification type solid-state imaging device according to claim 10, wherein the amplification type solid-state imaging device is alternately provided for each pixel unit arranged in the row direction.   12. The low voltage and the high voltage are supplied to a control terminal of the amplifying unit via the reset unit, and the selected pixel unit or the non-selected pixel unit can be selectively controlled by the amplifying unit. 12. The amplification type solid-state imaging device according to 12.   The said signal output part has a series circuit of the imaging signal output permission means and the constant current load means which permit permission of the output of the imaging signal from the said pixel unit via the said common signal line. Amplification type solid-state imaging device.   The power supply line is commonly connected for each column of a plurality of pixel units, and the signal line is commonly connected in the column direction for every two columns of pixel units corresponding to two pixel units adjacent in one direction in the row direction. The amplification type solid-state imaging device according to claim 6, wherein the signal output unit is connected between a terminal portion of the signal line and the ground.   The signal read drive unit outputs a first drive signal to drive and control the first high voltage switch means, outputs a second drive signal to drive and control the second high voltage switch means, and power supply switching control A signal is output to drive and control the power supply switching means, and the low voltage, the high voltage when the first high voltage switch means or the second high voltage switch means is turned on, and the first high voltage switch means The amplification type solid-state imaging device according to claim 15, wherein one of a high impedance state by turning off the second high voltage switch means is selected. In the high impedance state, when the imaging signals of all the pixel units in the row direction are sequentially read out in two times adjacent to the two pixel units in the row direction, the high impedance state is turned on by turning on the first high voltage switch means. A voltage and a high impedance state by turning off the second high voltage switch means, a high voltage by turning on the second high voltage switch means, and a high impedance state by turning off the first high voltage switch means are sequentially selected. ,
The amplification type solid-state imaging device according to claim 16, wherein the low voltage is selected after readout of imaging signals of all pixel units in the row direction.   The signal read drive unit outputs a reset drive signal to drive and control the reset unit to reset a control terminal of the amplification unit to a voltage from the power supply output unit, and then outputs a charge transfer drive signal to output the charge transfer drive signal. By driving and controlling the charge transfer means to transfer the signal charge of the photoelectric conversion element to the control end of the amplifying means, an imaging signal is output from the output end of the amplifying means in accordance with the potential due to the signal charge transferred. The amplification type solid-state imaging device according to claim 5, which is read out.   The signal readout driving unit outputs a load control signal to drive and control the constant current load unit, and sequentially reads out image pickup signals of all pixel units in the row direction from two pixel units adjacent in the row direction. 15. The amplification type solid-state imaging device according to claim 14, wherein only when the output permission control signal is output, the imaging signal output permission means is driven to permit output of the imaging signal.   A light receiving set is constituted by each one of the photoelectric conversion element and the charge transfer means, and a plurality of the light receiving sets are arranged in a column direction in the pixel unit and connected to the common floating diffusion portion. 5. The amplification type solid-state imaging device according to 5.   The charge transfer means comprises a charge transfer transistor, and a charge transfer transistor drive line for driving and controlling the charge transfer transistor is common to the gate of the charge transfer transistor between the light receiving sets arranged in a row direction. 21. The amplification type solid-state imaging device according to claim 20, wherein the amplification type solid-state imaging device is connected to the signal readout driving unit.   The reset means includes a reset transistor, and a reset transistor drive line for driving and controlling the reset transistor is commonly connected to a gate of the reset transistor between the pixel units arranged in a row direction. The amplification type solid-state imaging device according to claim 5, wherein the amplification type solid-state imaging device is connected to.   The charge transfer means is constituted by a charge transfer transistor, and a charge transfer transistor drive line for driving and controlling the charge transfer transistor is commonly connected to a gate of the charge transfer transistor between pixel units arranged in a row direction. The amplification type solid-state imaging device according to claim 5 or 18, connected to the signal readout driving unit.   The amplification type solid-state imaging device according to any one of claims 5 and 18 to 20, wherein the reset means includes a reset transistor, and the reset transistor is a depletion type MOS transistor.   The amplification type solid-state imaging device according to claim 5, wherein the photoelectric conversion element is an embedded photodiode. In the buried photodiode, the other conductivity type layer is formed in the one conductivity type well region, the one conductivity type surface layer for preventing dark current is provided on the surface of the other conductivity type layer, and the other conductivity type layer is The amplification type solid-state imaging device according to claim 25, which is embedded. A method of driving an amplification type solid-state imaging device for driving the amplification type solid-state imaging device according to claim 3,
A first step of applying a power supply voltage to one power supply line of two pixel units adjacent to each other in the row direction and reading out an imaging signal from one of the pixel units arranged in the row direction from all common signal lines;
And then applying a power supply voltage to the other power supply line of the two pixel units to read out image signals from the remaining pixel units arranged in the row direction from all the common signal lines. ,
A method for driving an amplification type solid-state imaging device, wherein driving is performed so as to sequentially read out imaging signals from all pixel units arranged in a row direction in two steps of the first step and the second step.   After the first step and the second step, all the power lines in the row direction are set to a low voltage, and all the common signal lines in the row direction are set to a high impedance state, and the reset means in the row direction is 28. The driving method of an amplification type solid-state imaging device according to claim 27, further comprising a third step of resetting the floating diffusion portion in the row direction to a low potential in a driving state.   Before the first step, all power lines in the row direction are connected to a high voltage, all common signal lines in the row direction are set in a high impedance state, and the reset means in the row direction is set in a driving state, 29. The driving method of an amplification type solid-state imaging device according to claim 27 or 28, further comprising a fourth step of resetting the floating diffusion portion in the row direction to a high potential. An electronic information device using the amplification type solid-state imaging device according to claim 1 for an imaging unit.

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