JP2007243094A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device in which the generation of shading is suppressed. <P>SOLUTION: The solid-state imaging device is provided with a pixel array 400 in which cells 150 each provided with at least one photodiode 101 are arranged in matrix, and a wiring such as power source lines 105 and vertical signal lines 106 which are arranged on the upper part of the pixel array 400. Of the power source lines 105 and the vertical signal lines 106, portions positioned on both neighborhoods in a line direction viewed from each photodiode 101 are formed into symmetry in a line direction viewed from each photodiode 101. With this configuration, variation can be reduced in incident characteristic of a light in the plane of each photodiode 101. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a MOS type solid-state imaging device used for a digital camera or the like.

  In recent years, applications of solid-state imaging devices (imaging chips) on which an imaging element is mounted have been expanded due to improvements in functions of the imaging element and progress in miniaturization. For example, a solid-state imaging device having a miniaturized imaging device is incorporated in a mobile phone or the like, while a solid-state imaging device with an emphasis on improving image quality is used for a high-end digital camera such as a single-lens reflex camera. The solid-state imaging device used for any product is common in basic configuration, and each solid-state imaging device includes a pixel array in which a plurality of cells receiving external light are arranged.

  14A to 14C are plan views showing cells of a conventional MOS type solid-state imaging device. FIG. 14A shows an impurity diffusion layer and a polysilicon wiring layer formed on the semiconductor substrate, and contacts for connecting the semiconductor substrate or the polysilicon wiring layer and the wiring of the first metal wiring layer. FIG. 14B is a plan view showing wiring formed in the first metal wiring layer in addition to the configuration shown in FIG. FIG. 14C is a diagram showing wiring formed in the second metal wiring layer in addition to the configuration shown in FIG. FIG. 15 is a view showing a cross section taken along line VIII-VIII shown in FIG. 14 of the conventional solid-state imaging device.

  As shown in FIGS. 14A to 14C, in the conventional cell, a photodiode 1501 that accumulates an amount of electric charge according to the intensity of received light, and an electric charge accumulated by the photodiode 1501 are transferred. Floating diffusion (hereinafter abbreviated as “FD”) 1530, a transfer transistor 1502 that is controlled by the potential of the transfer gate wiring 1508 and controls the transfer of charge from the photodiode 1501 to the FD 1530, and a reset gate wiring 1507 A reset transistor 1704 that initializes the potential of the FD 1530, an amplifying transistor 1703 that has a gate electrode connected to the FD 1530, a drain connected to the power supply line 1505, a source connected to the vertical signal line 1506, and constitutes a source follower, Amplifying transistor A gate wiring 1509 of 1703, and a FD wiring 1535 for connecting the gate wiring 1509 and FD1530, a wiring 1513. In the example shown in FIGS. 15A to 15C, the power supply line 1505 and the vertical signal line 1506 are formed in the first metal wiring layer, and the wiring 1513 is formed in the second metal wiring layer. The FD wiring 1535 is formed in the first metal wiring layer, and the gate wiring 1509 is formed in the polysilicon wiring layer. In the pixel array, a plurality of cells and photodiodes 1501 are arranged in a matrix (array). The FD wiring 1535 and the gate wiring 1509 are formed for each cell. In FIG. 14, a gate wiring in a cell adjacent to the cell provided with the gate wiring 1509 is shown as a gate wiring 1509 ″. Further, a vertical signal line adjacent to the vertical signal line 1506 is shown as a vertical signal line 1506 ″ for convenience.

  FIG. 16 is a diagram schematically showing a pixel array of a conventional solid-state imaging device. As shown in the figure, in a conventional solid-state imaging device, a plurality of cells 1600 are arranged in a matrix to form a pixel array. The substrate contact wiring 1540 is arranged for each column of the cells 1600 and is shared by a plurality of substrate contact cells 1601 arranged in one column. In this pixel array, a substrate contact cell 1601 is arranged for each fixed pixel.

  FIG. 17 is a schematic diagram illustrating another example of a pixel array of a conventional solid-state imaging device. A color filter is provided on each pixel, and each pixel recognizes one of G (green), R (red), and B (blue) colors. In this example, a 2 × 2 unit unit constituted by pixels that recognize G, R, and B constitutes a pixel array. This color arrangement is generally called a Bayer arrangement.

  The operation of the solid-state imaging device having the above will be described.

First, when a reset pulse signal is output from a vertical shift register (not shown), the reset transistor 1704 (see FIG. 14) operates to initialize the FD 1530 to the potential of the power supply line 1505. Next, when light hits the photodiode 1501, electric charge is stored in the photodiode 1501. Then, the charge accumulated in the photodiode 1501 is transferred to the FD 1530 through the transfer transistor 1502 selected by the vertical shift register. The potential of the FD 1530 is changed by the transferred charge. When the potential of the FD 1530 changes, the potential of the vertical signal line 1506 changes through the amplification transistor 1503. The change in potential of the vertical signal line 1506 passes through a noise suppression circuit (not shown), and is controlled by the selection transistor in the column selected by the horizontal shift register and output to the horizontal signal line.
JP 2004-273759 A JP-A-2005-142251 JP 2005-268537 A

  However, when the wiring is viewed from the photodiode 1501 in the conventional solid-state imaging device shown in FIGS. 14A to 14C, the shape of the wiring is different on the left and right (row direction). For this reason, in the conventional solid-state imaging device, the way light enters is different on the left and right, and unevenness in the brightness of the output image may occur. Hereinafter, this uneven brightness of the output image is referred to as “shading”.

  In addition, since the gate wirings located on the left and right sides of the photodiode 1501 have different shapes, photoelectric conversion characteristics may vary within the photodiode 1501 due to stress or the like. Such inconvenience becomes a significant problem particularly in applications requiring high image quality.

  The present invention has been made in view of such a problem, and an object thereof is to provide a solid-state imaging device in which the occurrence of shading is suppressed by devising a wiring layout in a pixel array.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes, in a cell provided with a photodiode, a portion of various metal wirings arranged on both sides of the photodiode, a diffusion layer of the amplification transistor, and an amplification transistor. At least one of the gate wirings is symmetrical in the row direction as viewed from the photodiode.

  As a result, variations in light incident characteristics, photoelectric conversion characteristics, and the like within the surface of each photodiode can be suppressed, so that occurrence of shading can be suppressed.

  For example, the solid-state imaging device of the present invention includes a photodiode that accumulates an amount of electric charge according to the intensity of received light, a floating diffusion to which the electric charge accumulated by the photodiode is transferred, and a photodiode to a floating diffusion. A pixel array in which a transfer transistor for controlling charge transfer, an amplification transistor for reading a signal corresponding to the charge transferred to the floating diffusion from a source, and a plurality of cells arranged on the substrate; And at least one photodiode and a transfer transistor are arranged in the cell. In the pixel array, the photodiodes are arranged in a matrix. Among the metal wirings, the photodiodes are arranged. Next to each row in each row Portion has a symmetrical row direction each other when viewed from the photo diode.

  With this configuration, the opening pattern of each photodiode is left-right symmetric when the row direction is the left-right direction, and the amount of light incident on the photodiode can be made uniform on the left and right of the photodiode. For this reason, it is possible to suppress variations in sensitivity within the surface of the photodiode and to effectively suppress the occurrence of shading.

  The type of metal wiring arranged symmetrically in the row direction as viewed from the photodiode is not particularly limited, but the metal wiring includes, for example, a power supply line and a vertical signal line. The metal wiring may include a substrate contact wiring as necessary. Since the layout of the plurality of wirings is changed for each column of photodiodes, the metal wirings are arranged symmetrically in the row direction as viewed from each photodiode.

  Since metal wiring blocks light incident from an angle, power supply lines, vertical signal lines, and substrate contact wiring are arranged so as to surround the top of each photodiode, so that the light enters the photodiode from above the adjacent cell. You can block the light to be. Therefore, the occurrence of color mixing can be suppressed.

  The vertical signal line, the power supply line, and the substrate contact wiring are arranged separately in either the first metal wiring layer or the second metal wiring layer. The power supply lines or the substrate contact wirings may be arranged separately for each column, but when arranged in the second metal wiring layer, they are adjacent as long as they surround each photodiode without gaps as a grid. Therefore, it is possible to prevent light incident obliquely from the cell to suppress color mixing. When the power supply line or the substrate contact wiring is arranged in the first metal wiring layer, the two adjacent power supply lines or the substrate contact wiring are connected to each other in a ladder shape so as to surround the photodiode. Also good. Further, when the power supply line or the substrate contact wiring is arranged in the first metal wiring layer together with the vertical signal line, the shape for the power supply line or the substrate contact so that the shape seen from the photodiode is the same as the shape of the vertical signal line. Wiring may be arranged. In this case, since the opening patterns of all the photodiodes can be made equal, variations in sensitivity of the photodiodes can be suppressed and the occurrence of shading or the like can be more effectively suppressed.

  Further, if the gate wirings of the amplification transistors arranged on both sides of the photodiode in the row direction are symmetrical in the row direction when viewed from the photodiode, the light incident on the photodiode can be symmetric. ,preferable. However, since the influence of the gate wiring on the incident light is smaller than the influence of the metal wiring on the incident light, the shape of the gate wiring may be the same in the pixel array.

  Note that at least one photodiode and one transfer transistor need only be arranged in each cell. For example, two or more photodiodes and transfer transistors may be arranged in one cell. When one photodiode and transfer transistor are arranged in one cell, the signal processing speed can be improved. On the other hand, when two or more photodiodes and transfer transistors are arranged in one cell, the area of the pixel array can be reduced.

  As described above, according to the solid-state imaging device of the present invention, the metal wirings etc. adjacent to one photodiode are arranged symmetrically in the row direction (left-right direction) as viewed from the photodiode, so that it can be viewed from the photodiode. In addition, the difference between the left and right layouts can be eliminated, and shading can be prevented.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIGS. 1A to 1C are plan views showing the layout of the pixel array of the solid-state imaging device according to the first embodiment of the present invention, which is a MOS type solid-state imaging device. FIG. 1A shows a polysilicon wiring layer and a contact (lower layer contact) for connecting a diffusion layer or polysilicon wiring formed on a semiconductor substrate and the wiring of the first metal wiring layer in the pixel array. (B) shows the wiring formed in the first metal wiring layer in addition to the configuration shown in (a), and (c) shows the second configuration in addition to the configuration shown in (b). It further shows the wiring formed in the metal wiring layer. In these figures, each of the portions surrounded by a dotted line is a cell 150. When one photodiode is provided in one cell as in the solid-state imaging device of the present embodiment, the cell is generally called a “pixel cell”. 2 is a cross-sectional view taken along the line II-II shown in FIGS. 1A to 1C of the solid-state imaging device according to the first embodiment. FIG. 3 is a circuit diagram showing the cell 150 in the solid-state imaging device according to the first embodiment.

  As shown in FIGS. 1A to 1C, 2, and 3, the cell 150 in the solid-state imaging device of this embodiment includes a photodiode 101 that accumulates an amount of electric charge according to the intensity of received light. Controlled by the FD 130 to which the charge accumulated by the photodiode 101 is transferred and the potential of the transfer gate wiring 108, and by the transfer transistor 102 for controlling the transfer of the charge from the photodiode 101 to the FD 130, and the reset gate wiring 107 The reset transistor 104 that initializes the potential of the FD 130, the gate electrode connected to the FD 130, the drain connected to the power supply line 105, the source connected to the vertical signal line 106, and the amplification transistor 103 constituting the source follower, and the amplification transistor 103 gate wiring 109, FD 130 and gate wiring The FD wiring 135 for connecting the 109, and a substrate contact wiring 112.

  As shown in FIG. 2, STI (Shallow Trench Isolation) is formed in the element isolation region 30 on the semiconductor substrate 10. A photodiode 101 is formed in the active region 20 surrounded by the element isolation region 30. Interlayer insulating films are formed between the polysilicon wiring layer and the first wiring layer and between the first wiring layer and the second wiring layer, respectively. Further, a color filter 40 is formed above the second wiring layer with an interlayer insulating film interposed therebetween, and a microlens 50 for collecting incident light on the photodiode 101 is formed on the color filter 40. . The color filter 40 has, for example, three colors of blue, green, and red, and the color filter 40 of any one color is disposed above one photodiode.

  FIG. 4 is a diagram schematically showing the configuration of the pixel array 400 and its peripheral circuits in the solid-state imaging device according to the present embodiment.

  As shown in the figure, in the solid-state imaging device of the present embodiment, the pixel array 400 includes a large number of cells 150 arranged in a matrix (array). The transfer gate line 108 and the reset gate line 107 are commonly connected to circuits in the cells 150 arranged in the same row. The vertical signal line 106 is commonly connected to the circuits in the cells 150 arranged in the same column. In the peripheral portion of the pixel array 400, noise is generated from a vertical shift register 401 that selects a cell 150 belonging to any row from the pixel array 400 via the transfer gate wiring 108 and a signal flowing through the vertical signal line 106. Are provided, a noise suppression circuit (CDS circuit) 402 that removes noise, a selection transistor 404 that transfers a signal from the noise suppression circuit 402 to the horizontal signal line 405, and a horizontal shift register 403 that controls the selection transistor.

  Next, the wiring layout and characteristics of the solid-state imaging device of this embodiment will be described.

  In the example shown in FIGS. 1A to 1C and FIG. 2, the power supply line 105 and the vertical signal line 106 are formed on the first metal wiring layer, and the substrate contact wiring 112 is formed on the second metal wiring layer. Has been. The gate wiring 109 is formed in the polysilicon wiring layer, and the FD wiring 135 is provided in the first metal wiring layer. Above the metal wiring layer, color filters such as G (green), R (red), and B (blue) are arranged in the same manner as the conventional example shown in FIG. In the pixel array 400, the photodiodes 101 are arranged in a matrix.

  The vertical signal line 106 extends in the column direction except for the branch portion 106-1, and is arranged for each column of the cells 150 (and the photodiodes 101). The gate wiring 109 and the FD wiring 135 are formed for each cell 150. In FIGS. 1 and 2, the FD in the cell 150 adjacent to the cell 150 in which the gate wiring 109 is provided in the row direction (left side in FIG. 1). The wiring is shown as a gate wiring 109 ″. Photodiodes in the cells arranged on both sides in the row direction of the cell 150 provided with the photodiode 101 (on the left and right sides shown in FIG. 1) are shown as photodiodes 101 ″ and 101 ′. Further, vertical signal lines arranged on both sides of the vertical signal line 106 are also shown as vertical signal lines 106 ″ and 106 ′ for convenience. However, when it is not necessary to specify which photodiode, vertical signal line, and gate wiring, these members will be described as “photodiode 101”, “vertical signal line 106”, and “gate wiring 109”. .

  In the pixel array 400, two vertical signal lines 106 and their branch portions 106-1 surround each of the photodiodes 101 arranged in one column, and are connected to each other in the form of a ladder (ladder). One power line 105 surrounds each of the photodiodes 101 arranged in one column. The columns of the photodiodes 101 surrounded by the vertical signal lines 106 and the columns of the photodiodes 101 surrounded by the power supply line 105 are alternately arranged.

  Both the reset gate wiring 107 and the transfer gate wiring 108 are made of polysilicon, and are arranged in the polysilicon wiring layer.

  A feature of the solid-state imaging device of the present embodiment is that it is arranged on both sides in the row direction of the photodiode 101 among metal wirings made of, for example, Al such as the vertical signal line 106, the power supply line 105, the substrate contact wiring 112, and the FD wiring 135. 1 and a gate wiring 109 formed in a polysilicon wiring layer and a diffusion layer (a source and a drain of the amplification transistor 103 shown in FIG. 1) formed in a semiconductor substrate are arranged in each of the plurality of cells 150. It is provided so as to be symmetrical (line symmetric) in the row direction (left-right direction) when viewed from the diode 101. Here, “symmetric with respect to the row direction when viewed from the photodiode 101” means “symmetric with respect to the center line of the photodiode 101 extending in the column direction”.

  With this configuration, the amount of light incident on each photodiode 101 from one side can be made equal to the amount of light incident from the other side. For this reason, the incident characteristics of light entering the photodiode 101 from both sides can be made substantially equal. In addition, the amount and direction of light incident on each of the plurality of cells 150 can be made uniform with the above configuration, that is, the light incident characteristics on each cell 150 can be made uniform with the above configuration. As a result, variation in light incident on each cell 150 can be suppressed, so that occurrence of shading can be suppressed.

  In particular, in the solid-state imaging device according to the present embodiment, the vertical signal line 106, the power supply line 105, the FD wiring 135, and the substrate contact wiring 112 excluding the branch portion 106-1 are symmetrical in the row direction as viewed from the photodiode 101. Is arranged.

  Further, the incident characteristics of light can be made uniform for each cell 150 by arranging the contacts so as to be symmetrical in the row direction when viewed from each photodiode 101.

  Further, both the FD wiring 135 of the amplification transistor 103 and the FD wiring 135 are symmetrical in the row direction when viewed from the respective photodiodes 101. This also makes it possible to make the light incident characteristics uniform between the left half and the right half of the photodiode 101 shown in FIGS.

  The vertical signal line 106, the power supply line 105, and the substrate contact wiring 112 are arranged so as to surround each photodiode 101. Thereby, light incident obliquely from the cells 150 adjacent in the vertical direction (column direction) and the horizontal direction (row direction) can be reduced, and color mixing can be prevented. Here, the substrate contact wiring 112 functioning as a light shielding layer may be formed in a lattice shape, for example. The substrate contact wiring 112 can be omitted if some color mixture is allowed. In this case, since the optical path of light incident on the photodiode 101 from an oblique direction can be secured, the sensitivity can be improved. Further, since it is not necessary to provide the second metal wiring layer, the number of manufacturing steps can be reduced.

  Further, two adjacent power supply lines 105 are combined into a ladder shape and surround the photodiode 101 without a break, so that light that should enter the cell 150 adjacent to the top and bottom leaks to the photodiode 101. Can be prevented.

  On the other hand, the vertical signal lines 106 adjacent to each other cannot be connected. Therefore, for example, a space 111 is formed between the vertical signal line 106 and the branch portion 106′-1 of the vertical signal line 106 ′ that are adjacent to each other, and the branch portion 106-1 of the vertical signal line 106 and the vertical signal line 106 ′. A space 110 is formed between the two. The distance between the vertical signal line 106 and the branch portion 106′-1 (the width of the space 111) and the distance between the vertical signal line 106 ′ and the branch portion 106-1 (the width of the space 110) are the minimum widths that can be separated in the manufacturing process. It has become. This makes it difficult for light to be incident on the photodiodes 101 adjacent in the vertical direction (column direction) to leak to the photodiodes 101, so that the incident characteristics of light at the photodiodes 101 surrounded by the vertical signal lines 106 can be determined as a power source. The incident characteristic of light at the photodiode 101 surrounded by the line 105 can be approached. In addition, when the planar shape of the photodiode 101 is a quadrilateral, the spaces 110 and 111 are arranged in the corner direction when viewed from the photodiode 101, thereby reducing the influence of light leaking from the cell 150 adjacent in the vertical direction. The occurrence of color mixing can be suppressed. Further, since the adjacent vertical signal lines 106 and 106 'both have a branch portion, a plurality of vertical signal lines having a branch portion and a vertical signal line having no branch portion are adjacent to each other. The variation in the parasitic capacitance generated between the vertical signal lines can be reduced. Further, with respect to the photodiodes 101 in the cells 150 in one column, the spaces 110 and the spaces 111 are alternately arranged in the column direction, that is, the positions where the spaces 110 and the spaces 111 are point-symmetric when viewed from the center of the photodiode 101. Therefore, the incident characteristics of light to the photodiodes 101 adjacent in the column direction can be made uniform.

  Further, part of the impurity diffusion layers (sources and drains of the transfer transistor 102, the amplification transistor 103, and the reset transistor 104) provided on both sides of the photodiode 101 are arranged at symmetrical positions in the row direction when viewed from the photodiode 101. Has been. For this reason, the distance between each of the impurity diffusion layers adjacent to both sides in the row direction as viewed from the photodiode 101 (except for the FD 130) and the photodiode 101 is equal to each other, and the shapes of both impurity diffusion layers are Are equal. As a result, the stress received by the photodiode 101 from the impurity diffusion layer provided adjacent to one side is equal to the stress received by the photodiode 101 from the impurity diffusion layer provided adjacent to the other side. Can be equal. As a result, the photoelectric conversion characteristics in each photodiode 101 can be made substantially equal between the right half and the left half. Note that the FD 130 cannot be arranged symmetrically in the row direction when viewed from the photodiode 101. Nevertheless, the in-plane variation in the photoelectric conversion characteristics of the photodiode 101 is significantly larger than when the sources and drains of the transfer transistor 102, the amplification transistor 103, and the reset transistor 104 are not arranged at symmetrical positions when viewed from the photodiode 101. It becomes possible to suppress.

  In the solid-state imaging device of the present embodiment, the signal output via the horizontal signal line 405 shown in FIG. 4 is processed by a signal processing circuit (Digital Signal Processor; DSP) provided outside the solid-state imaging device. Alternatively, it may be processed by a signal processing unit provided on the same chip as the pixel array 400. In such a signal processing circuit or signal processing unit, signal variations between adjacent cells 150 may be corrected when signals from the pixel array 400 are processed. In this case, the occurrence of shading can be prevented more effectively.

  In this embodiment, a so-called 1-pixel 1-cell solid-state imaging device in which one photodiode 101 is provided in each cell 150 has been described, but a plurality of photodiodes 101 and transfer transistors 102 are provided in one cell 150. Even if the wiring layout of this embodiment is applied to a so-called multi-pixel 1-cell type solid-state imaging device, the occurrence of shading can be effectively suppressed.

  For example, a plurality of photodiodes 101, a transfer transistor that transfers charges accumulated in each photodiode 101, one amplification transistor 103, and one reset transistor 104 are arranged in one cell, and a plurality of pixels are arranged. One cell may be configured. In the case of a two-pixel one-cell solid-state imaging device, the reset transistor 104 and the amplification transistor 103 are shared by two pixels (photodiodes 101) adjacent to each other in the column direction. In one cell 150, two photodiodes 101 are arranged with the reset gate wiring 107 and the transfer gate wiring 108 interposed therebetween. Metal wirings such as the vertical signal lines 106, the power supply lines 105, and the substrate contact wirings 112 as viewed from the respective photodiodes 101 are provided at symmetrical positions in the row direction. A solid-state imaging device including three or more pixels (photodiodes) in one cell can also be manufactured.

  In these cases, the number of reset transistors 104 and amplification transistors 103 formed in the entire pixel array 400 can be reduced as compared with the solid-state imaging device of the present embodiment, so that the area per pixel can be reduced, and the pixel array 400 Can be reduced. It is also easy to increase the aperture ratio of the photodiode 101 without reducing the pixel area. However, in the multi-pixel 1-cell structure, since the area of the FD 130 is increased, the conversion gain in the FD 130 is lowered, and the sensitivity of the sensor may be lowered. For this reason, the solid-state imaging device according to the present embodiment that can improve the sensitivity is preferably used in applications in which performance is more important than area reduction.

  In addition, even when the wiring layout of this embodiment is applied to the cell 150 having a configuration in which a selection transistor is further arranged between the output portion of the amplification transistor 103 and the vertical signal line 106, the occurrence of shading can be suppressed.

  In the wiring layout of this embodiment, the gate wirings 109 of the amplification transistors 103 arranged on both sides of the photodiode are formed so as to be symmetrical in the row direction as viewed from the photodiode. In the case of the direction, the gate wiring 109 may be arranged symmetrically with respect to a center line extending in the column direction of the pixel array (and the photodiode).

  Note that in the present invention, a so-called multi-pixel 1-cell configuration in which a plurality of pairs of photodiodes 101 and transfer transistors 102 are provided in one cell 150, or an output portion (source) of the amplification transistor 103 and a vertical signal line are selected. The same effect as that of the solid-state imaging device of this embodiment can be expected even when applied to a configuration applied to the cell 150 having a configuration in which transistors are arranged. As will be described later, in the case of a multi-pixel 1 cell, it is sufficient that at least a plurality of photodiodes 101 and a plurality of transfer transistors 102 are provided in one cell 150. The cells 150 are not necessarily arranged in a matrix, but the photodiodes 101 are preferably arranged in a matrix.

  In the solid-state imaging device according to the present embodiment, the substrate contact wiring 112 has a lattice shape so as to block light from adjacent cells as shown in FIG. 1 and surrounds each photodiode 101. Is preferred. In this case, in the vertical signal line 106 arranged in the first metal wiring layer, the occurrence of color mixing can be suppressed without forming the branch portions 106 ′-1 and 106-1 surrounding the photodiode 101. Similarly, the occurrence of color mixing can be suppressed without forming a bridging portion that connects two adjacent power supply lines 105.

-Modification of the first embodiment-
FIG. 5 is a plan view showing the layout of the pixel array of the solid-state imaging device according to the first modification of the first embodiment. In the drawing, a diffusion layer formed on the semiconductor substrate, a polysilicon wiring layer, and a contact (lower layer contact) for connecting the diffusion layer or the polysilicon wiring layer and the first metal wiring layer are shown.

  In the solid-state imaging device according to this modification, in each cell 150, portions (gate wiring) formed in the polysilicon wiring layer among the gate wirings 109 and 109 '' arranged on both sides in the row direction of the photodiode 101. Are arranged in the same shape and in the same direction. The shape of the portion of the gate wiring 109 provided in the polysilicon wiring layer has less influence on the light incident characteristics than the shape of the vertical signal line 106 and the power supply line 105. It does not have to be arranged symmetrically in the row direction. With this configuration, the sensitivity of the photodiode 101 between the cells 150 in the pixel array 400 can be made uniform.

  FIG. 6 is a plan view illustrating a layout of the pixel array of the solid-state imaging device according to the second modification of the first embodiment. In the solid-state imaging device according to the first embodiment shown in FIGS. 1A to 1C, the ladder-shaped power supply line 105 surrounds the photodiode 101. However, as in this modification, two power supply lines are used. The connecting portion 105 may be cut, and a space having the minimum width in the manufacturing process may be formed near the corner when viewed from the photodiode 101. Thereby, since the opening pattern on the photodiode 101 in all the cells becomes the same, the sensitivity of the photodiode 101 can be made uniform. At this time, branch portions 105a and 105b are provided in each of the two power supply lines 105 adjacent to each other, and 105a and 105b are alternately arranged, so that the parasitic capacitance generated in the power supply line 105 can be made uniform. it can.

  FIG. 7 is a plan view showing the layout of the pixel array of the solid-state imaging device according to the third modification of the first embodiment. In the solid-state imaging device according to the present modification, the spaces 110 and 111 formed between the vertical signal lines 106 and 106 ′ adjacent to each other overlap with the center line extending in the column direction of the photodiode 101 when viewed in plan. Is formed. In addition, a space is formed at a position where the two power supply lines 105 adjacent to each other overlap the center line of the photodiode 101 extending in the column direction. Thereby, since the opening pattern can be made the same above all the photodiodes 101, the sensitivity of the photodiodes 101 can be made uniform. In addition, for each of the power supply line 105 and the vertical signal line 106, a portion located in the column direction (vertical direction in FIG. 7) as viewed from the photodiode 101 is also symmetrical in the row direction. Thereby, the light incidence characteristics can be made uniform between the upper half and the lower half of the photodiode 101.

  FIGS. 8A to 8C are plan views showing the layout of the pixel array of the solid-state imaging device according to the fourth modification of the first embodiment. FIG. 8A shows a diffusion layer, a polysilicon wiring layer, and a lower layer contact formed on the semiconductor substrate in the pixel array, and FIG. 8B shows the first metal wiring layer in addition to the configuration shown in FIG. The wiring and the contact for connecting the first metal wiring layer and the second metal wiring layer are shown. (C) shows the wiring formed in the second metal wiring layer in addition to the configuration shown in (b). ing.

  In the solid-state imaging device according to this modification, a p-type well is formed in an n-type semiconductor substrate, and a cell 150 is formed in the p-type well. In order to reduce the resistance of the p-type well, a substrate contact region is provided in the p-type well for each cell 150, and this substrate contact region is formed in the second metal wiring layer through the contact. It is connected to the. Further, as shown in FIG. 8A, the gate wirings 109 and 109 ″ are routed longer in order to bypass the substrate contact region than the gate wirings 109 and 109 ″ shown in FIG. Yes.

  The substrate contact region is provided in order to reduce the resistance between the p-type well and the contact. When an n-type semiconductor substrate is used, compared with the case where a p-type semiconductor substrate is used, the charges that are photoelectrically converted in each cell 150 are less likely to be mixed, and the occurrence of color mixing can be suppressed. Further, by providing a substrate contact region for each cell 150, the substrate potential of the transistor can be stabilized and the response speed of the transistor can be improved. For this reason, the solid-state imaging device according to the present modification has a single color reflex camera or HD (High Definition) in which there is little color mixing and importance is placed on color reproducibility, when the number of pixels is large and the pixel array is large, or when a large frame rate is required. High definition) movie and the like. When a p-type semiconductor substrate is used, the substrate contact wiring 112 is connected to the p-type semiconductor substrate via the contact.

  In the solid-state imaging device according to this modification, it is preferable that the substrate contact wiring 112 has a lattice shape so as to block light from adjacent cells and surrounds the photodiodes 101. In this case, as shown in FIG. 8, in the power supply line 105 and the vertical signal line 106 arranged in the first metal wiring layer, the occurrence of color mixing can be suppressed without forming a branch portion surrounding the photodiode 101. it can. Further, it is preferable that the substrate contact regions and contacts adjacent to both sides of each photodiode 101 are also formed at positions symmetrical in the row direction as viewed from the photodiode 101.

  As in the conventional example shown in FIG. 16, a substrate contact pixel array may be provided and connected to the substrate contact wiring 112 in a substrate contact region formed in the pixel array.

(Second Embodiment)
FIGS. 9A to 9C are plan views showing the layout of the pixel array of the solid-state imaging device according to the second embodiment of the present invention. FIG. 9A shows a polysilicon wiring layer and contacts for connecting the diffusion layer or polysilicon wiring formed on the semiconductor substrate and the wiring of the first metal wiring layer in the pixel array. b) shows the wiring formed in the first metal wiring layer in addition to the configuration shown in (a), and the contact (via) connecting the first metal wiring layer and the second metal wiring layer. (C) further shows wiring formed in the second metal wiring layer in addition to the configuration shown in (b). FIG. 10 is a cross-sectional view taken along line XX shown in FIGS. 9A to 9C of the solid-state imaging device according to the second embodiment.

  The solid-state imaging device of the present embodiment is different from the solid-state imaging device of the first embodiment in part of the wiring layout. That is, the cell 250 in the solid-state imaging device of this embodiment includes a photodiode 201, an FD 230, a transfer transistor 202 having a gate electrode connected to the transfer gate wiring 208, and a gate electrode connected to the reset gate wiring 207. The reset transistor 204 includes an amplification transistor 203, a gate wiring 209 of the amplification transistor 203, an FD wiring 235, and a substrate contact wiring 212. Since the circuit configuration in the pixel array 500 and the function of each component are basically the same as those of the solid-state imaging device of the first embodiment, description thereof is omitted. 9 and 10, the FD wiring in the cell 250 adjacent to the cell 150 provided with the gate wiring 209 in the row direction (left side in FIG. 9) is shown as a gate wiring 209 ″. Photodiodes in the cells adjacent to the cell 250 provided with the photodiode 201 in the row direction (left and right sides shown in FIG. 9) are shown as photodiodes 201 ″ and 201 ′. Further, vertical signal lines arranged on both sides of the vertical signal line 106 are also shown as vertical signal lines 206 ″ and 206 ′ for convenience.

  A feature of the solid-state imaging device of this embodiment is that a substrate contact region is formed in the p-type well for each cell 250, and a power supply line 205 and a substrate contact wiring 212 are arranged in the first metal wiring layer. The vertical signal line 206 is disposed in the second metal wiring layer. Further, as the substrate contact region is formed, the gate wiring 209 is drawn longer than the solid-state imaging device of the first embodiment shown in FIG. 1 as in the example shown in FIG. Yes.

  Two power supply lines 205 arranged adjacent to each other are connected to each other to form a ladder shape and surround the photodiodes 101 belonging to one column. Two substrate contact wirings 212 arranged adjacent to each other are also connected to each other to form a ladder shape and surround each photodiode 101 belonging to one column. The columns of the photodiodes 101 surrounded by the power supply line 205 and the columns of the photodiodes 101 surrounded by the substrate contact wiring 212 are alternately arranged. Two vertical signal lines 206 provided in the second metal wiring layer are arranged so as to surround the photodiodes 101 in each column as a pair, but the vertical signal lines 206 are connected to each other. Therefore, a space having the minimum width in the manufacturing process is formed between the vertical signal lines 206 adjacent to each other. In the example shown in FIGS. 9A to 9C, this space is arranged on the center line of the photodiode 101 extending in the column direction.

  In the solid-state imaging device of the present embodiment, since the substrate contact wiring 212 connected to the substrate contact region provided for each cell 250 is provided as in the solid-state imaging device shown in FIG. The substrate potential of the transistor provided in the transistor can be stabilized, and the response speed of the transistor can be improved.

  In addition, the vertical signal line 206 provided in the second metal wiring layer surrounds each photodiode 101 so that light from the adjacent cell 250 is difficult to enter. Light shielding is not complete because a gap is formed between adjacent vertical signal lines 206, but in order to compensate for this, the power supply line 205 and the substrate contact wiring 212 surround the photodiode 101 without a gap. As a result, the light is more reliably shielded, and the occurrence of color mixing can be prevented more reliably. In addition, since the incident characteristics of the light to each photodiode 101 are uniform, the characteristics of the photodiode 101 are uniform. When a certain amount of color mixture is allowed, the power supply line 205 and the substrate contact wiring 212 may be linear.

  Further, since the vertical signal line 206 is arranged in the second metal wiring layer, the capacitance generated between the vertical signal line 206 and the FD wiring 135 is reduced as compared with the case where the vertical signal line 206 is arranged in the first metal wiring layer. Therefore, it is possible to suppress variations in parasitic capacitance among the cells 250 and more effectively suppress the occurrence of shading.

  Note that the substrate contact regions disposed on both sides of the photodiode 201 are also preferably disposed so as to be symmetrical to each other in the row direction when viewed from the photodiode 201. In this case, the stress applied to the photodiode 201 from the left direction in FIG. 9 can be made substantially equal to the stress applied to the photodiode 201 from the right direction, and the photoelectric conversion characteristics in the plane of the photodiode 201 are obtained. Can be made uniform.

  In the solid-state imaging device of this embodiment, the substrate contact region and the substrate contact wiring 212 are provided. However, as described above, the substrate contact wiring 212 may not be provided.

  In the solid-state imaging device according to the present embodiment, a light-shielding pixel region (so-called OB region) whose entire upper portion is covered with a light-shielding layer made of metal may be provided in the pixel array 500. In this case, the power supply line 205 may be disposed in the second metal wiring layer and the vertical signal line 206 may be disposed in the first metal wiring layer in the light-shielding pixel region. Further, in this case, there is a wiring layer transfer region for changing the wiring layer in which the wiring is provided between the light-shielding pixel region and the region (effective pixel region) having the configuration shown in FIGS. Preferably they are arranged.

(Third embodiment)
FIGS. 11A to 11C are plan views showing the layout of the pixel array of the solid-state imaging device according to the third embodiment of the present invention. FIG. 11A shows a polysilicon wiring layer and contacts for connecting the diffusion layer or polysilicon wiring formed on the semiconductor substrate and the wiring of the first metal wiring layer in the pixel array. (b) shows the wiring formed in the first metal wiring layer in addition to the configuration shown in (a), and the contact connecting the first metal wiring layer and the second metal wiring layer. c) further shows the wiring formed in the second metal wiring layer in addition to the configuration shown in (b).

  The solid-state imaging device according to the present embodiment differs from the solid-state imaging devices according to the first and second embodiments in a part of the wiring layout. That is, the cell 350 in the solid-state imaging device of this embodiment includes a photodiode 301, an FD 330, a transfer transistor 302 having a gate electrode connected to the transfer gate wiring 308, and a gate electrode connected to the reset gate wiring 307. The reset transistor 304 includes an amplification transistor 303, a gate wiring 309 of the amplification transistor 303, and an FD wiring 335. Since the circuit configuration in the pixel array 600 and the function of each component are basically the same as those of the solid-state imaging device of the first embodiment, description thereof is omitted.

  The solid-state imaging device of the present embodiment is characterized in that the gate wiring 309 does not bypass the contact, and the FD wiring 335 formed in the first metal wiring layer is routed so as to bypass the contact. The vertical signal line 306 is disposed in one metal wiring layer, and the power supply line 305 is disposed in the second metal wiring layer. The power supply line 305 has a grid shape, for example, and functions as a light shielding layer surrounding the photodiode 301 in each cell. Further, the substrate contact wiring is not formed on the pixel array.

  In the solid-state imaging device according to the present embodiment, gate wirings adjacent to both sides of the photodiode 301 are arranged at positions symmetrical to each other in the row direction when viewed from the photodiode 301. The vertical signal line 306 and the FD wiring 335 adjacent to both sides of the photodiode 301 are also arranged at positions symmetrical to each other in the row direction when viewed from the photodiode 301. As a result, variations in the incident characteristics of light in each photodiode 301 can be suppressed.

  In addition, since the power supply line 305 is formed in a lattice shape surrounding each photodiode 301 and functions as a light shielding layer, the vertical signal line 306 does not necessarily need to surround the photodiode 301. As shown in FIGS. 11A to 11C, the vertical signal line 306 is formed in a straight line when the solid-state imaging device needs to be miniaturized even if a certain amount of color mixture is allowed.

  As described above, the solid-state imaging device according to the present embodiment can suppress color mixing and shading and can be miniaturized.

(Fourth embodiment)
FIG. 12 is a circuit diagram showing a part of a pixel array of a solid-state imaging device according to the fourth embodiment of the present invention. In this embodiment, a solid-state imaging device in which two pixels (that is, two photodiodes) are included in one cell will be described as an example of a so-called multi-pixel one-cell solid-state imaging device.

  As shown in FIG. 12, in the solid-state imaging device according to the present embodiment, the cell includes a first photodiode 501a and a second photodiode 501b that store an amount of charge corresponding to the intensity of received light, and a first photodiode. The first FD 530a, the second FD 530b, and the first transfer gate wiring 508a (see FIG. 13) to which the charges accumulated by the photodiode 501a and the second photodiode 501b are transferred, respectively, are controlled. The second transfer gate wiring 508b (see FIG. 13) controls the charge transfer from the photodiode 501a to the first FD 530a and the second transfer gate wiring 508b. A second transfer transistor 502b for controlling the transfer of electric charge to the FD 530b, and a reset gate The reset transistor 504, which is controlled by the wiring 507 (see FIG. 13) and initializes the potentials of the first FD 530a and the second FD 530b, the gate electrode to the first FD 530a and the second FD 530b, and the drain to the power supply line 505 , The source is connected to the vertical signal line 506, and the amplification transistor 503 constituting the source follower is provided between the source of the amplification transistor 503 and the vertical signal line 506, and the output signal from the amplification transistor 503 is sent to the vertical signal line A selection transistor 520 to be transmitted to 506 and a substrate contact wiring 512 (see FIG. 13) connected to a substrate contact region containing p-type impurities formed on the substrate are provided. At least one substrate contact region is formed per cell.

  In the solid-state imaging device of this embodiment, two sets of photodiodes and transfer transistors connected to the photodiodes are formed in one cell. Note that three or more pairs of photodiodes and transfer transistors connected to the photodiodes may be formed. Further, the first FD 530a and the second FD 530b are provided in one cell, but one FD may be shared by a plurality of photodiodes in the cell. In addition, the reset transistor 504, the amplification transistor 503, the selection transistor 520, and the like can be shared by a plurality of photodiodes. In the pixel array of this embodiment, a plurality of cells are arranged in a matrix and a plurality of photodiodes are also arranged in a matrix.

  FIGS. 13A to 13C are plan views showing the layout of the effective pixel area of the solid-state imaging device according to the fourth embodiment. FIG. 13A shows a polysilicon wiring layer and contacts for connecting the diffusion layer or polysilicon wiring formed on the semiconductor substrate and the wiring of the first metal wiring layer in the pixel array. (b) shows the wiring formed in the first metal wiring layer in addition to the configuration shown in (a), and the contact connecting the first metal wiring layer and the second metal wiring layer. c) further shows the wiring formed in the second metal wiring layer in addition to the configuration shown in (b). Note that broken lines in FIGS. 13A to 13C indicate cell divisions. Although FIG. 13 shows only a part of the pixel array, the same configuration as that shown in FIG. 13 is actually repeated in both the row direction and the column direction.

  In the solid-state imaging device of the present embodiment, since two photodiodes (first photodiode 501a and second photodiode 501b) are provided in one cell, the unit area of the imaging region (pixel array) Of these, the proportion of the area occupied by the photodiode can be increased. For this reason, the sensitivity and saturation characteristics of the photodiode can be improved.

  In the solid-state imaging device of the present embodiment, the FD wiring 535 and the power supply line 505 are arranged in the first metal wiring layer above the pixel array. The vertical signal line 506 is disposed in the second metal wiring layer formed above the first metal wiring layer. Therefore, even when the oblique incident characteristics of light are improved by shifting the position of the vertical signal line 506 in accordance with the distance from the center line of the pixel array, variation in parasitic capacitance generated in the cell is suppressed, and shading is prevented. Occurrence can be suppressed.

  Further, in the solid-state imaging device of the present embodiment, when attention is paid to one photodiode, the row direction of the photodiode in the metal wiring arranged in the first metal wiring layer or the second metal wiring layer (FIG. 13). The portions adjacent to both sides in the left-right direction in FIG. With this configuration, the light incident from the left side and the light incident from the right side are equalized in each photodiode, so that variations in sensitivity within the surface of the photodiode can be suppressed, and shading can be effectively suppressed. It becomes possible. The gate wiring of the reset transistor 504 may have the same shape for each cell as shown in FIG. 13A, but the gate wirings adjacent to each other in the row direction of the photodiodes are viewed from the photodiode side. They may be arranged symmetrically in the direction.

  In addition, two power supply lines 506 arranged in the first metal wiring layer form a ladder shape, and surround each of the photodiodes arranged in one column. Similarly to the power supply line 506, the substrate contact wirings 512 arranged in the first metal wiring layer form a set of two ladders and surround the respective photodiodes arranged in one row. On the other hand, the vertical signal lines 506 arranged in the second metal wiring layer are provided for each column of photodiodes (or cells) and extend on a straight line. With this configuration, of the light collected by the microlens arranged above each photodiode to increase the light collection efficiency, the light that should originally reach the photodiode is the uppermost metal wiring layer (here, the first metal wiring layer). 2 is difficult to block by the wiring arranged in the metal wiring layer 2). Therefore, the sensitivity and saturation characteristics of the photodiode can be improved as compared with the case where the vertical signal line 506 arranged in the uppermost metal wiring layer surrounds the photodiode. In the solid-state imaging device according to the present embodiment, the columns of photodiodes surrounded by the power supply line 506 and the columns of photodiodes surrounded by the substrate contact wiring 512 are alternately arranged.

  In the solid-state imaging device of this embodiment, a substrate contact region is formed for each cell on the substrate on which the pixel array is provided. Therefore, the operation of the transistors formed in the pixel array can be stabilized and the signal reading speed can be improved.

  In addition, the power supply line 505 for supplying a pulsed power supply voltage is connected to the drain of the reset transistor 504 so as to function as a reset power supply, thereby simplifying the wiring layout and increasing the opening area of the photodiode. It becomes possible.

  Further, in the solid-state imaging device of the present embodiment, as shown in FIG. 13C, the power supply line 505 and the vertical signal line 506 are arranged at substantially parallel positions with an interlayer insulating film interposed therebetween. Further, the power supply line 505 and the vertical signal line 506 are arranged so as not to overlap as much as possible in plan view. With this configuration, a signal propagating through the vertical signal line 506 is less affected by noise from the power supply line 505.

  Further, the FD wiring 535 that connects the FD and the gate electrode of the amplification transistor 503 is disposed at a position substantially parallel to the power supply line 505. With this configuration, the charge accumulated in the FD wiring 535 is less affected by noise from the power supply line 505.

  The solid-state imaging device according to the present invention can be used in various imaging devices such as an imaging device having a large number of pixels such as a single-lens reflex digital camera and an HD movie, and a portable imaging device.

(A)-(c) is a top view which shows the layout of the pixel array of the solid-state imaging device which concerns on the 1st Embodiment of this invention which is a MOS type solid-state imaging device. It is sectional drawing between the II-II lines shown to Fig.1 (a)-(c) of the solid-state imaging device which concerns on 1st Embodiment. It is a circuit diagram which shows the cell in the solid-state imaging device which concerns on 1st Embodiment. It is a figure which shows schematically the structure of the pixel array and its peripheral circuit in the solid-state imaging device which concerns on 1st Embodiment. It is a top view which shows the layout of the pixel array of the solid-state imaging device which concerns on the 1st modification of 1st Embodiment. It is a top view which shows the layout of the pixel array of the solid-state imaging device which concerns on the 2nd modification of 1st Embodiment. It is a top view which shows the layout of the pixel array of the solid-state imaging device which concerns on the 3rd modification of 1st Embodiment. (A)-(c) is a top view which shows the layout of the pixel array of the solid-state imaging device which concerns on the 4th modification of 1st Embodiment. (A)-(c) is a top view which shows the layout of the pixel array of the solid-state imaging device concerning the 2nd Embodiment of this invention. It is sectional drawing between the XX lines shown to Fig.9 (a)-(c) of the solid-state imaging device concerning 2nd Embodiment. (A)-(c) is a top view which shows the layout of the pixel array of the solid-state imaging device concerning the 3rd Embodiment of this invention. It is a circuit diagram which shows a part of pixel array of the solid-state imaging device concerning the 4th Embodiment of this invention. (A)-(c) is a top view which shows the layout of the effective pixel area | region of the solid-state imaging device which concerns on 4th Embodiment. (A)-(c) is a top view which shows the cell of the conventional MOS type solid-state imaging device. It is a figure which shows the cross section in the VIII-VIII line shown in FIG. 14 of the conventional solid-state imaging device. It is a figure which shows schematically the pixel array of the conventional solid-state imaging device. It is a schematic diagram which shows another example of the pixel array of the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 20 Active area | region 30 Element isolation area | region 40 Color filter 50 Micro lens 101,101 ', 101'',201,201', 201 '', 301 Photodiode 102,202,302 Transfer transistor 103,203,303, 503 Amplification transistor 104, 204, 304, 504 Reset transistor 105, 205, 305, 505 Power supply line 105a, 105b Branch portion 106, 106 ′, 106 ″, 206, 206 ′, 206 ″, 306, 506 Vertical signal line 106-1, 106′-1 Branch portions 107, 207, 307, 507 Reset gate wirings 108, 208, 308 Transfer gate wirings 109, 109 ″, 209, 209 ″, 309 Gate wirings 110, 111 Spaces 112, 212 512 Substrate contact wiring 13 , 230,330 FD
135, 235, 335, 535 FD wiring 150, 250, 350 Cell 400, 500, 600 Pixel array 401 Vertical shift register 402 Noise suppression circuit 403 Horizontal shift register 404, 520 Selection transistor 405 Horizontal signal line 501a First photodiode 501b Second photodiode 530a First FD
530b second FD
508a First transfer gate line 508b Second transfer gate line 502a First transfer transistor 502b Second transfer transistor

Claims (26)

A photodiode that accumulates an amount of charge according to the intensity of received light, a floating diffusion to which the charge accumulated by the photodiode is transferred, and a transfer that controls the transfer of charge from the photodiode to the floating diffusion A pixel array in which a transistor and an amplification transistor from which a signal corresponding to the charge transferred to the floating diffusion is read from a source are provided, and a plurality of cells are arranged on a substrate;
Metal wiring provided above the pixel array,
At least one of the photodiode and the transfer transistor is disposed in the cell,
In the pixel array, the photodiodes are arranged in a matrix,
2. The solid-state imaging device according to claim 1, wherein portions of the metal wiring located on both sides in the row direction of the photodiodes are symmetrical to each other in the row direction when viewed from the photodiode. The metal wiring is composed of a plurality of wirings,
In the pixel column adjacent to the plurality of wirings, the layout of the metal wiring viewed from the photodiode in each of the adjacent pixel columns is symmetrical in the row direction by changing the arrangement order of the plurality of wirings in the row direction. The solid-state imaging device according to claim 1, wherein the metal wiring is arranged so as to be. The metal wiring is connected to the drain of the amplification transistor and extends in the row direction, and is connected to the source of the amplification transistor and is provided for each column of the photodiodes and extends in the row direction. Have
The portions of the power supply line located on both sides in the row direction of the photodiodes are symmetrical to each other in the row direction as viewed from the photodiodes.
The portion of each of the vertical signal lines located on both sides of each of the photodiodes in the row direction is symmetrical to each other in the row direction as viewed from the photodiode. Solid-state imaging device. The power supply line is provided for each column of the photodiodes,
The power supply line and the vertical signal line are both disposed in the first metal wiring layer,
The photodiode rows sandwiched between two mutually adjacent power supply lines and the photodiode columns sandwiched between two mutually adjacent vertical signal lines are alternately arranged. The solid-state imaging device according to claim 3.   5. The two adjacent vertical signal lines each have a branch portion for surrounding the photodiode, and are arranged with a space between each other. Solid-state imaging device. The photodiode has a corner,
6. The solid-state imaging device according to claim 5, wherein a space formed between the two adjacent vertical signal lines is arranged at a corner position of the photodiode when seen in a plan view.   Of the two adjacent vertical signal lines, a branch portion of one vertical signal line and a branch portion of the other vertical signal line are alternately arranged in the column direction with the photodiode interposed therebetween. The solid-state imaging device according to claim 5 or 6. Each of the two adjacent power lines is opposed to each other, and has a branching portion for surrounding the photodiode.
Bifurcated portions of the two adjacent power supply lines are opposed to each other with a planar overlap with a center line extending in the column direction of the photodiodes,
The solid-state imaging device according to claim 5, wherein a space between the two adjacent vertical signal lines is formed in a region overlapping with a center line extending in a column direction of the photodiodes in a plane.   9. The solid-state imaging device according to claim 5, wherein the two adjacent vertical signal lines are arranged with a space having a minimum width in a manufacturing process.   8. The solid-state imaging device according to claim 4, wherein the two adjacent power supply lines are connected to each other to form a ladder shape and surround the photodiode. 8. .   The metal wiring is further connected to the substrate and disposed on a second metal wiring layer provided above the first metal wiring layer, and further includes a substrate contact wiring surrounding each of the photodiodes. The solid-state imaging device according to claim 4, wherein the solid-state imaging device is provided.   The solid-state imaging device according to claim 11, wherein a substrate contact region disposed on each of the cells and connected to the substrate contact wiring is formed on the substrate. The power supply line is provided for each column of the photodiodes, and is disposed in the first metal wiring layer.
The vertical signal line is disposed in a second metal wiring layer provided above the first metal wiring layer,
The metal wiring is further connected to the substrate, and further includes a substrate contact wiring arranged in the first metal wiring layer for each column of the photodiodes,
The photodiode columns sandwiched between two mutually adjacent power supply lines and the photodiode columns sandwiched between two mutually adjacent substrate contact wirings are alternately arranged. The solid-state imaging device according to claim 3. The two adjacent power lines are connected to each other to form a ladder, and surround the photodiode.
The solid-state imaging device according to claim 13, wherein the two adjacent substrate contact wirings are connected to each other to form a ladder shape and surround the photodiode.   The vertical signal lines each have a branch portion for surrounding the photodiode, and are arranged with a space between adjacent vertical signal lines. Item 15. The solid-state imaging device according to Item 13 or 14. The planar shape of the photodiode is a quadrilateral shape,
The solid-state imaging device according to claim 15, wherein the space formed between the vertical signal lines is arranged at a corner of the photodiode when seen in a plan view.   The solid-state imaging device according to claim 15, wherein the space formed between the vertical signal lines is formed in a region overlapping with a center line extending in the column direction of each of the photodiodes.   The solid-state imaging device according to claim 13, wherein a substrate contact region connected to the substrate contact wiring is formed for each of the cells on the substrate. The vertical signal line is disposed in the first metal wiring layer,
4. The solid according to claim 3, wherein the power supply line is disposed in a second metal wiring layer provided above the first metal wiring layer and surrounds each of the photodiodes. Imaging device. On the substrate, the gate wiring of the amplification transistor is provided for each cell,
The gate wirings arranged on both sides in the row direction of the photodiodes are symmetrical with each other in the row direction as viewed from the photodiodes. Solid-state imaging device. On the substrate, a diffusion layer serving as a source and a drain of the amplification transistor is provided for each cell.
21. The diffusion layer disposed on both sides of the photodiode in the row direction is symmetrical to each other in the row direction when viewed from the photodiode. Solid-state imaging device.   The pixel array according to any one of claims 1 to 21, further comprising reset means connected to the floating diffusion and for initializing the state of the floating diffusion. Solid-state imaging device.   The plurality of pairs of the photodiode and the transfer transistor connected to the photodiode are provided in each of the plurality of cells. Solid-state imaging device.   The photodiode, the transfer transistor, the floating diffusion, and the amplification transistor are each formed in each of the plurality of cells. The solid-state imaging device described. A photodiode that accumulates an amount of charge according to the intensity of received light, a floating diffusion to which the charge accumulated by the photodiode is transferred, and a transfer that controls the transfer of charge from the photodiode to the floating diffusion A pixel array in which a transistor, an amplification transistor from which a signal corresponding to the charge transferred to the floating diffusion is read from a source, a gate wiring of the amplification transistor, and a plurality of cells are arranged on a substrate;
Metal wiring provided above the pixel array,
At least one of the photodiode and the transfer transistor is disposed in the cell,
In the pixel array, the photodiodes are arranged in a matrix,
The solid-state imaging device, wherein the gate wirings arranged on both sides of the photodiode in the row direction are symmetrical to each other in the row direction when viewed from the photodiode. A photodiode that accumulates an amount of charge according to the intensity of received light, a floating diffusion to which the charge accumulated by the photodiode is transferred, and a transfer that controls the transfer of charge from the photodiode to the floating diffusion A pixel array in which a transistor, an amplification transistor from which a signal corresponding to the charge transferred to the floating diffusion is read from a source, a gate wiring of the amplification transistor, and a plurality of cells are arranged on a substrate;
Metal wiring provided above the pixel array,
At least one of the photodiode and the transfer transistor is disposed in the cell,
In the pixel array, the photodiodes are arranged in a matrix,
On the substrate, a diffusion layer serving as a source and a drain of the amplification transistor is provided for each cell.
The solid-state imaging device, wherein the diffusion layers arranged on both sides of the photodiode in the row direction are symmetrical to each other in the row direction when viewed from the photodiode.

Images