JP2009206941A - Image pickup device and image pickup system using image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify the correction of pixels in which well contact is arranged, and to reduce a linear noise. <P>SOLUTION: In an amplification type image pickup device where well contact is arranged in each of a plurality of pixels, second wiring is arranged in second pixels which are adjacent to first pixels having well contact to which a voltage is supplied by first wiring, where any well contact is not arranged. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an amplification type imaging apparatus having a well contact.

  Imaging devices are used in many image input devices such as digital cameras. Representative types of the imaging device include a CCD type and a MOS type.

Patent Document 1 discloses a technique in which a plurality of well contacts for supplying a reference voltage to a well are provided inside a pixel array area in order to reduce shading that occurs in an output signal in a MOS imaging device. .
JP 2001-230400 A

  However, when the pixels are miniaturized in the configuration described in Patent Document 1, an area for providing a well contact is required, so that the area of the photoelectric conversion element is reduced and sensitivity is lowered.

  In order to suppress such a decrease in sensitivity, there is a method of providing a well contact in one pixel among a plurality of pixels. However, in this method, it is necessary to perform correction, for example, the sensitivity of a pixel provided with a well contact is lower than that of another pixel.

  At this time, the pixels in the pixel column or the pixel row in which the wiring for supplying a voltage to the well contact is arranged have a different sensitivity from the pixels in the pixel column or the pixel row in which no wiring is arranged, because the capacitance of the amplification unit is different. End up. It is difficult to correct a pixel provided with a well contact using pixels having such different sensitivities.

  Also, if the sensitivity of a pixel column or pixel row where a wiring for supplying a voltage to the well contact is arranged is different from that of a pixel column or pixel row where no wiring is arranged, the output step becomes linear. May appear as noise.

  In addition, since the number of wirings varies depending on the pixel column or the pixel row, the opening of the photoelectric conversion element may vary depending on the pixel column or the pixel row.

  Accordingly, an object of the present invention is to facilitate correction of a pixel provided with a well contact in an imaging device in which a well contact is provided for one pixel for a plurality of pixels. Another object is to reduce linear noise. Another object is to make the apertures of the pixels uniform.

  The present invention is an imaging apparatus having a pixel region in which pixels including one photoelectric conversion element are two-dimensionally arranged, and a plurality of color filters in which one color is arranged corresponding to each pixel. A floating diffusion region to which charges generated in the photoelectric conversion element are transferred, an amplification MOS transistor that outputs a signal based on a potential of the floating diffusion region, a first pixel in which a well contact is disposed, A first wiring that is electrically connected to the well contact and that is supplied with a first voltage, the first wiring being arranged in a first pixel column including the first pixel, A second pixel included in a second pixel column different from the first pixel column, in which a color filter of the same color is disposed and the well contact is not disposed, and the second pixel column And a second wiring.

  Further, the present invention is an imaging device having a pixel region in which one pixel including one photoelectric conversion element is two-dimensionally arranged, and a floating diffusion region to which charges generated in the photoelectric conversion element are transferred; An amplifying MOS transistor that outputs a signal based on the potential of the floating diffusion region, a first pixel provided with a well contact, and a first pixel column including the first pixel are electrically connected to the well contact. And a first wiring to which a first voltage is supplied, and is included in a second pixel column different from the first pixel column and adjacent to the first pixel. It has a second pixel in which the well contact is not arranged, and a second wiring arranged in the second pixel column.

  According to the present invention, it becomes easy to correct a pixel in which a well contact is arranged. In addition, linear noise can be reduced. In addition, the pixel openings can be made uniform.

  In the amplification type imaging device, the first pixel having a well contact to which a voltage is supplied by the first wiring, and the second pixel having no well contact adjacent to the first pixel are provided. The second wiring is arranged. As described above, by arranging the second wiring also in the second pixel, the difference in the coupling effect due to the wiring of the first pixel and the second pixel is reduced. Therefore, the output difference between the first pixel and the second pixel due to the wiring becomes small, and the correction of the first pixel becomes easy. Further, the output step between the first pixel column including the first pixel and the second pixel column including the second pixel is reduced, and the linear output step can be reduced. Further, the openings of the first pixel column and the second pixel column are uniform.

  Here, the pixel is a minimum unit corresponding to one photoelectric conversion element, and is an area periodically divided. An area in which a plurality of pixels are two-dimensionally arranged is referred to as a pixel area. Note that a transistor or the like for reading out charges from the photoelectric conversion element may be shared by the two photoelectric conversion elements, and thus may be arranged over the pixels.

  A well contact is a contact provided to reduce fluctuations in a well serving as a base of a pixel or a well of an element having an amplification function. The element having an amplification function is, for example, an amplification MOS transistor. If the potential of the well of the amplification MOS transistor differs depending on the location of the pixel region, the output of the amplification MOS transistor may vary. A voltage supply structure provided to fix the potential of the well is referred to as a well contact. Here, the well of the amplification MOS transistor may be formed of a uniform semiconductor region in which the source and the drain are formed, or may be formed of a partial semiconductor region such as a potential barrier under the gate electrode.

  Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1A is a conceptual diagram of a pixel region, and shows an array of 2.16 million pixels in which, for example, 1800 pixels × 1200 pixels are arrayed. Reference numeral 101 denotes an array of 200 pixels × 200 pixels, and each well 101 has one well contact. Reference numeral 102 denotes a well fixing region arranged on the outer periphery of the pixel region for fixing the potential of the well in the pixel region.

  FIG. 1B is a schematic plan view in which a range including a pixel having a well contact of a part 101 in FIG. 1A is enlarged, and shows an array of 5 pixels × 5 pixels. Although illustration and description are omitted for the sake of simplicity except for the specific wiring, it is assumed that they are similarly arranged for each pixel. The x direction in FIG. 1B is the pixel row direction, and the y direction is the pixel column direction.

  Reference numerals 1-1 to 5-5 denote pixels. For example, 1-1 means a pixel in the first column of the first row, and the outer edge of the pixel is indicated by 108. The image pickup apparatus of the present embodiment has a Bayer color filter, and reference numeral B in FIG. 1B is a pixel corresponding to a blue color filter, reference numerals Gr and Gb are green, and reference numeral R is a red color filter. It is shown that. Hereinafter, for simplicity, they are referred to as a blue pixel, a green pixel, and a red pixel. Reference numeral 110 denotes a well contact, and reference numeral 3-3 denotes a first pixel in which the well contact is arranged. The configuration of each pixel will be described in detail later with reference to FIG. Reference numeral 105 in FIG. 1B denotes a first wiring to which a first voltage is supplied, which is electrically connected to the well contact of the first pixel. In the present embodiment, the first voltage is GND, and the well can be fixed to GND. By providing this well contact, the light receiving area of the photoelectric conversion element of the first pixel is reduced, and characteristics such as sensitivity and saturation charge amount are deteriorated. Therefore, correction of the first pixel is necessary.

  A pixel that can be used for the correction of the first pixel is a second pixel. For the second pixel, it is desirable to use an adjacent pixel having characteristics as close as possible to the first pixel. In the present embodiment, the second pixel is an adjacent pixel of the same color arranged in the same pixel row as the first pixel. Specifically, the pixels that can be the second pixel with respect to the first pixel 3-3 are the pixels 3-1 and 3-5. If the first pixel is the pixel 2-3, the pixels that can be the second pixel are the pixels 2-1 and 2-5. One or a plurality of the second pixels may be provided. In addition, since the second pixel is used for correcting the first pixel, it is desirable that no well contact is disposed.

  In the present embodiment, in order to bring the characteristics of the second pixel closer to those of the first pixel, a second wiring is provided in the second pixel. The second wiring is 103, 107, for example. The voltage supplied to the first wiring is supplied to the second wiring. By providing the second wiring in the second pixel in this manner, the influence of the first wiring on the first pixel, for example, the influence of capacitive coupling can be similarly applied to the second pixel. Become. Therefore, it is possible to reduce the characteristic difference between the first pixel and the second pixel.

  In the present embodiment, the second wiring is arranged in addition to the pixel column including the second pixel. With such a configuration, it is possible to make the output difference between the first pixel column, the second pixel column, and the other pixel columns less noticeable. In addition, the pixel openings can be made uniform.

  Next, a change in capacitance due to wiring will be described while explaining the configuration of the pixel with reference to FIG. FIG. 2 is a diagram in which the four pixels 3-1, 3-3, 5-1, and 5-3 in FIG. 1B are extracted. FIG. 2A is a schematic plan view enlarging the four pixels, and FIG. 2B is an equivalent circuit diagram corresponding thereto. The MOS transistors in FIG. 2 are all N-type, and are turned on when the gate electrode becomes Hi level by the drive wirings PRES3, PTX3, PSEL3, PRES5s, PTX5, and PSEL5. Here, in FIG. 2A, wirings in a specific direction are illustrated as in FIG. 1, and other wirings are omitted.

  2A and 2B, 201 is a photoelectric conversion element, 202 is a transfer MOS transistor, 203 is a reset MOS transistor, 204 is an amplification MOS transistor, and 205 is a selection MOS transistor. The amplification MOS transistor 204 forms a source follower circuit. Reference numeral 206 denotes a semiconductor region, and reference numeral 207 denotes a connection wiring for connecting the gate electrode of the amplification MOS transistor and the semiconductor region 206. Charge is transferred from the photoelectric conversion element 201 to the semiconductor region 206 by the transfer MOS transistor, and a signal based on the charge is output to the signal line V1 or V2 via the amplification MOS transistor 204 and the selection MOS transistor. The reset MOS transistor 203 resets the input stage of the amplification MOS transistor 204 (operation for setting to a predetermined potential). The portion of the node that is the same as the gate electrode of the amplification MOS transistor 204 is an input stage of the source follower circuit. Specifically, the input stage includes the gate electrode of the amplification MOS transistor 204, the semiconductor region 206, the drains of the transfer MOS transistor and the reset MOS transistor, the semiconductor region 206, the connection wiring 207, and the like.

  Here, the semiconductor region 206 is a charge conversion unit that converts the charge of the photoelectric conversion element 201 into a voltage, and is also referred to as a floating diffusion region (hereinafter referred to as an FD region). During this charge-voltage conversion, the capacitance of the semiconductor region 206 determines the charge-voltage conversion efficiency. Therefore, the change in the capacitance of the semiconductor region 206 changes the efficiency, which causes a change in the output signal.

Specifically, when a signal generated in the photoelectric conversion element 201 is read out to the semiconductor region 206 via the transfer MOS transistor 202, the voltage change ΔV of the semiconductor region 206 is a capacitance (FD region capacitance) of the semiconductor region 206. When C _fd is set, ΔV = Q / C _fd . Then, the voltage change ΔV is output as a signal to the signal line V1 or V2 via the amplification MOS transistor 204. Therefore, the voltage change ΔV is changed by the capacitance C _fd even with the same charge amount.

Here, the semiconductor region 206 is connected to the gate electrode of the amplification MOS transistor, the drain of the transfer MOS transistor and the reset MOS transistor, and the connection wiring 207 between the semiconductor region 206 and the gate electrode of the amplification MOS transistor. Therefore, the capacitance C _fd of the semiconductor region 206 includes the capacitance of the gate electrode of the amplification MOS transistor, the drain of the transfer MOS transistor and the reset MOS transistor, and the connection wiring 207. Further, the capacitance C _fd includes a coupling capacitance between these elements and a wiring arranged on the upper portion thereof. In particular, the case where the upper part is not directly above is included. That is, the capacitance C _fd changes depending on the presence or absence of the wiring, and the output capacitance also changes.

Therefore, the second wiring 103 is arranged in the second pixel column included in the second pixel, for example, the pixel 3-1, corresponding to the first wiring 105 arranged in the first pixel 3-3. With such a configuration, it is possible to reduce the difference in capacitance C _fd due to the coupling between the wiring of the first pixel and the second pixel.

  Here, if the coupling capacitance is simply made uniform, the first wiring 105 and the second wiring 103 may be connected to different power supply voltages. However, the wiring potential fluctuates due to noise, clocks, etc., and the fluctuation amount and recovery time vary depending on the original wiring potential. Therefore, the second wiring 103 is preferably a wiring to which the same voltage as that of the first wiring 105 is supplied.

  As described above, the first voltage having the same color as that of the first pixel and the same first voltage as that of the first wiring is supplied onto the second pixel in the same pixel row as the first pixel. By having two wirings, the output difference between the first pixel and the second pixel can be suppressed, and correction can be made easier.

  In the present embodiment, the description has been made using only the pixel 3-1 as the second pixel used for the correction, but the pixel 3-5 may be used in order to increase the accuracy of the correction.

  Here, a pixel in the same pixel row as the first pixel is a second pixel, but a pixel in a different pixel row may be used. However, in the case of an imaging device that reads out a signal for each pixel row, a memory for holding the signal is required, and the circuit scale increases. Therefore, in the case of such an imaging device, it is preferable that the first pixel and the second pixel are in the same pixel row.

  In addition, the coupling capacitance of the wiring is maximized particularly when the wiring is arranged immediately above the element. Specifically, when the wiring is arranged on the gate electrode of the amplification MOS transistor or on the connection wiring 207, the influence of the coupling becomes large because the wiring is closest to the element. Therefore, when the first wiring is arranged on the gate electrode of the amplification MOS transistor, it is more preferable to arrange the second wiring.

  Further, the imaging device may include a light-shielded pixel that is shielded by a light-shielding film for obtaining a reference signal, and a well contact that is supplied with a voltage by a second wiring may be disposed on the light-shielded pixel. In the case of a light-shielding pixel, even if the light receiving area of the photoelectric conversion element is reduced due to the well contact, the well contact may be provided because the image is not greatly affected.

  Further, even when the first pixel is not corrected, the second wiring may be arranged in the second pixel. It is possible to reduce linear noise due to an output step, an uneven opening, or the like caused by arranging the first wiring only in the first pixel column.

  In the present embodiment, the second wiring is arranged in addition to the second pixel column including the second pixel. With such a configuration, it is possible to make the output difference between not only the first pixel column but also the second pixel column and the other pixel columns inconspicuous. Therefore, linear noise can be further reduced.

(Second Embodiment)
A second embodiment will be described with reference to FIG. FIG. 3A is a schematic plan view of a pixel region, and FIG. 3B shows a pixel circuit. 3A corresponds to FIG. 1B illustrating the first embodiment, FIG. 3B corresponds to FIG. 2B, and common elements are denoted by the same reference numerals and described. Is omitted.

  This embodiment is different from the first embodiment in that a third pixel between a first pixel column including the first pixel 3-3 and a second pixel column including the second pixel 3-1. The third wiring 301 is arranged in the third pixel column including the second pixel 3-2. A second voltage different from the first voltage is supplied to the third wiring. In FIG. 1B, the third wiring is omitted and arranged in each pixel column (each pixel) (not shown), but in this embodiment, the third wiring is shared by the two pixel columns. . With such a configuration, the number of wirings necessary for each pixel column can be reduced. By reducing the number of wirings, the degree of freedom of wiring layout is improved and the opening of the photoelectric conversion element can be widened, so that the incident efficiency to the photoelectric conversion element can be improved. In addition, the pixel openings can be made uniform.

  FIG. 3B shows an equivalent circuit. FIG. 3B is a circuit diagram in which the pixels 3-2, 3-3, 2-2, and 2-3 in FIG. 3A are extracted. By having the wiring 303, a voltage is supplied from the third wiring VDD (301) arranged along the pixel column having the pixel 3-2 to the pixel column having the pixel 3-3 (FIG. 3A). (Not shown). The third wiring supplies, for example, a power supply voltage (VDD) which is a driving voltage of the amplification MOS transistor constituting the source follower circuit and a reset voltage for resetting the input portion of the amplification MOS transistor.

  Here, since the voltages supplied to the first wiring, the second wiring, and the third wiring are different, there is a possibility that the amount of fluctuation in the wiring potential due to noise or the time for returning to the original potential may be different. . However, the first wiring 103 and the second wirings 105 and 107 are arranged in the pixels 3-1, 3-3, and 3-5 corresponding to red, and the pixels 3-2, 3 and 3 corresponding to blue are arranged. -3 is provided with third wirings 301 and 302. That is, the same color pixel is provided with a wiring to which the same voltage is supplied. Therefore, even when the pixel 3-3 is corrected using the pixel 3-1 or the pixel 3-5, the correction can be easily performed.

(Third embodiment)
A third embodiment will be described with reference to FIG. FIG. 4 is a schematic plan view of a pixel region similar to FIG. The difference of this embodiment from the first embodiment is that the first wiring 105 is arranged in the pixel row direction. As in this embodiment, the row direction and the column direction may be interchanged from those in the first embodiment.

  Here, when the first wiring 105 is in the pixel row direction, the correction of the first pixel 3-3 can be performed using the pixel 3-1 and the pixel 3-5 in the same pixel row. However, in the state where only the first wiring 105 is arranged, the output of the pixel row including the pixel 3-3 is different from the other pixel rows. Therefore, second wirings 103, 104, 106, and 107 for supplying a first voltage equal to the first wiring are arranged in the pixel row direction. In this manner, by further arranging the second wiring, it is possible to correct not only the correction of the first pixel but also the output difference of the pixel row including the pixel 3-3 using another pixel row. Become.

  Here, it is also possible to use the pixels 1-3 and 5-3 as the second pixels with respect to the first pixel 3-3. Even in this case, since an output difference occurs between the first pixel and the second pixel, it is desirable to arrange the second wirings 103 and 107. However, in the configuration in which the signal is read out for each pixel row, a memory for holding a signal of a pixel in a pixel row different from the first pixel is necessary, and thus the second pixel is the same as the first pixel. Preferably in the pixel row.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIG. FIG. 5 is a schematic plan view of a pixel region similar to FIG. The difference of this embodiment from the first embodiment is the color of the corresponding color filter of the first pixel 3-3 where the well contact is disposed. In the first embodiment, the well contact is arranged on the red pixel, but in this embodiment, the well contact is arranged on the blue pixel 3-3.

  In an image pickup apparatus having a Bayer color filter, pixels (green pixels) provided with green color filters tend to be more sensitive than pixels provided with other color filters (blue pixels and red pixels). is there. Therefore, when white light including the three primary colors is irradiated, the green pixel is saturated earlier than the blue pixel and the red pixel. Specifically, when the saturation level of the photoelectric conversion element is 1 V and white light is irradiated, when the green pixel reaches saturation (1 V), the blue pixel becomes 700 mV, the red pixel becomes 800 mV, and the blue pixel and the red pixel are still The saturation level has not been reached. That is, since the green pixel is recognized as white when it is saturated, the difference of 300 mV and 200 mV from the saturation level of the blue pixel and the red pixel need not be used. Therefore, it is desirable to arrange the well contact in the red pixel and further in the blue pixel rather than the green pixel.

  By making the pixel in which the well contact is arranged a red pixel or a blue pixel, performance deterioration due to the arrangement of the well contact is reduced, correction becomes easier, and a good image can be obtained. In addition, even when correction is not performed, it is possible to obtain good image quality.

(Fifth embodiment)
A fifth embodiment will be described with reference to FIG. This embodiment has a configuration in which the pixel circuit configuration is different from that of the second embodiment shown in FIG. Two photoelectric conversion elements share an amplification MOS transistor and a reset MOS transistor. 6A is a schematic plan view of a pixel region similar to FIG. 3A, and FIG. 6B is a pixel circuit diagram similar to FIG. 3B. Configurations having similar functions are denoted by the same reference numerals and description thereof is omitted.

  6A and 6B, reference numeral 601 denotes a unit cell, and the unit cells 601 are arranged two-dimensionally. The unit cell 601 includes two photoelectric conversion elements, an amplification MOS transistor 204, and a reset MOS transistor 203. In other words, it can be said that one unit cell includes two pixels. In the unit cell 601, two semiconductor regions 206 are connected to one amplification MOS transistor 204. In this embodiment, the semiconductor region 206 is connected by the connection wiring 207 as shown in FIG. 6A, but may be connected by the semiconductor region (the same semiconductor region). Such a circuit configuration makes it possible to reduce the number of pixel elements. Therefore, the pixel can be reduced while maintaining the area of the photoelectric conversion element, or the area of the photoelectric conversion element can be maintained while maintaining the size of the pixel. Can be increased.

However, in such a circuit configuration, coupling between the element included in the capacitor C _fd and the first wiring 105 (GND) is likely to occur, such as the connection wiring 207 being long. Also in the case of being connected by the semiconductor region 206, since the area of the semiconductor region 206 becomes large, coupling with the first wiring 105 (GND) is likely to occur. Therefore, in the pixel configuration as in this embodiment, the influence on the capacitance C _fd by the first wiring 105 (GND) is greater than that in the second embodiment. Therefore, it is more desirable to provide the second wiring (the wiring 103 or the wiring 107, VDD).

(Application to imaging system)
In the present embodiment, a case where the imaging apparatus described in the first to fifth embodiments is applied to an imaging system will be described with reference to FIG. The imaging system is a digital still camera, a digital video camera, or a digital camera for mobile phones.

  FIG. 7 is a block diagram of a digital still camera. An optical image of a subject is formed on the imaging surface of an imaging device (photoelectric conversion device) 804 by an optical system including a lens 802 and the like. On the outside of the lens 802, a barrier 801 serving both as a protection function of the lens 802 and a main switch can be provided. The lens 802 can be provided with a stop 803 for adjusting the amount of light emitted therefrom. The imaging signal output from the photoelectric conversion device 804 through a plurality of channels is subjected to various corrections, clamping, and the like by the imaging signal processing circuit 805. Imaging signals output from the imaging signal processing circuit 805 through a plurality of channels are analog-digital converted by an A / D converter 806. The image data output from the A / D converter 806 is subjected to various corrections, data compression, and the like by a signal processing unit (image processing unit) 807. The photoelectric conversion device 804, the imaging signal processing circuit 805, the A / D converter 806, and the signal processing unit 807 operate in accordance with the timing signal generated by the timing generation unit 808.

  805 to 808 may be formed on the same chip as the photoelectric conversion device 804. Each block is controlled by the overall control / arithmetic unit 809. In addition, a memory unit 810 for temporarily storing image data and a recording medium control interface unit 811 for recording or reading an image on a recording medium are provided. The recording medium 812 includes a semiconductor memory or the like and can be attached and detached. Furthermore, an external interface (I / F) unit 813 for communicating with an external computer or the like may be provided.

  Next, the operation of FIG. 7 will be described. When the barrier 801 is opened, the main power supply, the control system power supply, and the image pickup system circuit such as the A / D converter 806 are sequentially turned on. Thereafter, the overall control / arithmetic unit 809 opens the aperture 803 to control the exposure amount. A signal output from the photoelectric conversion device 804 passes through the imaging signal processing circuit 805 and is provided to the A / D converter 806. The A / D converter 806 A / D converts the signal and outputs it to the signal processing unit 807. The signal processing unit 807 processes the data and provides it to the overall control / calculation unit 809, and the overall control / calculation unit 809 performs computation to determine the exposure amount. The overall control / calculation unit 809 controls the aperture based on the determined exposure amount.

  Next, the overall control / calculation unit 809 extracts a high frequency component from the signal output from the photoelectric conversion device 804 and processed by the signal processing unit 807, and calculates the distance to the subject based on the high frequency component. Thereafter, the lens 802 is driven to determine whether or not it is in focus. If it is determined that the subject is not in focus, the lens 802 is driven again to calculate the distance.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the imaging signal output from the photoelectric conversion device 804 is corrected in the imaging signal processing circuit 805, A / D converted by the A / D converter 806, and processed by the signal processing unit 807. The image data processed by the signal processing unit 807 is accumulated in the memory unit 810 by the overall control / arithmetic unit 809.

  Thereafter, the image data stored in the memory unit 810 is recorded on the recording medium 812 via the recording medium control I / F unit under the control of the overall control / arithmetic unit 809. Further, the image data is provided to a computer or the like through the external I / F unit 813 and processed.

  As described above, the configuration of the present invention makes it easy to correct a pixel in which a well contact is arranged. This pixel correction is performed at an arbitrary place such as the imaging signal processing circuit 805 and the signal processing unit 807, and the configuration of the present invention enables reduction of necessary memory and easy calculation.

  In the description of the present invention, the structure in which the well contact is disposed on the same active region as the photoelectric conversion element is used. However, the well contact may be disposed in another active region separated by using a field oxide film. Further, the pixels that make well contact are not limited to the colors of the present embodiment, and can be applied to a monochrome imaging device that does not have a color filter.

  Further, although Gr and Gb of the Bayer array color filter are described as pixels having different characteristics, since Gr and Gb are the same green, the first pixel is a pixel corresponding to Gr. In this case, a pixel corresponding to Gb may be used as the second pixel.

  The configurations of the embodiments can be used in combination with each other.

(A) The plane schematic diagram of the pixel area which shows 1st Embodiment, (B) The plane schematic diagram of the pixel area which shows 1st Embodiment. (A) The plane schematic diagram of the pixel area | region explaining 1st Embodiment, (B) The equivalent circuit schematic of the pixel area | region explaining 1st Embodiment. (A) The plane schematic diagram of the pixel area | region explaining 2nd Embodiment. (B) The equivalent circuit schematic of the pixel area | region explaining 2nd Embodiment. FIG. 10 is a schematic plan view of a pixel region for explaining a third embodiment. The plane schematic diagram of the pixel area explaining a 4th embodiment. FIG. 10 is a schematic plan view of a pixel region for explaining a fifth embodiment. 1 is a block diagram illustrating an imaging system.

Explanation of symbols

101 array of 200 pixels × 200 pixels 102 well fixing region 1-1 to 5-5 pixel 110 well contact 105 first wiring 103, 104, 106, 107 second wiring 108 outer edge of pixel 201 photoelectric conversion element 202 transfer MOS Transistor 203 Reset MOS transistor 204 Amplification MOS transistor 205 Selection MOS transistor 206 Semiconductor region 207 Connection wiring V1, V2 Signal lines 301, 302 Third wiring

Claims (11)

A pixel region in which pixels including one photoelectric conversion element are two-dimensionally arranged;
An imaging apparatus having a plurality of color filters in which one color is arranged corresponding to each pixel,
A floating diffusion region to which charges generated in the photoelectric conversion element are transferred;
An amplification MOS transistor that outputs a signal based on the potential of the floating diffusion region, a first pixel in which a well contact is disposed,
A first wiring that is arranged in a first pixel column including the first pixel and is electrically connected to the well contact and supplied with a first voltage;
A second pixel included in a second pixel column different from the first pixel column, in which a color filter of the same color as the first pixel is disposed and the well contact is not disposed,
An imaging device comprising: a second wiring arranged in the second pixel column.   The imaging device according to claim 1, wherein the first voltage is supplied to the second wiring. The first wiring is disposed on the floating diffusion region of the first pixel or the gate electrode of the amplification MOS transistor of the first pixel,
3. The imaging according to claim 1, wherein the second wiring is arranged on a floating diffusion region of the second pixel or an upper part of a gate electrode of an amplification MOS transistor of the second pixel. apparatus. The color filter is a Bayer array,
The imaging apparatus according to claim 1, wherein the same color is blue.   5. The imaging apparatus according to claim 1, wherein the second pixels are arranged in the same row as the first pixels. 6. Having a third pixel column between the first pixel column and the second pixel column;
The third pixel column has a third wiring electrically connected to the source or drain of the amplification MOS transistor,
6. The third wiring according to claim 1, wherein the third wiring supplies a second voltage to a source or a drain of the amplification MOS transistor of the first pixel or the second pixel. The imaging apparatus according to item 1.   The imaging device according to claim 1, wherein the amplification MOS transistor outputs a signal based on charges from the plurality of photoelectric conversion elements.   The imaging apparatus according to claim 7, wherein a signal based on charges from the plurality of photoelectric conversion elements is transferred to the floating diffusion region. An imaging apparatus having a pixel region in which one pixel including one photoelectric conversion element is two-dimensionally arranged,
A floating diffusion region to which charges generated in the photoelectric conversion element are transferred;
An amplification MOS transistor that outputs a signal based on the potential of the floating diffusion region, a first pixel in which a well contact is disposed,
A first wiring that is arranged in a first pixel column including the first pixel, is electrically connected to the well contact, and is supplied with a first voltage;
A second pixel that is included in a second pixel column different from the first pixel column, is adjacent to the first pixel, and is not provided with the well contact;
An imaging device comprising: a second wiring arranged in the second pixel column.   The imaging device according to claim 9, wherein the second voltage is supplied to the second wiring. The imaging device according to any one of claims 1 to 10,
An image pickup system comprising: a signal processing circuit that processes an output signal from the image pickup apparatus.

Images