JP2010259110A - Solid-state imaging sensor and solid-state imaging system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent deterioration of image quality by devising layouts of a plurality of storage capacities. <P>SOLUTION: In a solid-state image sensor provided with a first storage capacity Cs and a second storage capacity Cn respectively holding first signals and second signals read from each pixel 300, lengths (gate length L) of the first storage capacity Cs and the second storage capacity Cn in the shorter direction is longer than a pixel pitch. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a solid-state imaging system, and more particularly to a solid-state imaging device and a solid-state imaging system used for a digital camera or the like.

  Conventionally, a plurality of imaging lenses are provided on a plane, and each imaging lens collects light from an imaging target on a two-dimensional sensor having a photoelectric conversion element, and outputs an output signal from the two-dimensional sensor, etc. There is a solid-state imaging device that forms an image by processing in a processing unit.

  FIG. 1 is a schematic diagram illustrating a configuration of a solid-state imaging device including a conventional MOS type imaging device. In FIG. 1, reference numeral 300 denotes a pixel including any one of G, B, and R color filters, 301 denotes a photodiode that converts incident light into electric charge, 307 denotes a floating diffusion region to which the converted electric charge is transferred, and 302. Is a transfer switch for transferring the charge of the photodiode 301 to the floating diffusion region 307, 303 is a MOS transistor for obtaining an amplified signal based on the charge, 305 is a selection switch for applying a voltage from the power source VD to the MOS transistor 303, 306 Is a vertical signal line from which the amplified signal is read, 313 is a constant current source for reading the amplified signal to the vertical signal line, and 304 is for resetting the potential of the floating diffusion region 307 and the photodiode 301 after reading the amplified signal. This is a reset switch for applying the power supply VR. Here, the transfer switch 302, the reset switch 304, and the selection switch 305 are composed of MOS transistors.

  In FIG. 1, reference numerals 312, 314, and 315 denote transfer pulses for controlling ON / OFF of the transfer switch 302, the reset switch 304, and the selection switch 305, a transfer pulse transmission line for transmitting a reset pulse and a selection pulse, and a reset pulse, respectively. Transmission line and selection pulse transmission line, 931-933 are transfer pulse transmission lines 312, reset pulse transmission line 314 and selection pulse transmission line 315, and transfer to input generation signals for generating reset pulse and selection pulse, respectively. A pulse generation signal input terminal, a reset pulse generation signal input terminal and a selection pulse generation signal input terminal, and 330 are input from a transfer pulse generation signal input terminal 931, a reset pulse generation signal input terminal 932, and a selection pulse generation signal input terminal 933, respectively. Generated signal and An AND gate for adding the control signal outputted from the vertical shift register 906 on the basis of the click signal PV.

  Further, in FIG. 1, reference numerals 320a and 320b denote noise cancellation circuits 323a and 323b for canceling noise signals such as fixed patterns caused by switching operations of the transfer switch 302, the reset switch 304, and the selection switch 305 and manufacturing variations of the transfer switch 302 and the like. Is an amplified signal holding capacitor for storing an amplified signal including a noise signal, switches 324a and 324b are noise signal holding capacitors for storing a noise signal, and 321a and 321b are amplified signals holding capacitors 323a and 323b according to the control signal Ptn. Switches 322a and 322b are switches for sending noise signals to the noise signal holding capacitors 324a and 324b in accordance with the control signal Pts, and 325a and 325b are amplified signals held in the amplified signal holding capacitors 323a and 323b. Switches 326a and 326b output the noise signals held in the noise signal holding capacitors 324a and 324b to the clock signal PH1 based on the clock signals PH1 and PH2 in accordance with the control signals output from the horizontal shift registers 911a and 911b. , PH2, and switches 327a and 327b that are output to the outside in accordance with control signals output from the horizontal shift registers 911a and 911b are differential amplifiers that amplify the signals output from the noise cancellation circuits 320a and 320b.

  In FIG. 1, for example, a signal read from the pixels 300 arranged in the odd columns is sent to the noise cancellation circuit 320a on the horizontal shift register 911a side and read from the pixels 300 arranged in the even columns. The received signal is sent to the noise cancellation circuit 320b on the horizontal shift register 911b side.

  Further, although four pixels 300 are shown in FIG. 1 for the sake of simplicity, the number of pixels corresponding to the required resolution and the area of the imaging region is actually arranged. Further, the number of noise cancellation circuits 320a and 320b corresponding to the number of pixel columns is provided. As will be described below, the noise cancellation circuits 320a and 320b are actually arranged at a two-pixel pitch.

FIG. 7B is a layout diagram of the upper surfaces of the noise cancellation circuits 320a and 320b of FIG. Fig.7 (a) is sectional drawing between AA 'of FIG.7 (b). In FIG. 7, 600 is an n-type semiconductor substrate, 603 is a high-concentration p-type diffusion region for forming the source-drain of a p-type channel MOS transistor provided in the n-type semiconductor substrate 600, and 601 is on the n-type semiconductor substrate 600. A silicon oxide film (SiO ₂ ) 602 formed on the substrate, 602 is a high-concentration n-type diffusion region for taking the potential of the n-type semiconductor substrate 100, and 604 is a multi-layer made of polysilicon that forms the gate of a p-type channel MOS transistor. A crystalline silicon layer (Poly-Si layer), 606 is a wiring layer (Al layer) made of aluminum or the like, 605 is a wiring layer 606 and a polycrystalline silicon layer 102, a high-concentration n-type diffusion region 602 or a high-concentration p-type diffusion region. Each contact hole is electrically connected.

  The noise signal holding capacitors 324a and 324b shown in FIG. 1 are indicated by Cn, and the amplified signal holding capacitors 323a and 323b are indicated by Cs. The wiring layer 606 in Cs in the drawing connects the switches 321a and 321b and the switches 325a and 325b, respectively, and the wiring layer 606 in Cn connects the switches 322a and 322b and the switches 326a and 326b, respectively. ing.

  As shown in FIG. 7, the noise cancellation circuits 320a and 320b are arranged so that the respective short directions of the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn are within one pixel pitch. The gate length of the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn is, for example, 3.5 μm, and the gate width is, for example, 1100 μm.

  However, in recent years, the pixel size of the solid-state imaging device is being reduced along with the trend of reduction in chip size and increase in the number of pixels. When the pixel pitch is shortened as the pixel size is reduced, the gate lengths of the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn are shortened.

  Here, the gate length variation ΔL is caused by the variation in processing accuracy when the gate is formed. The gate length variation becomes larger as each gate length becomes shorter, and the amplified signal holding capacitance Cs and the noise signal holding capacitance Cn The variation in the capacitance value increases. As a result, the performance of the solid-state imaging device has a problem that the image quality deteriorates due to an increase in fixed pattern noise for each column.

  In view of the above, an object of the present invention is to devise a layout of a plurality of storage capacitors to prevent deterioration in image quality.

In order to solve the above problems, the present invention provides a plurality of pixels arranged in a horizontal direction and a vertical direction, a plurality of vertical output lines commonly connected to the plurality of pixels in the vertical direction, and one vertical output. A plurality of storage capacitors that are provided for each line and hold a signal of the vertical output line; and a horizontal output line from which the signal of the vertical output line is read, the horizontal output line sandwiching the pixel region The first and second horizontal output lines are arranged opposite to each other, and the plurality of vertical output lines includes a first vertical output line group for reading a signal to the first horizontal output line, and the second And a second vertical output line group for reading a signal to a horizontal output line, and the plurality of storage capacitors are arranged in the vertical direction.
Another aspect of the invention described in this specification includes a plurality of pixels arranged in one direction, a common output line from which signals from the plurality of pixels are sequentially read, and a signal from the plurality of pixels, respectively. A plurality of readout means for reading out to the common output line; and a plurality of storage capacitors provided between the pixels and the readout means, wherein the plurality of storage capacitors are perpendicular to the one direction. It is arranged in the direction.

According to still another aspect of the invention described in this specification, a plurality of pixels arranged in a plurality of horizontal and vertical directions and a plurality of vertical outputs commonly connected to each of the plurality of pixels in the vertical direction. And a plurality of storage capacitors provided for each vertical output line, and a plurality of storage capacitors for each vertical output line are arranged in the vertical direction.

Furthermore, in a preferred embodiment of the present invention , in a solid-state imaging device having a storage capacitor that stores a signal read from each pixel, the length of the storage capacitor in the short direction is longer than the pixel pitch. And

In a preferred embodiment of the present invention , in the solid-state imaging device including a first storage capacitor and a second storage capacitor that respectively hold a first signal and a second signal read from each pixel, the first storage capacitor and the second storage capacitor The length of the second storage capacitor in the short direction is longer than the pixel pitch.

  Furthermore, a solid-state imaging system of the present invention includes the solid-state imaging device, an optical system that focuses light on the solid-state imaging device, and a signal processing circuit that processes an output signal from the solid-state imaging device. And

  As described above, since the present invention suppresses the increase in fixed pattern noise, it is possible to prevent the image quality from being deteriorated.

It is a schematic diagram which shows the structure of the solid-state imaging device provided with the MOS type imaging device of Embodiment 1 of this invention. It is a circuit diagram of one form of the noise cancellation circuit of FIG. FIG. 3 is a layout view and a cross-sectional view of the top surface of the noise cancellation circuit of FIG. 2. FIG. 2 is a pattern diagram of pulse signals used in the solid-state imaging device of FIG. 1. It is the layout figure and sectional drawing of the upper surface of the noise cancellation circuit which concern on Embodiment 2 of this invention. It is a block diagram of the solid-state imaging system of Embodiment 3 of this invention. It is the layout figure and sectional drawing of the upper surface of the noise cancellation circuit of the conventional solid-state imaging device.

(Embodiment 1)
[Description of configuration]
FIG. 1 is a schematic diagram illustrating a configuration of a solid-state imaging apparatus including a MOS imaging element according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 300 denotes a pixel including any one of G, B, and R color filters, and a plurality of pixels are arranged in the horizontal direction and the vertical direction. Reference numeral 301 denotes a photodiode that converts incident light into electric charge, 307 denotes a floating diffusion region to which the converted electric charge is transferred, 302 denotes a transfer switch that transfers electric charge of the photodiode 301 to the floating diffusion region 307, and 303 denotes a first signal. MOS transistor for obtaining an amplified signal based on a certain charge, 305 is a selection switch for applying a voltage from the power source VD to the MOS transistor 303, 306 is a vertical signal line from which the amplified signal is read, 313 is an amplified signal on the vertical signal line , A constant current source 304 for reading out, and a reset switch 304 for applying a power source VR to reset the potentials of the floating diffusion region 307 and the photodiode 301 after reading out the amplified signal. Here, the transfer switch 302, the reset switch 304, and the selection switch 305 are composed of MOS transistors.

  In FIG. 1, reference numerals 312, 314, and 315 denote transfer pulses for controlling ON / OFF of the transfer switch 302, the reset switch 304, and the selection switch 305, a transfer pulse transmission line for transmitting a reset pulse and a selection pulse, and a reset pulse, respectively. Transmission line and selection pulse transmission line, 931-933 are transfer pulse transmission lines 312, reset pulse transmission line 314 and selection pulse transmission line 315, and transfer to input generation signals for generating reset pulse and selection pulse, respectively. A pulse generation signal input terminal, a reset pulse generation signal input terminal and a selection pulse generation signal input terminal, and 330 are input from a transfer pulse generation signal input terminal 931, a reset pulse generation signal input terminal 932, and a selection pulse generation signal input terminal 933, respectively. Generated signal and An AND gate for adding the control signal outputted from the vertical shift register 906 on the basis of the click signal PV.

  Further, in FIG. 1, reference numerals 320a and 320b denote noise cancellations for canceling a noise signal that is a second signal such as a fixed pattern caused by the switching operation of the transfer switch 302, the reset switch 304, and the selection switch 305, and manufacturing variations of the transfer switch 302 and the like. Circuits 323a and 323b are amplification signal holding capacitors that are first holding capacitors for accumulating amplified signals including noise signals, and switches 324a and 324b are noise signal holding capacitors that are second holding capacitors for accumulating noise signals, 321a, 321b is a switch for sending an amplified signal to the amplified signal holding capacitors 323a and 323b according to the control signal Ptn, 322a and 322b are switches for sending a noise signal to the noise signal holding capacitors 324a and 324b according to the control signal Pts, and 325a and 325b are amplified signals. Switches 326a and 326b for outputting the amplified signals held in the holding capacitors 323a and 323b to the outside according to control signals output from the horizontal shift registers 911a and 911b based on the clock signals PH1 and PH2 A switch for outputting the noise signal held in 324b to the outside in accordance with a control signal output from the horizontal shift registers 911a and 911b based on the clock signals PH1 and PH2, and 327a and 327b are output from the noise cancellation circuits 320a and 320b. It is a differential amplifier that amplifies each signal.

  In FIG. 1, for example, a signal read from the pixels 300 arranged in the odd columns is sent to the noise cancellation circuit 320a on the horizontal shift register 911a side and read from the pixels 300 arranged in the even columns. The received signal is sent to the noise cancellation circuit 320b on the horizontal shift register 911b side.

  Further, although four pixels 300 are shown in FIG. 1 for the sake of simplicity, the number of pixels corresponding to the required resolution and the area of the imaging region is actually arranged. In addition, the number of noise cancellation circuits 320a and 320b corresponding to the number of pixel columns is provided.

  FIG. 2 is a circuit diagram of one form of the noise cancellation circuits 320a and 320b of FIG. FIG. 3B is a layout diagram of the top surfaces of the noise cancellation circuits 320a and 320b of FIG. FIG. 3A is a cross-sectional view taken along the line A-A ′ in FIG. In this embodiment, a so-called p-type channel MOS transistor is used.

  In FIG. 2, 323 ′ and 324 ′ are p-type channel MOS transistors. In FIG. 2, the same parts as those shown in FIG.

In FIG. 3, 100 is an n-type semiconductor substrate, 110 is a high-concentration p-type diffusion region for forming the source-drain of a p-type channel MOS transistor provided in the n-type semiconductor substrate 600, and 111 is on the n-type semiconductor substrate 100. The silicon oxide film (SiO ₂ ) 102 is formed, a polycrystalline silicon layer (Poly-Si layer) 102 made of polysilicon or the like forming the gate of the p-type channel MOS transistor, and 103, 104, 107 are made of aluminum or the like. Wiring layers (Al layers) 105, 106 and 108 connect the wiring layer 103 and the polycrystalline silicon layer 101, the wiring layer 104 and the polycrystalline silicon layer 102, the wiring layer 107 and the high-concentration p-type diffusion region 110, respectively. A contact hole 109 is a power line for preventing crosstalk between the wiring layers 103 and 104. Although not shown, a high-concentration n-type diffusion region for taking the potential of the n-type semiconductor substrate 100 is formed in the n-type semiconductor substrate 100.

  The wiring layer 103 connects the switches 321a and 321b and the switches 325a and 325b, respectively, and the wiring layer 104 connects the switches 322a and 322b and the switches 326a and 326b, respectively.

  As shown in FIG. 3, in this embodiment, the amplification signal holding capacitor Cs and the noise signal holding capacitor Cn are arranged so that the gate lengths (short direction) L are within one pixel pitch and within two pixel pitches. ing. In addition, the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn are arranged in a vertical direction that is a direction perpendicular to a plurality of pixels in the horizontal direction. Each gate length of the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn is, for example, 8 μm, and each gate width (longitudinal direction) is, for example, 500 μm.

  By the way, the gate lengths and the gate widths of the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn are ideally the same so that the variation of the capacitance value hardly increases even when the gate length variation ΔL increases. It is desirable to lay out as follows.

  However, for example, when [each gate length / each gate width] is 0.05, 0.01, 0.1, 1, 10, the capacitance variation is 0.1%, 0.05%, 0.018%, respectively. 0.01% and 0.018%, and [each gate length / each gate width] has an exponential logarithmic relationship, and considering this, [each gate length / each gate width] Is preferably about 0.1.

  Thus, in order to adjust each gate length and each gate width of the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn, the gate length and the gate width are set to about 65 μm, for example, at a pitch of 5 to 8 pixels. As the gate length, the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn may be arranged in the gate width direction in accordance with each gate length.

  However, in practice, if the gate length is 5 pixels, the layout of the wiring layer 107 and the like becomes troublesome. Therefore, as shown in FIG. 3, it is sufficient to secure the gate length so as to fit within about 2 pixel pitch.

In FIG. 3, the amplified signal holding capacitor Cs is arranged on the side far from the pixel.
The noise signal holding capacitor Cn may be arranged on the side far from the pixel.

  Further, the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn may be n-type channel MOS transistors. However, if any MOS transistor is used, for example, each pixel 300 is configured by a MOS type image pickup device. In some cases, the same layer structure makes the manufacture easy.

[Description of operation]
FIG. 4 is a pattern diagram of pulse signals used in the solid-state imaging device of FIG. As shown in FIG. 4, (1) when the clock signal PV input to the vertical shift register 906 becomes high level, the output of the first stage of the vertical shift register 906 becomes high level. Thus, the low-level transfer pulse Ptx, the high-level reset pulse Pres, and the low-level selection pulse Psel are respectively applied to the transfer switch 302, the reset switch 304, and the selection switch 305 in the pixels in the first row.

  For this reason, only the reset switch 304 is turned on, and the potential of the floating diffusion region 307 becomes the reset voltage VR. Next, (2) when the reset pulse Pres is set to a low level, reset noise is generated and the potential of the floating diffusion region 307 changes.

At the same time, by setting the selection pulse Psel to high level, reset noise and
A noise signal including fixed pattern noise due to threshold variation of the MOS transistor is output to the vertical signal line 306. Next, (3) the noise signal is held in the noise signal holding capacitors 323a and 323b by setting the control signal Ptn to the high level.

  Next, (4) by setting the transfer pulse Ptx to high level, the charge accumulated in the photodiode 301 is transferred to the floating diffusion region 307, and from the source of the MOS transistor 303 to the charge and the noise signal due to reset. The amplified signal is output to the vertical signal line 306. Next, (5) by setting the control signal Pts to a high level, the output amplified signal is held in the amplified signal holding capacitors 324a and 324b. Through the above operations (1) to (5), the signals of all the pixels in the first row are held in the amplified signal holding capacitors 324a and 324b and the noise signal holding capacitors 323a and 323b corresponding to the respective columns.

  Next, (6) the clock signal PH1 is set to the high level, and the horizontal shift register 911a is simultaneously turned on by the switches 325a and 326a, thereby being held in the amplified signal holding capacitor 324a related to the pixel in the first column. The noise signal held in the noise signal holding capacitor 323a related to the pixel in the first column is read out from the amplified signal, input to the differential amplifier 327a, and the noise signal is subtracted from the amplified signal, so that the noise signal component And only the amplified signal based on the charge is output from the differential amplifier 327a.

  Then, after the clock signal PH1 is set to the low level, the clock signal PH2 is set to the high level, and the horizontal shift register 911b is turned on at the same time by turning on the switches 325b and 326b. The noise signal held in the noise signal holding capacitor 323b related to the pixel in the second column is read out from the amplified signal held in the capacitor 324b, input to the differential amplifier 327b, and the noise signal is subtracted from the amplified signal. Thus, the noise signal component is removed, and only the amplified signal based on the charge is output from the differential amplifier 327b.

  By similarly setting the clock pulses PH1 and PH2 to the high level and the low level in the same procedure, the horizontal shift registers 911a and 911b are sequentially scanned, and the charges from the pixels from the first row to the first column to the last column are obtained. Based on the amplified signals, the differential amplifiers 327a and 327b are sequentially output alternately.

  Next, (7) the clock pulse PV is set to the high level, the vertical shift register 906 is scanned one stage, and the output of the second stage of the vertical shift register 906 is set to the high level, so that the pixels in the second row Is selected, and (1) to (6) are repeated, so that amplified signals based on the charges from the pixels in the two rows and all columns are sequentially output from the differential amplifiers 327a and 327b alternately. In this manner, an amplified signal for one frame is obtained by outputting an amplified signal based on charges from pixels in all rows and all columns to the outside.

(Embodiment 2)
FIG. 5B is a layout diagram of the top surfaces of the noise cancellation circuits 320a and 320b according to the present embodiment, and corresponds to FIG. FIG. 5A is a cross-sectional view taken along the line AA ′ in FIG. 5B, and corresponds to FIG. As shown in FIG. 5, in this embodiment, the amplified signal holding capacitor Cs is spatially formed by the porous silicon layers 203 and 209, and the noise signal holding capacitor Cn is spatially formed by the porous silicon layers 204 and 209. is doing.

  In FIG. 5, 200 is an n-type semiconductor substrate, 210 is a p-type well formed in the n-type semiconductor substrate 200, 202 is a selective film for element isolation, 203, 204 and 209 are porous silicon layers, 207, 208, 211 are wiring layers made of aluminum or the like, 205, 206, 212 are wiring layers 207, porous silicon layers 203, wiring layers 208, porous silicon layers 204, wiring layers 211, and porous silicon layers 209. Each contact hole is electrically connected, 210 is a silicon oxide film, and 213 is a power line for preventing crosstalk between the wiring layers 207 and 208. Although not shown, a high-concentration n-type diffusion region for taking the potential of the n-type semiconductor substrate 200 is formed in the n-type semiconductor substrate 200.

  The wiring layer 207 connects the switches 321a and 321b and the switches 325a and 325b, respectively. The wiring layer 208 connects the switches 322a and 322b and the switches 326a and 326b, respectively.

  In the present embodiment, each capacitor is formed using a parallel plate formed of a porous silicon layer as an electrode instead of each capacitor formed by a MOS transistor. With such a layout, parallel flat plates of porous silicon layers can be arranged at a pitch of 2 pixels, and the length in the short direction can be set to 10 μm, for example. Further, as shown in FIG. 3B, it is not necessary to arrange the two capacitors in the longitudinal direction, so that the length on the longitudinal direction side can be shortened.

  As in the first embodiment, the short direction may be a plurality of pixel pitches other than the two-pixel pitch. Further, even in a so-called compound eye solid-state imaging device in which a plurality of pixels are divided into several regions and the same color filter is formed on each region, the layout of each capacitor can be similarly performed.

  In the first and second embodiments, the solid-state imaging device including the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn has been described as an example. However, in the solid-state imaging device of the type that cancels noise, the amplified signal and the like are held. The short side direction of the storage capacitor may be, for example, a two-pixel pitch.

  In the first and second embodiments, the solid-state imaging device including the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn has been described as an example. However, one vertical signal is used so that signals from two pixels in the vertical direction can be held. The configuration may be such that a plurality of amplified signal holding capacitors Cs are provided for each output line.

  In the first and second embodiments, the configuration in which the signals are read out to the upper and lower differential amplifiers for each pixel in the vertical direction is described. However, signals from a plurality of pixels arranged in the horizontal direction and the vertical direction are described. The output from one differential amplifier may be sufficient. In this case, the amplified signal holding capacitor Cs and the noise signal holding capacitor Cn are arranged at a pixel pitch.

(Embodiment 3)
FIG. 6 is a configuration diagram of a solid-state imaging system using the solid-state imaging device described in the first and second embodiments. In FIG. 6, 1 is a barrier that serves as a lens protect and a main switch, 2 is a lens that forms an optical image of a subject on the solid-state imaging device 4 that is the solid-state imaging device described in the first and second embodiments, and 3 is a lens. A diaphragm for changing the amount of light that has passed through, 4 is a solid-state image sensor for capturing the subject imaged by the lens 2 as an image signal, and 5 is various corrections, clamps, etc. for the image signal output from the solid-state image sensor 4 The image signal processing circuit 6 performs the above processing, 6 is an A / D converter that performs analog-digital conversion of the image signal output from the solid-state image sensor 4, and 7 is various image data output from the A / D converter 6. Is a signal processing unit for performing correction of data and compressing data, 8 is a timing for outputting various timing signals to the solid-state imaging device 4, the imaging signal processing circuit 5, the A / D converter 6, and the signal processing unit 7. A generating unit, 9 is an overall control / arithmetic unit for controlling various operations and the entire still video camera, 10 is a memory unit for temporarily storing image data, and 11 is a recording medium for recording or reading on a recording medium. A control interface unit 12, a removable recording medium such as a semiconductor memory for recording or reading image data, and an external interface (I / F) unit 13 for communicating with an external computer or the like.

  Next, the operation of FIG. 6 will be described. When the barrier 1 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 6 is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 9 opens the aperture 3, and the signal output from the solid-state imaging device 4 passes through the imaging signal processing circuit 5 to the A / D converter 6. Is output. The A / D converter 6 performs A / D conversion on the signal and outputs it to the signal processing unit 7. The signal processing unit 7 performs an exposure calculation by the overall control / calculation unit 9 based on the data.

  The brightness is determined based on the result of the photometry, and the overall control / calculation unit 9 controls the aperture according to the result. Next, based on the signal output from the solid-state imaging device 4, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 9. Thereafter, the lens is driven to determine whether or not it is in focus. If it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 4 is corrected in the imaging signal processing circuit 5, further A / D converted by the A / D converter 6, and totally controlled through the signal processing unit 7. Accumulated in the memory unit 10 by calculation 9 Thereafter, the data stored in the memory unit 10 is recorded on a removable recording medium 12 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 9. Further, the image may be processed by directly entering the computer or the like through the external I / F unit 13.

DESCRIPTION OF SYMBOLS 1 Barrier 2 Lens 3 Diaphragm 4 Solid-state image sensor 5 Imaging signal processing circuit 6 A / D converter 7 Signal processing part 8 Timing generation part 9 Overall control and calculation part 10 Memory part 11 Recording medium control interface (I / F) part 12 Recording medium 13 External interface (I / F) section 101, 102, 203, 204, 209, 604 Polycrystalline silicon layer 103, 104, 107, 109, 207, 208, 211, 606 Wiring layer 105, 106, 108, 205 , 206, 212, 605 Contact hole 109, 213 Power supply line 110, 603 High concentration p-type diffusion region 111, 210, 601 Silicon oxide film 200, 600 n-type semiconductor substrate 201 p-type well 202 Select film 300 Pixel 301 Photodiode 302 Transfer switch 303 MOS transistor Star 304 reset switch 305 selection switch 306 vertical signal line 307 floating diffusion region 312 transfer pulse transmission line 313 constant current source 314 reset pulse transmission line 315 selection pulse transmission line 321a, 321b, 322a, 322b, 325a, 325b, 326a,
326b Switch 323a, 323b Amplified signal holding capacity 324a, 324b Reset signal holding capacity 327a, 327b Differential amplifier 330 AND gate 323 ', 324' p-type channel MOS transistor 602 High-concentration n-type diffusion region

Claims (7)

A plurality of pixels arranged in the horizontal and vertical directions;
A plurality of vertical output lines connected in common to the plurality of pixels in the vertical direction;
A plurality of storage capacitor for holding a signal of the vertical output lines are set eclipse every one vertical output lines,
A horizontal output line from which a signal of the vertical output line is read out ,
The horizontal output line has first and second horizontal output lines arranged opposite to each other across the pixel region,
The plurality of vertical output lines include a first vertical output line group that reads a signal to the first horizontal output line, and a second vertical output line group that reads a signal to the second horizontal output line. ,
A solid-state imaging apparatus characterized by disposing the holding capacity of the multiple in the vertical direction. The horizontal length of the plurality of storage capacitor, the solid-state imaging device according to claim 1, characterized in that has a length than the horizontal pixel pitch. 2. The plurality of storage capacitors provided for each vertical output line include a first storage capacitor that stores a noise signal and a second storage capacitor that stores a signal generated by photoelectric conversion. Or the solid-state imaging device of 2. The holding capacity, solid-state imaging device according to any one of claims 1 to 3, characterized in that formed using MOS transistors or parallel plate capacitor. Wherein each pixel, the solid-state imaging device according to claim 1, any one of 4, characterized in that the color separation filter is provided. Each of the pixels is provided with one of an R, G, and B color separation filter, and each of the separation filters includes an R filter and a B filter arranged diagonally, and two G filters arranged diagonally. the solid-state imaging device according to any one of claims 1-5, characterized in Rukoto. It has a solid-state imaging device according, an optical system for focusing light to the solid-state imaging device, a signal processing circuit for processing an output signal from the solid-state imaging device in any one of claims 1 6 Solid-state imaging system characterized by

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