JP2009054852A - Solid-state imaging device and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device and an imaging apparatus which are low in power consumption and easy to design. <P>SOLUTION: The solid-state imaging device 100 has a plurality of vertical charge transfer sections 3 for transferring signal charges read out of a photoelectric conversion section 2 in a column direction; a horizontal charge transfer section 5, which transfers the signal charges transferred in the vertical charge transfer sections 3 in a row direction X orthogonal to the column direction Y, and the horizontal charge transfer section 5 is divided into at least three blocks 5b for transferring signal charges, respectively. Then an output section 8, which detects signal charges transferred in each block by floating diffusion and outputs them, is connected to the block downstream in the signal charge transfer direction; each output section 8 has a dummy transfer section extended from a horizontal transfer electrode to leave it and coupling the horizontal charge transfer section 5 and floating diffusion; and at least the horizontal charge transfer section 5 and dummy transfer section are covered with the same light-shielding film 13. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a photoelectric conversion element, a number of vertical charge transfer paths for transferring charges generated in the photoelectric conversion element in the vertical direction, and a horizontal direction perpendicular to the vertical direction for charges transferred through the vertical charge transfer path. The present invention relates to a solid-state image pickup device having a horizontal charge transfer path for transferring to a battery.

  In the CCD type solid-state imaging device, the driving frequency of the horizontal CCD has increased with the recent increase in the number of pixels, which causes an increase in power consumption. Conventionally, in order to reduce power consumption, a CCD type solid-state imaging device having a configuration without a horizontal CCD has been proposed. According to this solid-state imaging device, since there is no horizontal CCD, power consumption can be greatly reduced. However, since there is no horizontal CCD, flexible driving for improving image quality such as pixel addition in the horizontal direction cannot be performed.

  Therefore, a solid-state imaging device having a horizontal CCD and proposed in Patent Document 1 and Patent Document 2 have been proposed as power consumption reduced. The solid-state imaging device described in Patent Document 1 and Patent Document 2 has a configuration in which a horizontal CCD is divided into two and an output amplifier is connected to each of the divided two horizontal CCDs.

Japanese Patent Laid-Open No. 2004-80286 JP 2004-194023 A

  However, as described in Patent Document 1 and Patent Document 2, it is difficult to cope with an increase in power consumption due to further increase in the number of pixels only by dividing the horizontal CCD into two. Further, in the configuration described in Patent Document 2, it is necessary to devise the structure of the horizontal CCD, and when miniaturization due to the increase in the number of pixels advances, the design is not easy.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a solid-state imaging device and an imaging apparatus that have low power consumption and are easy to design.

The above object of the present invention is achieved by the following configuration.
(1) A light receiving unit having a plurality of photoelectric conversion units, a plurality of vertical charge transfer units for transferring signal charges read from the plurality of photoelectric conversion units in a column direction, and the vertical charge transfer unit have been transferred. A solid-state imaging device having a horizontal charge transfer unit that transfers the signal charges in a row direction orthogonal to the column direction,
Each of the horizontal charge transfer units is divided into at least three blocks for transferring the signal charges, and the signal charges transferred in the blocks are detected by floating diffusion on the downstream side in the signal charge transfer direction of each block. Are connected to each output unit,
Each output unit includes a dummy transfer unit that extends in a direction away from the horizontal transfer electrode and connects the horizontal charge transfer unit and the floating diffusion.
A solid-state imaging device in which at least the horizontal charge transfer unit and the dummy transfer unit are covered with the same light-shielding film.

  According to this solid-state imaging device, a sufficient distance can be secured between the end of the light shielding film and the horizontal charge transfer unit, and a predetermined distance can be secured for the floating diffusion.

(2) The solid-state imaging device according to (1),
A solid-state imaging device in which the dummy transfer unit includes a plurality of transfer electrodes.

  According to this solid-state imaging device, the separation distance from the horizontal charge transfer unit can be increased by increasing the number of stages, and the horizontal charge transfer unit can be more reliably shielded from light.

(3) The solid-state imaging device according to (1) or (2),
A solid-state imaging device in which the dummy transfer unit is connected to a transfer electrode of the horizontal charge transfer unit, and signal charges are transferred in synchronization with a drive signal of the horizontal charge transfer unit.

  According to this solid-state imaging device, the drive signal for the horizontal charge transfer unit can be directly applied to the dummy transfer unit, and the driving of the dummy transfer unit is simplified.

(4) The solid-state imaging device according to any one of (1) to (3),
An output gate electrode is connected to the downstream end of the dummy transfer portion in the charge transfer direction,
A solid-state imaging device in which the light shielding film covers up to a connection position of the dummy transfer section with the output gate electrode.

  According to this solid-state imaging device, the distance from the horizontal charge transfer unit can be gained while securing a certain distance from the floating diffusion by covering the output gate electrode closest to the floating diffusion with the light shielding film.

(5) The solid-state imaging device according to any one of (1) to (4),
An optical system for forming an optical image on the solid-state imaging device;
An imaging apparatus comprising:

  According to this imaging apparatus, it is possible to acquire a good image with low power consumption and not affected by a false signal due to stray light.

  According to the solid-state imaging device according to the present invention, it is possible to provide a solid-state imaging device with low power consumption and easy design. Can be strong.

  The image pickup apparatus according to the present invention includes the solid-state image pickup device and the optical system that forms an optical image on the solid-state image pickup device. You can get it.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a solid-state imaging device and an imaging device according to the invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic plan view of a portion excluding a laminate above a semiconductor substrate of a CCD type solid-state imaging device for explaining an embodiment of the present invention.
The solid-state imaging device 100 shown in FIG. 1 is arranged in a square lattice pattern in the row direction (X direction in the drawing) of the n-type semiconductor substrate 1 and in the column direction (Y direction in the drawing) orthogonal to the row direction X. And a plurality of photoelectric conversion elements (photoelectric conversion units) 2 and a vertical transfer channel (VCCD) which is a plurality of vertical charge transfer units for transferring charges read from each photoelectric conversion element 2 in the column direction Y 3 and a line memory (LM) 4 connected to each vertical transfer channel 3 and temporarily storing the charges transferred through each vertical transfer channel 3, and the charges stored in LM4 are read out in the row direction X And a horizontal transfer channel (HCCD) 5 which is a horizontal charge transfer unit for transferring the data.

  The HCCD 5 is divided into at least three blocks in the row direction X. For example, eight VCCDs 3 arranged in the row direction X are electrically connected to each block 5b. The number of VCCDs 3 connected to each block 5b may be plural, and is not particularly limited. Each block 5b is connected to an output unit 8 for outputting a signal corresponding to the charge transferred to the end of the HCCD 5 in each block 5b. Each output unit 8 is connected to a CDS / AD unit 9 that performs analog signal processing of correlated double sampling processing on the analog signal output from the output unit 8 and digitizes the processed analog signal. . The output unit 8 includes an output gate unit 6 and an amplifier unit 7.

FIG. 2 is an enlarged view showing a configuration example of one block of the HCCD 5 shown in FIG. 1 by (a) and (b). In FIG. 2, a part of the block 5b stacked on the semiconductor substrate is also partially shown.
As shown in FIG. 2A, the HCCD 5 in the block 5b forms an accumulation region 10 made of an n-type impurity as a region for accumulating charges during the charge transfer operation of the HCCD 5, and a barrier during the charge transfer operation of the HCCD 5. The storage regions 10 and the barrier regions 11 are alternately arranged in the row direction X, including the barrier regions 11 made of n ⁻ -type impurities. Each storage area 10 is connected to the LM 4 shown in FIG. Although not shown in FIG. 2, a storage electrode having substantially the same shape as the storage region 10 is formed above the storage region 10, and a barrier electrode having substantially the same shape as the barrier region 11 is formed above the barrier region 11. Has been.

In the HCCD 5 at both ends in the row direction X of the block 5b, an inter-block barrier region 12 made of an n ⁻ type impurity for forming a barrier separating the blocks 5b is formed. Although not shown in FIG. 2, an inter-block barrier electrode having the same shape as the inter-block barrier region 12 is formed above the inter-block barrier region 12.

  A wiring (not shown) made of tungsten or the like is formed above the storage electrode, the barrier electrode, and the inter-block barrier electrode, and a light shielding film 13 made of tungsten or the like is formed above the wiring. Each of the storage electrode, the barrier electrode, and the inter-block barrier electrode is connected to the wiring at a contact portion (not shown).

  By controlling the voltage supplied to the storage electrode, the barrier electrode, and the inter-block barrier electrode via the wiring, the charge transferred from the LM 4 to each storage region 10 can be transferred in the row direction X. . Here, it is assumed that charges are transferred from the left to the right in FIG. 2, and in the figure, the storage region 10 disposed at the left end is defined as the first-stage storage region 10 and the storage region disposed at the right end. 10 is defined as the storage area 10 in the final stage. Similarly, for the barrier region 11, the barrier region 11 disposed at the left end is defined as the first-stage barrier region 11, and the barrier region 11 disposed at the right end is defined as the final-stage barrier region 11.

  A wiring connected to the storage electrode on the odd-numbered storage region 10 and the barrier electrode on the even-numbered barrier region 11, and a storage electrode on the even-numbered storage region 10 and a barrier electrode on the odd-numbered barrier region 11 Different drive pulses are supplied to the connected wiring. Thereby, the HCCD 5 of each block 5b is driven in two phases. In the HCCD 5, by repeatedly driving the drive pulse at a high level and a low level, the electric charge is sequentially moved to the next storage area 10 and transferred to the final storage area 10.

  Of the end in the column direction Y of the storage region 10 at the final stage, the output unit 8 is connected to the end opposite to the VCCD 3, that is, the end not connected to the LM4.

The output gate unit 6 is connected to the output gate barrier region 14 made of n ⁻ -type impurity connected to the final-stage storage region 10, the charge storage region 15 connected to the output gate barrier region 14, and the charge storage region 15. The floating diffusion (FD) 16 region and a reset gate 17 for resetting the potential of the FD 16 region. Although not shown, an electrode for applying a voltage to each of the output gate barrier region 14 and the charge storage region 15 is formed above the output gate barrier region 14 and the charge storage region 15. The charges transferred to the storage region 10 at the final stage move and accumulate in the charge accumulation region 15 due to the deep potential of the output gate barrier region 14, and the accumulated charges move and accumulate in the FD16 region. .

  The amplifier unit 7 is configured by a source follower circuit. The amplifier unit 7 is located below the HCCD 5 and the horizontally transferred charge is read and output to the FD 16 area on the amplifier unit 7 side. The first stage MOS transistor of this source follower circuit is constituted by the gate electrode 18 connected to the FD16 region, the source region 19 and the drain region 20. The potential change in the FD16 region is converted into a signal by the first-stage MOS transistor, and this signal is amplified by the source follower circuit. The amplified signal is input to the CDS / AD unit 9. The configuration of the output unit 8 is not limited to the illustrated one, and various known ones can be used.

  With such a configuration, the charge transferred to the storage region 10 at the final stage is transferred from the end of the storage region 10 in the column direction Y in the column direction Y, stored in the FD16 region, and stored in the FD16 region. A voltage signal in accordance with can be obtained.

  In the solid-state imaging device having this configuration, in each block 5b, the charge transferred to the final storage region 10 is transferred in the column direction Y and stored in the charge storage region 15. The time required for the charge transfer in the column direction Y to the charge storage region 15 is longer than the time required for the charge transfer in the row direction X from the storage region 10 to the next storage region 10, and the charge transfer efficiency in the block 5b is increased. There is concern about the decline.

  For this reason, in the solid-state imaging device 100, the potential at the time of voltage application of the final storage region 10 in each block 5b is the end portion on the VCCD3 side of the end portion in the column direction Y of the final storage region 10. And deeper toward the opposite end. By doing so, it is possible to shorten the time required for the charge transfer in the column direction Y from the storage region 10 in the final stage to the charge storage region 15, and to improve the charge transfer efficiency in the entire block 5b. It becomes.

  In the solid-state imaging device 100, since the HCCD 5 is divided into at least three blocks 5b and the output unit 8 is provided in each block 5b, the driving frequency of the HCCD 5 is significantly reduced as compared with the case where the HCCD 5 is not divided. be able to. For example, consider a case where the number of storage areas 10 included in the HCCD 5 is 2048. In this case, if the HCCD 5 is driven without being divided, it is assumed that a drive frequency of 36 MHz is required to realize a certain frame rate. When the HCCD 5 is divided into two as in Patent Documents 1 and 2, a drive frequency of 36/2 = 18 MHz is sufficient to realize the frame rate. Furthermore, when the HCCD 5 is divided into three or more (for example, 256) as in the present embodiment, a drive frequency of 2048/256 = 140 kHz is sufficient to realize the frame rate. Thus, as the number of divisions of the HCCD 5 increases, the drive frequency can be reduced, and power consumption can be reduced accordingly. As described above, the solid-state imaging device 100 can reduce the horizontal driving frequency while realizing a large number of pixels and a high frame rate, and can reduce power consumption.

  Incidentally, the solid-state imaging device 100 has a structure in which the HCCD channel region and the amplifier unit 7 are close to each other, and the end of the HCCD light shielding film 13A can be cut only at a position close to the HCCD channel. This is because the contact 21 between the gate electrode 18 of the amplifier unit 7 and the substrate in the FD16 region is formed through the light shielding film 13B using the light shielding film 13B formed by the same process as the HCCD light shielding film 13A. This is because it is necessary to provide a certain gap G between the light shielding film 13A and the light shielding film 13B used in the FD16 region. When the light shielding film 13A and the light shielding film 13B are brought close to each other, parasitic capacitance is generated and the light detection sensitivity is lowered. That is, the HCCD 5 is desired to be completely covered, but the FD16 region cannot be covered due to the generation of parasitic capacitance.

  On the other hand, as shown in FIG. 2B, a light shielding film 23 different from the HCCD light shielding film 13 is used for the contact 21 between the gate electrode 18 and the substrate in the FD16 area, and the FD16 area is formed by the HCCD light shielding film 13. In the case where the included amplifier section 7 is covered, as shown in FIG. 3 as seen from the arrow A-A in FIG. 2, tungsten films overlap each other. As a result, a parasitic capacitance F is generated between the light shielding film 23 in the FD16 region and the HCCD light shielding film 13, and this causes a decrease in charge detection sensitivity, which is disadvantageous for higher sensitivity. Although the insulating layers 24a and 24b are appropriately interposed, since the film thickness cannot be increased more than the horizontal distance, parasitic capacitance is generated between the upper and lower light shielding films 13 and 23. As described above, even if the above two cases are assumed, the parasitic capacitance increases, the sensitivity cannot be increased, and a false signal is generated by stray light and enters. In addition, if the channel part is formed long, the movement of electric charges becomes slow.

Therefore, the solid-state imaging device 100 according to the present embodiment solves these problems by further adding the following configuration.
FIG. 4 is an enlarged view of the vicinity of the HCCD to which a dummy transfer unit is added.
That is, the HCCD 5 is connected to one end of the VCCD 3 provided alternately with the channel stop region 27 via the LM 4. Above the HCCD 5, an inverted L-shaped electrode 26a and a rectangular electrode 26b are arranged in the horizontal direction X in this order.

  The transfer electrode of the HCCD 5 has an electrode (hereinafter referred to as a CG electrode) that transfers charges to the amplifier unit 7 for every 8 columns of the VCCD 3 and an electrode that is not horizontally transferred at this time (hereinafter referred to as an HS electrode). . A transfer prevention pulse φHS is applied to the HS electrode that prevents horizontal transfer. A CG electrode is interposed between the first electrode H1 and the dummy transfer unit 25, and a transfer pulse φCG is applied to the CG electrode.

  In the HCCD 5, an electrode set of a first electrode H1, a second electrode H2, a third electrode H3, and a fourth electrode H4 is repeated on the right side of the drawing from the HS electrode. Transfer pulses φH1, φH2, φH3, and φH4 are applied to this electrode set. The HCCD 5 operates to form a charge accumulation region and a barrier region by switching the level of the transfer pulse applied to these electrode sets between a high level and a low level, and forms a plurality of charge transfer stages.

  Each output unit 8 includes a dummy transfer unit 25 that extends in a direction away from the HCCD 5 on the opposite side of the HCCD 5 from the VCCD 3 and connects the HCCD 5 and the FD16 region. At least the HCCD 5 and the dummy transfer unit 25 are covered with the same light shielding film 13. The dummy transfer section 25 is provided with a first dummy electrode HD1, a second dummy electrode HD2, and a third dummy electrode HD3 that are transfer electrodes in a plurality of stages, and the first dummy electrode HD1 to the third dummy electrode HD3 are the first electrode. H1, the second electrode H2, and the third electrode H3 are connected in parallel. The first electrode H1 and the first dummy electrode HD1 have a transfer pulse φH1, the second electrode H2 and the second dummy electrode HD2 have a transfer pulse φH2, the third electrode H3 and the third dummy electrode HD3 have a transfer pulse φH3, A transfer pulse φH4 is applied to the fourth electrode H4.

  An output gate electrode OG is connected to the first dummy electrode HD1 of the dummy transfer section 25, and a DC bias φOG is applied to the output gate electrode OG. A reset terminal RS for resetting the potential of the FD16 region is connected to the FD16 region connected to the output gate electrode OG. The amplifier unit 7 has a source terminal OD and a reset drain terminal RD that constitute the first-stage MOS transistor of the source follower circuit. The potential change in the FD region is converted into a signal by the first-stage MOS transistor, and this signal is amplified by the source follower circuit. When the HS electrode is low and the CG electrode is synchronized with the H4 electrode, charges are transferred to the FD16 region side, transferred to one stage of the dummy transfer unit 25, and passed through the OG electrode that is a DC bias to the FD16 region. It is structured to be transferred and output.

  In the structure according to the present embodiment, the end of the HCCD light-shielding film 13 extends from the FD16 region to the vicinity of the OG electrode by taking a certain gap G. Even in the conventional structure that does not have the dummy transfer unit 25 from the HCCD 5 to the amplifier unit 7, the HCCD light shielding film 13 also extends from the FD16 region to the vicinity of the OG electrode, but the HCCD5. Therefore, the end of the HCCD light-shielding film 13 is close to the HCCD channel that performs horizontal transfer, and has a structure that easily enters the HCCD channel region that performs horizontal transfer when stray light enters (that is, dummy transfer). Since the portion 25 does not exist, the distance L in the figure is shortened). On the other hand, in the present embodiment, the end of the HCCD light shielding film 13 is separated from the HCCD channel region that performs horizontal transfer by the number of stages of the dummy transfer unit 25. Never get in.

  That is, a dummy transfer path 25 connected to the HCCD 5 is formed using the drive pulse of the HCCD 5, and the signal charge is transported to a place away from the HCCD 5 by applying the drive pulse of the HCCD 5 to the dummy transfer path 25. Thus, the distance L between the HCCD 5 and the end of the light shielding film 13 is increased to prevent light leakage. Since the FD16 region is connected by the dummy transfer unit 25, there is no problem due to extension of the transfer path such as a decrease in charge transfer efficiency due to an increase in the charge storage area. Also, a certain gap G is secured between the HCCD light shielding film 13 and the light shielding film 13 used in the FD 16 region (see FIG. 2A).

  Therefore, in the solid-state imaging device 100 according to the present embodiment, the HCCD 5 is divided into at least three blocks 5b, and the signal charges transferred in the block 5b on the downstream side in the signal charge transfer direction of each block 5b are in the FD16 region. Even though the amplifier unit 7 that detects and outputs is connected, the distance L between the HCCD 5 and the end of the light shielding film 13 can be increased, and the light shielding property against stray light can be enhanced. That is, the amplifier unit 7 is provided with a dummy transfer unit 25 that extends in a direction away from the HCCD 5 and connects the HCCD 5 and the FD 16 region, and the HCCD 5 and the dummy transfer unit 25 are covered with the same light shielding film 13. It is possible to provide the solid-state imaging device 100 that consumes power and is easy to design.

  The dummy transfer unit 25 includes a plurality of stages of transfer electrodes. By setting the desired number of stages, the distance from the HCCD 5 can be increased, and the horizontal charge transfer unit is more reliably shielded from light. Can do.

  The dummy transfer unit 25 is connected to the transfer electrode of the HCCD 5 and the signal charges are transferred in synchronization with the drive signals φH1 to φH4 of the HCCD 5, so that the drive signal for the HCCD 5 is applied to the dummy transfer unit 25 as it is. In addition, the driving of the dummy transfer unit 25 is simplified.

  Further, the output gate electrode OG is connected to the downstream end in the charge transfer direction of the dummy transfer unit 25, and the light shielding film 13 covers the connection position with the output gate electrode OG of the dummy transfer unit 25, so that the area closest to the FD16 region is covered. By covering up to the output gate electrode OG with the light shielding film 13, it is possible to earn a distance from the HCCD 5 while securing a certain distance from the FD16 region.

Next, a digital camera that is an image pickup apparatus including the solid-state image pickup device 100 according to the above-described embodiment will be described.
FIG. 5 is a block diagram of a digital camera equipped with a solid-state imaging device according to the present invention.
The digital camera shown in the figure includes a photographic lens 41, the above-described solid-state imaging device 100, a diaphragm 43 provided therebetween, an infrared cut filter 45, and an optical low-pass filter 47. A CPU 49 that performs overall control of the entire digital camera controls the flash light emitting unit 51 and the light receiving unit 53, controls the lens driving unit 55 to adjust the position of the photographing lens 41 to the focus position, and controls the aperture via the aperture driving unit 57. The amount of opening 43 is controlled to adjust the exposure amount.

  Further, the CPU 49 drives the solid-state image sensor 100 via the image sensor driving unit 59 and outputs the subject image captured through the photographing lens 41 as a color signal. An instruction signal from the user is input to the CPU 49 through the operation unit 61, and the CPU 49 performs various controls according to the instruction.

  The electric control system of the digital camera includes an analog signal processing unit 67 connected to the output of the solid-state imaging device 100, and an A / D conversion circuit that converts RGB color signals output from the analog signal processing unit 67 into digital signals. 69, and these are controlled by the CPU 49.

  Further, the electric control system of the digital camera includes a memory control unit 73 connected to a main memory (frame memory) 71 and digital signal processing for performing image processing such as gamma correction calculation, RGB / YC conversion processing, and image synthesis processing. Unit 75, a compression / decompression processing unit 77 that compresses the captured image into a JPEG image or expands the compressed image, an integration unit 79 that integrates photometric data and obtains the gain of white balance correction performed by digital signal processing unit 75 , An external memory control unit 83 to which a detachable recording medium 81 is connected, and a display control unit 87 to which a liquid crystal display unit 85 mounted on the rear surface of the camera is connected. These include a control bus 89 and a data bus. 91 are connected to each other and controlled by a command from the CPU 49.

  When a subject image is picked up by the digital camera according to the present embodiment, each photoelectric conversion element 2 shown in FIG. 1 accumulates signal charges corresponding to the amount of received light, and the signal charges are first read out to the VCCD 3, and the HCCD 5 along the VCCD 3. Forward in the direction of.

  At the timing immediately before each signal charge is read out to the VCCD 3, each of the VCCD 3 and the HCCD 5 is in an empty state due to the sweep-out operation. After the readout processing of the injected predetermined charge amount, the signal charge corresponding to the received light amount of each pixel is read from the solid-state imaging device 100, and the digital signal processing unit 75 generates subject image data.

  According to this digital camera, since the solid-state imaging device 100 and the optical system that forms an optical image on the solid-state imaging device 100 are provided, transfer efficiency is not deteriorated, high-speed operation can be realized, and noise is excellent. Can acquire high-speed images. Further, the output signal difference can be corrected with high accuracy using a uniform reference signal, and a good image can be obtained.

  The present invention is a CCD type solid-state imaging device. In particular, the horizontal charge transfer unit is divided into at least three blocks, and the signal charges transferred in the blocks are floated downstream of each block in the signal charge transfer direction. Low power consumption and easy design for solid-state imaging devices connected to output units that detect and output by diffusion, and can enhance stray light shielding. For example, it can be applied to electronic cameras, video cameras, mobile terminals, etc. It is effective for use.

FIG. 3 is a schematic plan view of a portion excluding a stack above a semiconductor substrate of a CCD type solid-state imaging device for explaining an embodiment of the present invention. It is the enlarged view which represented the structural example for 1 block of HCCD5 shown in FIG. 1 by (a), (b). It is an AA arrow line view of FIG. It is an enlarged view of the HCCD vicinity which added the dummy transfer part. It is a block diagram of the digital camera carrying the solid-state image sensor which concerns on this invention.

Explanation of symbols

2 Photoelectric conversion element (photoelectric conversion unit)
3 VCCD (vertical charge transfer unit)
5 HCCD (horizontal charge transfer unit)
5b Three blocks 8 Output unit 13, 13A, 13B Light shielding film 16 FD (floating diffusion)
25 Dummy transfer unit 53 Light receiving unit 100 Solid-state imaging device HD1, HD2, HD3 First, second and third dummy electrodes (multiple transfer electrodes)
OG Output gate electrode X Row direction Y Column direction

Claims (5)

A light receiving unit having a plurality of photoelectric conversion units, a plurality of vertical charge transfer units that transfer signal charges read from the plurality of photoelectric conversion units in a column direction, and a signal charge that has been transferred through the vertical charge transfer units A solid-state imaging device having a horizontal charge transfer unit that transfers a signal in a row direction orthogonal to the column direction,
Each of the horizontal charge transfer units is divided into at least three blocks for transferring the signal charges, and the signal charges transferred in the blocks are detected by floating diffusion on the downstream side in the signal charge transfer direction of each block. Are connected to each output unit,
Each output unit includes a dummy transfer unit that extends in a direction away from the horizontal transfer electrode and connects the horizontal charge transfer unit and the floating diffusion.
A solid-state imaging device in which at least the horizontal charge transfer unit and the dummy transfer unit are covered with the same light-shielding film. The solid-state imaging device according to claim 1,
A solid-state imaging device in which the dummy transfer unit includes a plurality of transfer electrodes. The solid-state imaging device according to claim 1 or 2,
A solid-state imaging device in which the dummy transfer unit is connected to a transfer electrode of the horizontal charge transfer unit, and signal charges are transferred in synchronization with a drive signal of the horizontal charge transfer unit. The solid-state imaging device according to any one of claims 1 to 3,
An output gate electrode is connected to the downstream end of the dummy transfer portion in the charge transfer direction,
A solid-state imaging device in which the light shielding film covers up to a connection position of the dummy transfer section with the output gate electrode. The solid-state image sensor according to any one of claims 1 to 4,
An optical system for forming an optical image on the solid-state imaging device;
An imaging apparatus comprising:

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