JP2009054847A - A solid-state imaging device and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein a solid-state imaging device has a line memory with less charge transfer capacity of a horizontal charge transfer path, larger power consumption, and deterioration in transfer efficiency. <P>SOLUTION: In the solid-state imaging device 100 having the line memory 23 which is provided at the downstream ends of vertical charge transfer sections 22, in a signal charge transfer direction and temporarily stores transferred signal charges; the line memory 23 has a transfer channel region where the potential gradient of a potential that gradually decreases in the signal charge transfer direction is formed; a gate electrode disposed opposite the transfer channel area; and a plurality of memory control electrodes extended in the array direction of a plurality of line memories 23 and electrically connected to a gate electrode with respect a prescribed line memory 23; a contact portion between the memory control electrodes; and gate electrode being formed upstream in the charge transfer direction by half the length of the transfer channel area in the charge transfer direction. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a photoelectric conversion element, a number of vertical charge transfer paths for transferring charges generated in the photoelectric conversion element in the vertical direction, and a charge transferred through the vertical charge transfer path in a horizontal direction orthogonal to the vertical direction. The present invention relates to a solid-state imaging device having a horizontal charge transfer path for transferring in a direction.

FIG. 13 is a partially enlarged view of a general solid-state image sensor.
The solid-state imaging device shown in FIG. 13 includes a photoelectric conversion element (not shown) arranged two-dimensionally on a semiconductor substrate, a number of vertical charge transfer units 1 that transfer charges generated in the photoelectric conversion element in the vertical direction Y, A horizontal charge transfer unit 2 that transfers charges transferred through the vertical charge transfer unit 1 in a horizontal direction X orthogonal to the vertical direction Y, a charge storage region 3 that connects the vertical charge transfer unit 1 and the horizontal charge transfer unit 2, and And a line memory LM including a memory electrode 4 formed above the charge storage region 3. The vertical charge transfer unit 1, the charge storage region 3, and the horizontal charge transfer unit 2 are configured by n-type impurity layers.

  Above the horizontal charge transfer section 2, a plurality of electrode sets are arranged in the horizontal direction X in which inverted L-shaped electrodes 5 and rectangular electrodes 6 are arranged in this order in the horizontal direction X. This electrode set includes a first electrode set to which the transfer pulse φH1 is applied and a second electrode set to which the transfer pulse φH2 is applied, which are alternately arranged in the horizontal direction X. When the transfer pulse φH1 is at a high level and the transfer pulse φH2 is at a low level, the horizontal charge transfer unit 2 below the first electrode set operates as a charge storage region capable of storing charges, and the horizontal charge below the second electrode set The transfer unit 2 operates as a barrier region between the charge storage regions. On the other hand, when the transfer pulse φH1 is at a low level and the transfer pulse φH2 is at a high level, the horizontal charge transfer unit 2 below the second electrode set operates as a charge storage region capable of storing charges, and below the first electrode set. The horizontal charge transfer unit 2 operates as a barrier region between the charge storage regions. As described above, the horizontal charge transfer unit 2 is formed with a plurality of charge transfer stages that operate as a barrier region or a charge storage region according to the level of the applied voltage by the first electrode set and the second electrode set. ing.

  Patent Document 1 discloses a solid-state imaging device having a vertical charge transfer path, a line memory, and a horizontal charge transfer path.

JP 2007-27977 A

  The solid-state imaging device having the configuration shown in FIG. 13 is provided with one charge transfer stage corresponding to one vertical charge transfer unit 1. For this reason, when the pixel size is reduced without changing the horizontal width of the horizontal charge transfer unit 2 corresponding to the increase in the number of pixels, the horizontal width of the charge transfer stage (the portion indicated by P in FIG. 13). Decreases, and the charge transfer capacity of the horizontal charge transfer unit 2 decreases. In order to secure the charge transfer capacity, it is conceivable to increase the width of each charge transfer stage. However, in this case, since the entire width of the horizontal charge transfer unit 2 is expanded in the horizontal direction, consumption due to an increase in electrostatic capacity. An increase in power will occur. In addition, since the number of charge transfer stages increases corresponding to the increase in the number of pixels, there is a concern that transfer efficiency may deteriorate when high-speed driving is performed.

  The present invention has been made in view of the above circumstances, and even when the number of pixels is increased without increasing the size of the horizontal charge transfer path, the charge transfer capacity of the horizontal charge transfer path is reduced and the power consumption is increased. An object of the present invention is to provide a solid-state imaging device capable of solving problems such as deterioration of transfer efficiency.

The above object of the present invention is achieved by the following configuration.
(1) A large number of photodiodes arranged in a row direction and a column direction orthogonal thereto, a plurality of vertical charge transfer units that transfer signal charges generated in the photodiodes in the column direction, and the vertical charge transfer units A plurality of line memories that temporarily store signal charges to be transferred and a horizontal charge transfer unit that transfers signal charges read from the plurality of line memories in the row direction. A solid-state imaging device having
The line memory includes a transfer channel region in which a potential slope in which a potential potential gradually increases toward a signal charge transfer direction;
A gate electrode disposed facing the transfer channel region;
A plurality of memory control electrodes extending along an arrangement direction of the plurality of line memories and electrically connected to gate electrodes for line memories belonging to a predetermined group of the line memories;
A solid-state imaging device in which a contact portion between the memory control electrode and the gate electrode is formed on the upstream side in the charge transfer direction with respect to half the length of the transfer channel region in the charge transfer direction.

  According to this solid-state imaging device, the number of pixels can be increased without enlarging the size of the horizontal charge transfer path only by limiting the arrangement position of the contact portion without requiring the film formation process of the diffusion / reaction prevention film. Even in this case, problems such as a decrease in charge transfer capacity of the horizontal charge transfer path, an increase in power consumption, and a deterioration in transfer efficiency are solved.

(2) The solid-state imaging device according to (1),
The memory control electrode includes a first memory control electrode to which a voltage can be applied independently, and a second memory control electrode,
A solid-state imaging device in which the first memory control electrode and the second memory control electrode are alternately connected to the gate electrode of the line memory along the arrangement direction of the line memory.

  According to this solid-state imaging device, different line memory pulses can be applied to the first memory control electrode and the second memory control electrode, and the line memory pulses can take a high level state and a low level state, respectively.

(3) The solid-state imaging device according to (1) or (2),
A solid-state imaging device in which signal charges transferred by the plurality of vertical charge transfer units are introduced into one charge transfer stage of the horizontal charge transfer unit through the line memory.

  According to this solid-state imaging device, voltage is independently applied to a plurality of electrodes above the charge accumulation region connected to the vertical charge transfer unit, thereby selecting a charge to be transferred to the horizontal charge transfer path in the line memory. It becomes possible.

(4) The solid-state imaging device according to any one of (1) to (3);
An optical system for forming an optical image on the solid-state imaging device;
An imaging apparatus comprising:

  According to this imaging apparatus, transfer efficiency is not deteriorated, high speed operation is realized, and a good image without noise can be acquired at high speed.

  According to the solid-state imaging device according to the present invention, even when the number of pixels is increased without increasing the size of the horizontal charge transfer path, the charge transfer capacity of the horizontal charge transfer path is decreased, the power consumption is increased, and the transfer efficiency is increased. It becomes possible to solve problems such as deterioration. In addition, since the contact portion between the memory control electrode and the gate electrode is formed on the upstream side in the charge transfer direction from half the length of the transfer channel region in the charge transfer direction, transfer efficiency does not deteriorate and high speed operation can be realized. At the same time, since the step of forming the diffusion / reaction prevention film is not required, the yield can be improved while reducing the number of steps.

  According to the imaging apparatus according to the present invention, since the solid-state imaging device and the optical system that forms an optical image on the solid-state imaging device are provided, a good image can be acquired at low cost at high speed.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a solid-state imaging device and an imaging device according to the invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a basic configuration of a solid-state imaging device according to the present invention.
The solid-state imaging device 100 according to the present embodiment has an imaging in which a large number of photoelectric conversion elements 20 are two-dimensionally arranged so as to be aligned along a row direction (direction of arrow X) and a column direction (direction of arrow Y) on a plane. Part 21. Each photoelectric conversion element 20 is a photodiode usually made of a semiconductor, and generates a signal charge corresponding to the amount of light determined by the intensity of light incident on each light receiving surface and the length of exposure time. That is, the amount of signal charge generated by each of the plurality of photoelectric conversion elements 20 corresponds to the brightness of each pixel constituting the two-dimensional image.

  In order to take out signal charges output from each of a large number of two-dimensionally arranged photoelectric conversion elements 20 from the output terminal OUT of the solid-state imaging element 100 as signals in time series in an appropriate order, a plurality of vertical charge transfer units The solid-state imaging device 100 includes (VCCD) 22 (1) to 22 (n), a line memory (LM) 23, a horizontal charge transfer unit (HCCD) 24, and an output amplifier 25.

  Each vertical charge transfer unit 22 extends in the Y direction at a position adjacent to the photoelectric conversion element 20, and receives a signal charge from each of the photoelectric conversion elements 20 for one column, and then The signal charges are sequentially transferred in the vertical direction (arrow Y direction).

  A line memory 23 is arranged on the output side of the vertical charge transfer units 22 (1) to 22 (n), and one row of signal charges output from the vertical charge transfer units 22 (1) to 22 (n). Is temporarily stored in the line memory 23.

  The signal charges for one row accumulated in the line memory 23 are transferred from the line memory 23 to the horizontal charge transfer unit 24, and as a result, the signal charges for one row are held in the horizontal charge transfer unit 24. The horizontal charge transfer unit 24 sequentially transfers signal charges for one row held by the horizontal charge transfer unit 24 in the horizontal direction (arrow X direction) in units of one pixel. The signal charge output from the horizontal charge transfer unit 24 is amplified by the output amplifier 25 and sent to the output terminal OUT.

  Control signals necessary for realizing such a read operation, that is, vertical transfer control signals φV1 to φV8, line memory transfer control signals φLM1 and φLM2, and horizontal transfer control signals φH1 and φH2, respectively, are predetermined timing signals. Generated by the generation circuit 26 and applied to the vertical charge transfer unit 22, the line memory 23, and the horizontal charge transfer unit 24 of the solid-state imaging device 100.

Here, a more specific configuration example of the solid-state imaging device 100 will be described below with reference to FIGS.
FIG. 2 is a partial plan view schematically showing the configuration of the solid-state image sensor.
In the solid-state imaging device 100, the line memory 23 includes a charge storage region 27 that connects each of the large number of vertical charge transfer units 22 and the horizontal charge transfer unit 24, and a memory control electrode provided independently above the charge storage region 27. 28 (first memory control electrode 28a, second memory control electrode 28b). The vertical charge transfer unit 22, the charge storage region 27, and the horizontal charge transfer unit 24 are configured by, for example, an n-type impurity layer formed in a p-well layer formed on an n-type semiconductor substrate.

  Above the horizontal charge transfer section 24, a plurality of electrode sets in which the inverted L-shaped electrode 29a and the rectangular electrode 29b are arranged in the horizontal direction X in this order are arranged in the horizontal direction X. This electrode set includes an electrode set D1 to which the transfer pulse φH2 is applied and an electrode set D2 to which the transfer pulse φH1 is applied, and these are alternately arranged in the horizontal direction X. When the transfer pulse φH2 becomes high level and the transfer pulse φH1 becomes low level, the horizontal charge transfer unit 24 below the electrode set D1 operates as a charge storage region capable of storing charges, and the horizontal charge transfer unit 24 below the electrode set D2 It operates as a barrier region between the charge storage regions. On the other hand, when the transfer pulse φH2 is at a low level and the transfer pulse φH1 is at a high level, the horizontal charge transfer unit 24 below the electrode set D2 operates as a charge storage region capable of storing charges, and the horizontal charge transfer unit below the electrode set D1. 24 operates as a barrier region between the charge storage regions. As described above, in the horizontal charge transfer section 24, a plurality of charge transfer stages that operate as a barrier region or a charge storage region according to the level of the applied voltage are formed by the overlapping portion of the electrode set D1 and the electrode set D2. .

  Each of the adjacent vertical charge transfer units 22 is connected to each charge transfer stage of the horizontal charge transfer unit 24 via a charge storage region 27. Of the two charge storage regions 27 connected to each charge transfer stage, the line memory pulse φLM1 is applied above the charge storage region 27 on the upstream side (right side in the drawing) of the horizontal charge transfer unit 24 in the charge transfer direction. A memory control electrode 28a to which the line memory pulse φLM2 is applied is formed above the charge storage region 27 on the downstream side (left side in the figure) of the horizontal charge transfer unit 24 in the charge transfer direction. ing. The line memory pulses φLM1 and φLM2 can take a high level state and a low level state, respectively.

Hereinafter, the operation of the solid-state imaging device 100 having such a configuration will be described.
FIG. 3 is a diagram for explaining the charge transfer operation from the line memory of the solid-state imaging device shown in FIG. 2 to the horizontal charge transfer path. In FIG. 3, the timing chart of the transfer pulses φH1 and φH2 and the line memory pulses φLM1 and φLM2 is shown on the left side, and the state of charge at each timing shown on the left side is shown on the right side. Here, the case where the arrangement of the photoelectric conversion elements 20 included in the solid-state imaging element 100 is a honeycomb arrangement as disclosed in JP 2007-27977 A will be described as an example. Note that the honeycomb arrangement is a photoelectric conversion element row composed of photoelectric conversion elements arranged in the row direction as an arrangement of photoelectric conversion elements, and the odd-numbered rows and the even-numbered rows have a pitch between the photoelectric conversion elements in the row direction. The arrangement is approximately ½ shifted in the row direction.

  FIG. 3A shows a state where charges obtained from the photoelectric conversion elements 20 for two lines of the solid-state imaging device 100 are accumulated in a large number of charge accumulation regions 27. In this state, φH1 and φH2 are at a low level, φLM1 and φLM2 are at a high level, a potential well is formed in the charge storage region 27, and each charge transfer stage of the horizontal charge transfer unit 24 forms a barrier for this potential well. Forming.

  Next, as shown in FIG. 3 (b), φLM2 is set to a low level and φH2 is set to a high level, and the charge accumulation stage below the memory control electrode 28b corresponding to the charge transfer stage is set in the charge transfer stage below the electrode set D1. The charge “R” in the region 27 is moved. Thereafter, φH2 is set to the low level and φH1 is set to the high level to transfer the charge “R” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “R” is transferred to the horizontal charge. Is output from the output amplifier 25 connected to the end of the unit 24.

  After the signal corresponding to the charge “R” is output, φLM2, φLM1, φH1, and φH2 are set to the state shown in FIG. 3A, then φLM1 is set to the low level and φH2 is set to the high level, as shown in FIG. At a level, the charge “G1” in the charge storage region 27 below the memory control electrode 28a corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D1. Thereafter, φH2 is set to the low level and φH1 is set to the high level to transfer the charge “G1” to the adjacent charge transfer stage. By repeating such transfer operation, the signal corresponding to the charge “G1” is transferred to the horizontal charge. Is output from the output amplifier 25 connected to the end of the unit 24.

  After the signal corresponding to the charge “G1” is output, φLM2, φLM1, φH1, and φH2 are once set to the state shown in FIG. 3A, and then, as shown in FIG. At a level, the charge “B” in the charge storage region 27 below the memory control electrode 28b corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D2. Thereafter, φH1 is set to low level and φH2 is set to high level to transfer the charge “B” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “B” is transferred to the horizontal charge. Is output from the output amplifier 25 connected to the end of the unit 24.

  After the signal corresponding to the charge “B” is output, φLM2, φLM1, φH1, and φH2 are set to the state shown in FIG. 3A, then φLM1 is set to the low level and φH1 is set to the high level, as shown in FIG. At a level, the charge “G2” in the charge storage region 27 below the memory control electrode 28a corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D2. Thereafter, φH1 is set to low level and φH2 is set to high level to transfer the charge “G2” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “G2” is transferred to the horizontal charge. Is output from the output amplifier 25 connected to the end of the unit 24.

  With this operation, the transfer of charges for two lines is completed.

  In the solid-state imaging device 100 described above, two vertical charge transfer units 22 are connected to one charge transfer stage, and the memory control electrodes 28a and 28b above the charge storage region 27 connected to the two vertical charge transfer units 22 are connected. By allowing each voltage to be applied independently, it is possible to select the charge transferred to the horizontal charge transfer unit 24 by the line memory 23. For this reason, even when the same pixel pitch as in FIG. 13 is realized, the horizontal width (W in FIG. 2) of the charge transfer stage is shown in FIG. 13 while maintaining the horizontal width of the horizontal charge transfer section 24. Can be expanded more than the ones. As a result, the charge transfer capacity of the horizontal charge transfer unit 24 can be increased without increasing the power consumption. In addition, since the number of charge transfer stages can be reduced, it is possible to prevent deterioration in transfer efficiency.

  In the solid-state imaging device 100 described above, the memory electrodes of the line memory 23 are divided into the memory control electrode 28a and the memory control electrode 28b to which voltages can be applied independently, so that the line memory pulses φLM1 and φLM2 are By controlling, it is possible to distribute charges from the line memory 23 to the horizontal charge transfer unit 24. When multi-field reading is performed with the configuration shown in FIG. 13, the driving of the vertical charge transfer unit 1 becomes complicated. However, according to the configuration shown in FIG. 2, the driving of the vertical charge transfer unit 22 is complicated. Therefore, multi-field reading can be realized only by controlling the line memory pulses φLM1 and φLM2. Further, by controlling the line memory pulses φLM1 and φLM2, it is possible to easily realize thinning driving and the like. Thus, by providing a plurality of types of memory electrodes, various driving methods can be easily realized.

  As described above, the solid-state imaging device 100 according to the present embodiment obtains a transfer pitch by the horizontal charge transfer unit 24 by using the memory control electrode 28 (28a, 28b) in which a plurality of electrodes of the line memory 23 are formed. Although securing the capacity of the horizontal charge transfer portion 24 and improving the transfer efficiency, there is a concern that it may include a new problem due to a change in work function in the contact portions of the memory control electrodes 28a and 28b. That is, in order to alternately arrange a plurality of memory control electrodes 28a and 28b and drive them independently, it is necessary to connect the gate electrode to the memory control electrodes 28a and 28b. If it is provided on the line memory charge transfer channel, there arises a problem that the work function of the electrode in the contact portion changes and transfer efficiency deteriorates.

  On the other hand, a transfer diffusion / reaction prevention film is formed between the transfer electrode made of polycrystalline silicon and the gate electrode so that the work function does not change, thereby preventing transfer efficiency from deteriorating. A technique (for example, Japanese Patent Laid-Open No. 7-211883) has been proposed, but in this method, a step of forming a diffusion / reaction prevention film is added, resulting in a decrease in yield due to the addition of the step.

Therefore, the solid-state imaging device 100 according to the present embodiment solves these problems by further adding the following configuration.
4 is an enlarged view of a main part of the line memory shown in FIG. 2, and FIG. 5 is a cross-sectional view taken along line AB in FIG.
In the imaging unit 21, the plurality of vertical charge transfer units 22 are separated by a pixel separation band 30. Between the vertical charge transfer units 22, a plurality of photoelectric conversion elements 20 are provided along the charge transfer direction of the vertical charge transfer unit 22. Each photoelectric conversion element 20 is connected to a vertical charge transfer upper electrode 31 a and a vertical charge transfer lower electrode 31 b in a direction orthogonal to the vertical charge transfer unit 22. The vertical charge transfer unit 22 performs eight-phase driving in which vertical transfer signals φV1 to φV8 are input to the vertical charge transfer upper electrode 31a and the vertical charge transfer lower electrode 31b.

  A line memory 23 having a line memory charge transfer channel 32 is provided between each vertical charge transfer unit 22 and horizontal charge transfer unit 24. The line memory 23 gradually increases the width of the line memory charge transfer channel 32 so that a potential slope is formed in the charge transfer direction. As shown in JP-A-2002-185870, a potential slope can be applied by implanting impurities or by channel stop. Each line memory 23 is provided with memory control electrodes 28 a and 28 b in a direction orthogonal to the charge transfer direction, and the memory control electrodes 28 a and 28 b are connected to the gate electrode at the contact portion 33. Line memory control signals φLM1 and φLM2 are input to the memory control electrodes 28a and 28b. In the figure, 34 indicates a channel stop.

  As shown in FIG. 5B, the arrangement position of the contact portion 33 shown in FIG. 5A is a part of the line memory charge transfer channel 32 that is out of the charge accumulation region due to the potential potential well. It has become.

  Since the contact part 33 is formed by bonding different kinds of materials, both the materials are distributed. Since the work function varies depending on the material, the work function becomes higher or lower in the diffused region than the surroundings. If the state is compared with the potential of the electric potential, it becomes a shape like a dip (concave; well) or a barrier (convex; barrier). That is, the work function can be considered as a parameter representing the height of the potential potential. When the work function is large, this is equivalent to a low potential state. In order to transfer signal charges by changing the work function in this way, a well is formed by increasing the work function of the object surface, and a barrier is formed by decreasing the work function. Actually, a transfer path is formed by adjusting the ion implantation concentration, and the signal charge is moved by moving the potential up and down by applying a voltage to the electrode.

  In the line memory 23, as shown in FIG. 5B, the barrier BA becomes high and the charge accumulation region 35 is formed during line memory accumulation in the horizontal charge transfer section 24 when the electrode 29a has φH1 low and φLM1 low. The Further, as shown in FIG. 5C, the barrier BA is lowered and the accumulated charge is transferred to the horizontal charge transfer unit 24 when the electrode 29a is transferred to the horizontal charge transfer unit 24 in which φH1 is High and φLM1 is Low. Is done.

Here, FIG. 6 is a schematic diagram showing the charge transfer process by the barrier formation of the line memory charge transfer channel in (a), (b), and (c), and FIG. 7 is the charge transfer by dip formation of the line memory charge transfer channel. It is the schematic diagram which showed the process to (a), (b), (c).
In the contact portion 33 shown in FIG. 5A, the work function changes due to trap levels due to crystal defects or contamination, potential unevenness due to a non-uniform structure, etc., and a barrier Ba or dip Da is formed. Although the potential potential distributions are different from each other, the behavior of charge transfer is almost the same in both cases. As shown in FIGS. 6 and 7, the charge blocked or accumulated by the barrier Ba or dip Da is transferred in the horizontal charge within the period from the line memory accumulation to the horizontal charge transfer unit 24. The transfer gradually proceeds to the unit 24 and is completely transferred with the passage of time, resulting in no residual noise. That is, in the barrier Ba or the dip Da, charges are transferred even if there is a potential step due to thermal diffusion and fringe electric field drift.

FIG. 8 is a schematic diagram showing the correlation between the length and width of the line memory charge transfer channel.
When the channel widths W1 and W2 are continuously widened in the transfer direction, the contact portion 33 is disposed in a region having a width narrower than the intermediate width (W1 + W2) / 2 of the channel width (on the upper side in the figure). A region of length S) may be used.

FIG. 9 is a schematic diagram showing the correlation between the charge storage region of the line memory charge transfer channel and the length in the charge transfer direction.
Furthermore, the arrangement position of the contact portion 33 may be formed on the upstream side in the charge transfer direction (the region of the length S on the right side in the drawing) from half the length of the line memory charge transfer channel 32 in the charge transfer direction. That is, in any case, the contact portion 33 is not disposed in the substantial charge storage region. The charge storage region is difficult to define accurately because it varies depending on the ion concentration in the channel, etc., but it is designed at least downstream of the length of the line memory charge transfer channel 32 in the charge transfer direction. Therefore, the contact portion 33 is not disposed at that region.

  By disposing the contact portion 33 at the specified position, the contact portion 33 is disposed upstream of the charge accumulation region 35 even if the barrier Ba or the dip Da occurs due to a change in the work function in the vicinity of the contact portion. Therefore, the charge of the barrier Ba or the dip Da changes with time due to thermal diffusion and fringe electric field drift within the transfer period from the period in which the charge is accumulated in the line memory 23 to the horizontal charge transfer unit 24. It will be transferred reliably.

10A and 10B are schematic diagrams showing the charge transfer process by barrier formation during small signal accumulation, and FIG. 11 is a charge transfer in a configuration in which a contact portion is provided in the charge accumulation region. It is the schematic diagram by the comparative example which showed the process to (a), (b), (c).
When the contact portion 33 is arranged on the upstream side in the charge storage region 35, even if the barrier Ba or the dip Da occurs due to a change in the work function in the vicinity of the contact portion, the transfer efficiency due to the dip Da or the like is remarkably deteriorated. 10B, since the contact portion 33 is disposed upstream of the charge storage region 35, the horizontal charge from the period in which the charge is stored in the line memory 23 is displayed. Within the transfer period to the transfer unit 24, the charges in the dip Da are transferred due to thermal diffusion and fringe field drift.

  On the other hand, as shown in FIG. 11, when the contact portion 33 is arranged on the downstream side of the charge storage region 35, the charge in the dip Da is not transferred during the period in which the charge is stored in the line memory 23. The charge in the dip Da cannot be transferred in a short period that is only in the transfer period to the horizontal charge transfer unit 24. For this reason, in order to transfer the charge in the dip Da, it is necessary to extend the transfer period to the horizontal charge transfer unit 24. This also proves that the configuration according to the present embodiment is effective.

  Therefore, according to the solid-state imaging device 100 according to the present embodiment, the contact portion 33 between the memory control electrodes 28a and 28b and the gate electrode is transferred from half the length of the line memory charge transfer channel 32 region in the charge transfer direction. Since it is formed on the upstream side in the direction, even when the contact part 33 whose work function is changed is connected to the line memory 23 in the memory control electrodes 28a and 28b having a plurality of electrodes, the transfer efficiency is not deteriorated. High-speed operation can be realized. In addition, since the step of forming the diffusion / reaction prevention film is not required, the yield can be improved while reducing the number of steps.

Next, a digital camera that is an image pickup apparatus including the solid-state image pickup device 100 according to the above-described embodiment will be described.
FIG. 12 is a block diagram of a digital camera equipped with a solid-state image sensor according to the present invention.
The digital camera shown in the figure includes a photographic lens 41, the above-described solid-state imaging device 100, a diaphragm 43 provided therebetween, an infrared cut filter 45, and an optical low-pass filter 47. A CPU 49 that performs overall control of the entire digital camera controls the flash light emitting unit 51 and the light receiving unit 53, controls the lens driving unit 55 to adjust the position of the photographing lens 41 to the focus position, and controls the aperture via the aperture driving unit 57. The amount of opening 43 is controlled to adjust the exposure amount.

  Further, the CPU 49 drives the solid-state image sensor 100 via the image sensor driving unit 59 and outputs the subject image captured through the photographing lens 41 as a color signal. An instruction signal from the user is input to the CPU 49 through the operation unit 61, and the CPU 49 performs various controls according to the instruction.

  The electric control system of the digital camera includes an analog signal processing unit 67 connected to the output of the solid-state imaging device 100, and an A / D conversion circuit that converts RGB color signals output from the analog signal processing unit 67 into digital signals. 69, and these are controlled by the CPU 49.

  Further, the electric control system of the digital camera includes a memory control unit 73 connected to a main memory (frame memory) 71 and digital signal processing for performing image processing such as gamma correction calculation, RGB / YC conversion processing, and image synthesis processing. Unit 75, a compression / decompression processing unit 77 that compresses the captured image into a JPEG image or expands the compressed image, an integration unit 79 that integrates photometric data and obtains the gain of white balance correction performed by digital signal processing unit 75 , An external memory control unit 83 to which a detachable recording medium 81 is connected, and a display control unit 87 to which a liquid crystal display unit 85 mounted on the rear surface of the camera is connected. These include a control bus 89 and a data bus. 91 are connected to each other and controlled by a command from the CPU 49.

  When a subject image is captured by the digital camera according to the present embodiment, each pixel 20 shown in FIG. 1 accumulates signal charges corresponding to the amount of received light, and the signal charges are first read to the vertical charge transfer path 22 to transfer the vertical charges. Transfer along the path 25 in the direction of the horizontal charge transfer unit 24.

  At the timing immediately before each signal charge is read out to the vertical charge transfer path 22, each vertical charge transfer path 22 and the horizontal charge transfer unit 24 are in an empty state by the sweeping operation. After the readout processing of the injected predetermined charge amount, the signal charge corresponding to the received light amount of each pixel is read from the solid-state imaging device 100, and the digital signal processing unit 75 generates subject image data.

  According to this digital camera, since the solid-state imaging device 100 and the optical system that forms an optical image on the solid-state imaging device 100 are provided, transfer efficiency is not deteriorated, high-speed operation can be realized, and noise is excellent. Can acquire high-speed images. Further, the output signal difference can be corrected with high accuracy using a uniform reference signal, and a good image can be obtained.

  The present invention is a CCD type solid-state imaging device, and in particular, even when a contact portion with a variable work function is connected to a solid-state imaging device having a line memory control electrode with a plurality of electrodes, transfer efficiency can be improved. Deterioration does not occur and high-speed operation can be realized. For example, it is effective for use in an electronic camera, a video camera, a portable terminal, or the like.

It is a block diagram which shows the basic composition of the solid-state image sensor which concerns on this invention. Partial plan schematic diagram showing a schematic configuration of a solid-state imaging device FIG. 3 is a diagram for explaining a charge transfer operation from the line memory of the solid-state imaging device shown in FIG. 2 to a horizontal charge transfer path. FIG. 3 is an enlarged view of a main part of the line memory shown in FIG. 2. FIG. 5 is a cross-sectional view taken along line AB in FIG. 4. It is the schematic diagram which showed the charge transfer process by the barrier formation of a line memory charge transfer channel to (a), (b), (c). It is the schematic diagram which showed the charge transfer process by the dip formation of a line memory charge transfer channel to (a), (b), (c). It is the schematic diagram showing the correlation of the length and width of a line memory charge transfer channel. It is a schematic diagram showing the correlation between the charge accumulation region of the line memory charge transfer channel and the length in the charge transfer direction. It is the schematic diagram which showed the charge transfer process by barrier formation at the time of small signal accumulation | storage at (a), (b), (c). It is the schematic by the comparative example which showed the charge transfer process in the structure which arrange | positioned the contact part in the electric charge storage area | region, (a), (b), (c). It is a block diagram of the digital camera carrying the solid-state image sensor which concerns on this invention. It is the elements on larger scale of the conventional solid-state image sensor.

Explanation of symbols

20 Photoelectric conversion element (photodiode)
22 vertical charge transfer unit 23 line memory 24 horizontal charge transfer unit 28a first memory control electrode 28b second memory control electrode 32 line memory charge transfer channel (transfer channel region)
33 Contact part 100 Solid-state image sensor X Row direction Y Column direction

Claims (4)

A large number of photodiodes arranged in a row direction and a column direction orthogonal thereto, a plurality of vertical charge transfer units that transfer signal charges generated in the photodiodes in the column direction, and signal charges of the vertical charge transfer units A plurality of line memories that are respectively provided at the downstream ends in the transfer direction and temporarily store signal charges to be transferred; and a horizontal charge transfer unit that transfers signal charges read from the plurality of line memories in the row direction. A solid-state imaging device comprising:
The line memory includes a transfer channel region in which a potential slope in which a potential potential gradually increases toward a signal charge transfer direction;
A gate electrode disposed facing the transfer channel region;
A plurality of memory control electrodes extending along an arrangement direction of the plurality of line memories and electrically connected to gate electrodes for line memories belonging to a predetermined group of the line memories;
A solid-state imaging device in which a contact portion between the memory control electrode and the gate electrode is formed on the upstream side in the charge transfer direction with respect to half the length of the transfer channel region in the charge transfer direction. The solid-state imaging device according to claim 1,
The memory control electrode includes a first memory control electrode to which a voltage can be applied independently, and a second memory control electrode,
A solid-state imaging device in which the first memory control electrode and the second memory control electrode are alternately connected to the gate electrode of the line memory along the arrangement direction of the line memory. The solid-state imaging device according to claim 1 or 2,
A solid-state imaging device in which signal charges transferred by the plurality of vertical charge transfer units are introduced into one charge transfer stage of the horizontal charge transfer unit through the line memory. The solid-state image sensor according to any one of claims 1 to 3,
An optical system for forming an optical image on the solid-state imaging device;
An imaging apparatus comprising:

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