JP2009088288A - Charge transfer element, solid-state image sensor and imaging device - Google Patents

Charge transfer element, solid-state image sensor and imaging device Download PDF

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JP2009088288A
JP2009088288A JP2007256704A JP2007256704A JP2009088288A JP 2009088288 A JP2009088288 A JP 2009088288A JP 2007256704 A JP2007256704 A JP 2007256704A JP 2007256704 A JP2007256704 A JP 2007256704A JP 2009088288 A JP2009088288 A JP 2009088288A
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charge transfer
charge
reset
unit
transfer element
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JP2009088288A5 (en
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Tsuneo Sasamoto
恒夫 笹本
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Fujifilm Corp
富士フイルム株式会社
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Abstract

In a charge transfer element (reset transistor) of a charge detection unit formed of a depletion type MOS transistor, on-resistance is reduced during reset to reliably discharge residual signal charge, and the charge transfer element is discharged during signal charge accumulation. Provided are a charge transfer device, a solid-state imaging device, and an imaging device that are surely turned off and have both reset characteristics and low noise characteristics.
A charge transfer element includes a charge injection part (floating diffusion layer), a reset drain part, and a reset gate part that resets the potential of the charge injection part. A channel depth suppression layer 92 for limiting the above is disposed below the reset gate portion 90 at a position shallower than the conductive type well layer 72 or with a higher impurity concentration than the conductive type well layer 72.
[Selection] Figure 2

Description

  The present invention relates to a charge transfer device, a solid-state imaging device, and an imaging device, and more particularly to a technique for combining excellent reset characteristics and low noise characteristics.

  2. Description of the Related Art Conventionally, in a solid-state imaging device such as a CCD (Charge Coupled Device) type solid-state imaging device, a depletion is used as a reset transistor (charge transfer device) of a charge detection unit that converts a signal charge from a charge transfer unit into a signal voltage and outputs the signal voltage. A type using a MOS (Metal Oxide Semiconductor) transistor is known (for example, see Patent Document 1).

As shown in FIG. 7, such a charge detection unit includes an N + type semiconductor region 16 formed on the surface of the N type semiconductor layer 12 on the P well layer 10. The N + type semiconductor region 16 forms a floating diffusion layer (floating diffusion: FD), and an output amplifier 20 is connected to the floating diffusion layer 16. The output amplifier 20 uses a source follower using a MOS transistor. In the figure, VFD represents the potential of the floating diffusion layer 16. The N + type semiconductor region 18 that receives signal charges from the N + type semiconductor region 16 constitutes a reset drain (RD), and the reset drain (RD) 18 is set to the reset drain potential VRD. The electrode 22 constitutes a reset gate (RG), and a reset gate signal φRG is applied to the reset gate (RG) 22. That is, a charge transfer element (reset transistor) 32 that operates in the depletion mode is formed by the floating diffusion layer 16, the reset drain (RD) 18, and the reset gate (RG) 22.

  A drive pulse φ1 is applied to the electrodes 24 and 28 of the horizontal charge transfer section, and a drive pulse φ2 is applied to the electrode 26. The electrode 30 is a horizontal transfer output gate, and a predetermined DC voltage VOG is constantly applied to the electrode 30. In the figure, Q indicated by a dotted line is a signal charge, and an arrow indicates the movement (transfer) of the signal charge Q.

  By sequentially switching the voltage of each signal (φ1, φ2) applied to the solid-state imaging device from the outside according to a predetermined control procedure, the signal charge Q floats in the horizontal charge transfer section as indicated by an arrow in FIG. The signal charge transferred toward the diffusion layer 16 and transferred to the position of the floating diffusion layer 16 is output from the output amplifier 20 as a voltage corresponding to the amount of the signal charge Q.

  The charge transfer element 32 configured as described above is on / off controlled in accordance with the timing of the reset gate signal φRG applied to the reset gate 22. When the voltage is not applied to the reset gate 22, the signal charge Q of the floating diffusion layer 16 is discharged to the reset drain (RD) 18 through the on-resistance of the charge transfer element 32, and a negative voltage is applied to the reset gate 22. When turned off, the charge transfer element 32 is turned off in the depletion layer formed by the negative voltage. That is, it is controlled as a normally-on element.

Japanese Patent Laid-Open No. 8-23039

  However, the charge transfer element 32 operating in the depletion mode can discharge the remaining signal charge reliably when the charge is reset, but has a characteristic that it is difficult to be completely turned off when the signal charge is accumulated. The charge transfer element 32 that is normally on (normally on) is turned off by applying a negative voltage to the reset gate 22. This switching operation will be described with reference to FIGS. As shown in FIG. 8, when a negative voltage is applied to the reset gate 22, a depletion layer 34 is formed in the N-type semiconductor layer 12 between the floating diffusion layer 16 and the reset drain (RD) 18, and the charge transfer element 32. Is turned off.

  However, since the charge transfer element 32 in the depletion mode has a deep current path, when the negative voltage (−Va) applied to the reset gate 22 is small, the depletion layer 34 is small as shown in FIG. Leakage occurs and the off state becomes insufficient. In order to ensure the off state, it is necessary to apply a large negative voltage (−Vb) to the reset gate 22 as shown in FIG.

  FIG. 9 shows the potential potential in the B1-B2 cross section shown in FIG. As shown in FIG. 9, since the reset gate 22 is provided on the surface side of the N-type semiconductor layer 12, the potential potential at a deep position of the N-type semiconductor layer 12 is raised by a negative voltage applied to the reset gate 22 ( A large negative voltage (−Vb) must be applied to ensure an off state (which changes to the negative potential side).

  When a large negative voltage (−Vb) is applied to the reset gate 22, as shown in FIG. 8B, extra charge / discharge occurs according to the parasitic capacitance F of the charge transfer element 32, and the signal charge due to this discharge is reduced. There is a problem that noise accumulates in the floating diffusion layer 16 and becomes a noise generation source. In order to cope with this problem, it is possible to control the reset drain potential VRD biased to the power supply voltage level to be lowered in synchronization with the reset gate signal φRG (to be lowered at the time of signal charge accumulation). There is a problem that the signal control becomes complicated.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the on-resistance during reset in a charge transfer element (reset transistor) of a charge detection unit formed of a depletion type MOS transistor, thereby reducing the residual signal charge. A charge transfer element that ensures both reset characteristics and low noise characteristics by reliably turning off the charge transfer element during signal charge accumulation, and a solid-state imaging device having the charge transfer element, and It is to provide an imaging apparatus provided.

The above object of the present invention is achieved by a charge transfer device, a solid-state imaging device, and an imaging device having the following configurations.
(1) a charge injection unit in which a signal charge is injected and a potential change is detected;
A reset drain part for receiving signal charges injected into the charge injection part;
A charge transfer element comprising: a reset gate unit that discharges the signal charge injected into the charge injection unit to the reset drain unit and resets the potential of the charge injection unit,
Below the reset gate, a charge transfer channel layer and a high-resistance conductivity type well layer are formed in this order,
A channel depth suppression layer for limiting a depletion layer depth of the charge transfer channel layer is disposed below the reset gate at a position shallower than the conductivity type well layer, or more impurity than the conductivity type well layer. A charge transfer element formed so as to satisfy at least one of arrangement with a high concentration.

  According to this charge transfer element, the charge transfer channel layer and the high-resistance conductivity type well layer are formed in this order below the reset gate, and the channel depth suppression layer disposed below the reset gate further includes the conductivity type well. It is disposed at a position shallower than the layer or with a higher impurity concentration than the conductive type well layer. As a result, even if the negative voltage applied to the reset gate is reduced, the charge transfer element can be surely turned off, and noise caused by the parasitic capacitance of the charge transfer element is suppressed and the reset characteristics and low noise characteristics are achieved. Thus, a charge transfer device that achieves both of the above can be obtained.

(2) The charge transfer device according to (1),
The charge transfer element in which the channel depth suppression layer below the reset gate is formed over the entire length from the charge injection portion to the reset drain.

  According to this charge transfer device, since the channel depth suppression layer is formed over the entire length from the charge injection portion to the reset drain, when forming the channel depth suppression layer by ion implantation processing or the like, The charge transfer element can be easily manufactured without requiring high alignment accuracy.

(3) The charge transfer device according to (1),
The channel depth suppression layer below the reset gate is such that the center of the length along the signal charge transfer direction from the charge injection portion to the reset drain is biased from the center of the reset gate toward the charge injection portion. The charge transfer element is arranged.

  According to this charge transfer device, since the channel depth suppression layer is disposed to be biased toward the charge injection portion from the center of the reset gate, the channel depth suppression layer can be disposed apart from the reset drain. As a result, the withstand voltage performance can be improved, and the parasitic capacitance can be reduced to suppress the generation of noise.

(4) The charge transfer device according to any one of (1) to (3),
The charge injection portion and the reset drain portion are N-type semiconductor layers;
A charge transfer element in which the conductive well layer and the channel depth suppression layer are made of a P-type semiconductor layer.

  According to this charge transfer element, the charge injection part and the reset drain part are N-type semiconductor layers, and the conductive well layer and the channel depth suppression layer are P-type semiconductor layers. Therefore, the charge transfer element is a depletion type N channel. It can be configured as a MOS transistor.

(5) A charge transfer element in which a reset transistor including the reset gate, the charge injection unit, and the reset drain is a depletion type MOS transistor.

  According to this charge transfer element, since the reset transistor including the reset gate, the charge injection portion, and the reset drain is composed of a depletion type MOS transistor, electrons can flow deep in the channel, reducing noise and reducing S. A charge transfer device having a high / N ratio can be obtained.

(6) A light receiving unit having a plurality of photoelectric conversion units, a plurality of vertical charge transfer units for transferring signal charges read from the plurality of photoelectric conversion units in a column direction, and the vertical charge transfer unit have been transferred. A solid-state imaging device having a horizontal charge transfer unit that transfers the signal charge in a row direction orthogonal to the column direction, and an output unit connected to a downstream side of the horizontal charge transfer unit in the charge transfer direction,
The output unit includes the charge transfer element according to any one of (1) to (5), and is a solid that is a floating diffusion in which the charge injection unit detects a signal charge transferred in the horizontal charge transfer unit. Image sensor.

  According to this solid-state imaging device, since it includes a light receiving unit, a vertical charge transfer unit, a horizontal charge transfer unit, and an output unit, and the charge injection unit of the charge transfer element of the output unit is a floating diffusion, It is possible to obtain a solid-state imaging device capable of obtaining a low output.

(7) The solid-state imaging device according to (5),
An optical system for forming an optical image on the solid-state imaging device;
An imaging apparatus comprising:

  According to this imaging apparatus, since a solid-state imaging device with little noise and an optical system for forming an optical image on the solid-state imaging device are provided, it is possible to take a high-quality image with little noise.

  According to the present invention, in the charge transfer element (reset transistor) of the charge detection unit formed of a depletion type MOS transistor, the on-resistance is reduced at the time of resetting to reliably discharge the remaining signal charge and the charge at the time of signal charge accumulation. It is possible to provide a charge transfer element, a solid-state image sensor, and an image pickup apparatus that have both a reset characteristic and a low noise characteristic by reliably turning off the transfer element.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a charge transfer device, a solid-state imaging device, and an imaging device according to the invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a schematic plan view of a solid-state imaging device according to the present invention, and FIG. 2 is a schematic cross-sectional view showing the structure of a floating diffusion amplifier in the solid-state imaging device shown in FIG.

  As shown in FIG. 1, the CCD solid-state imaging device 100 includes an imaging device forming region 52 and external connection terminals 54 provided around the imaging device forming region 52.

  In the imaging element formation region 52, a light receiving region 56, a horizontal charge transfer unit 58, an amplifier 60, and a signal output terminal 62 are provided. The light receiving region 56 includes a photoelectric conversion unit (photosensor) 64, a charge readout unit 66, and a vertical charge transfer unit 68.

As schematically shown in FIG. 2 on the downstream side of the horizontal charge transfer portion 58 in the charge transfer direction, the charge transfer element 70 is formed of an N-type semiconductor region (charge transfer) formed in a conductive well layer (P-type well layer) 72. N + type semiconductor regions 78 and 80 are formed on the surface of the (channel layer) 74. An N type semiconductor region 76 is formed in the region of the horizontal charge transfer portion 58. The N + type semiconductor region 78 is a floating diffusion layer (floating diffusion) and serves as a charge injection portion into which signal charges are injected. An amplifier 60 is connected to the floating diffusion layer 78. The amplifier 60 normally uses a source follower that uses a MOS transistor. Note that VFD in the figure represents the potential of the floating diffusion layer 78. The N + type semiconductor region 80 that receives signal charges from the N + type semiconductor region 78 constitutes a reset drain (RD), and the reset drain (RD) 80 is fixed to the reset drain potential VRD.

  Reference numerals 82 to 90 denote electrodes, and drive pulses φ 1 and φ 2 are applied to the electrodes 82, 84 and 86 of the horizontal charge transfer section 38. The electrode 88 is a horizontal transfer output gate (OG), and a predetermined DC voltage VOG is always applied to the electrode 88. Further, the electrode 90 constitutes a reset gate (RG), and a reset gate signal φRG is applied to the reset gate portion 90.

  FIG. 3 is an enlarged view of the depletion type MOS reset transistor (charge transfer element) shown in FIG. As shown in FIG. 3, below the reset gate portion 90, a charge transfer channel layer 74 and a P-type well layer 72 are formed in this order. A channel depth suppression layer 92 that is a P-type semiconductor region for limiting the depletion layer depth of the charge transfer channel layer 74 is formed at a position shallower than the P-type well layer 72. The channel depth suppression layer 92 is formed over the entire length between the floating diffusion layer 78 and the reset drain portion 80. In other words, the channel depth suppression layer 92 is disposed at a position where the center of the length W2 along the signal charge transfer direction substantially coincides with the center of the length W1 of the reset gate portion 90.

  The channel depth suppression layer 92 can be configured to have an impurity concentration higher than that of the P-type well layer 72. The channel depth suppression layer 92 can be disposed at a position shallower than the P-type well layer 72 or has an impurity concentration higher than that of the P-type well layer 72. It arrange | positions with high, or it forms so that at least one may be satisfy | filled.

  The floating diffusion layer 78, the reset drain unit 80, and the reset gate unit 90 formed in the N-type semiconductor region 74 constitute a depletion type MOS reset transistor 70, and a voltage (negative voltage) applied to the reset gate unit 90. The transfer of the signal charge Q discharged from the floating diffusion layer 78 to the reset drain unit 80 is controlled on / off.

Next, the operation of this embodiment will be described.
By sequentially switching the voltage of each signal (φ1, φ2) applied to the solid-state imaging device 100 from the outside according to a predetermined control procedure, the signal charge Q is generated by the horizontal charge transfer unit as shown by an arrow in FIG. The signal charge transferred toward the floating diffusion layer 78 and transferred to the position of the floating diffusion layer 78 is output as a voltage corresponding to the amount of the signal charge Q from the signal output terminal 62 via the amplifier 60.

  That is, in the charge transfer element 70, first, a zero voltage is applied to the reset gate unit 90, the charge transfer element 70 is turned on, the signal charge Q of the floating diffusion layer 78 is discharged to the reset drain unit 80, and the charge is reset. At the same time, the signal charge Q is transferred under the electrode 86 to which φ1 is applied. Then, after a negative voltage is applied to the reset gate unit 90 and the charge transfer element 70 is turned off, the signal charge Q is transferred to the floating diffusion layer 78.

  At this time, as shown in FIG. 3, the depletion type MOS reset transistor (charge transfer element) 70 is ON / OFF controlled according to the timing of the reset gate signal φRG applied to the reset gate unit 90. That is, in an on state where no voltage is applied to the reset gate unit 90, the signal charge Q of the floating diffusion layer 78 is discharged to the reset drain unit 80 via the on resistance of the reset transistor 70 and reset.

  Further, when a negative voltage (reset gate signal φRG) is applied to the reset gate unit 90, the holes 95 in the N-type region (charge transfer channel layer) 74 below the reset gate unit 90 enter the reset gate unit 90 and free electrons. 96 is attracted to the channel depth suppression layer 92 to form a depletion layer 94 in the charge transfer channel layer 74, and the reset transistor 70 is turned off.

  FIG. 4 is a diagram showing the potential potential in the A1-A2 cross section shown in FIG. 2, and the potential potential of each part together with the potential potential (indicated by a two-dot chain line) of a conventional charge transfer device without a channel depth suppression layer. It is shown. As shown in FIG. 4, the potential potential (indicated by a broken line in the figure) of the charge transfer element 70 of the present invention in the on state is the position where the channel depth suppression layer 92 is shallower than the P-type well layer 72 and the P-type. Since the impurity concentration is higher than that of the well layer 72, it is higher than the potential potential of the conventional charge transfer element indicated by the two-dot chain line. Therefore, the potential potential can be easily and reliably raised by the small negative voltage (−Va) applied to the reset gate portion 90, and the reset transistor 70 is reliably turned off. It should be noted that the above effect can be obtained only by either the channel depth suppression layer 92 being located at a position shallower than the P-type well layer 72 or being disposed with a higher impurity concentration than the P-type well layer 72. However, if both conditions are satisfied, further stable operation of the reset transistor 70 becomes possible.

  According to the charge transfer device 70 of the present embodiment, in order to prevent leakage in the charge transfer device 70, the negative voltage applied to the reset gate unit 90 is increased, or the reset drain potential VRD applied to the reset drain unit 80 is set. Therefore, there is no need to lower the signal in synchronization with the reset gate signal φRG. As a result, the on-resistance is reduced at the time of resetting to reliably discharge the remaining signal charge to the reset drain unit 80, and the charge transfer element 70 can be surely applied by applying a small negative voltage to the reset gate unit 90 at the time of signal charge accumulation. The charge transfer element 70 which is in the off state and has both reset characteristics and low noise characteristics can be obtained.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is an enlarged view of a charge transfer element (depletion type MOS reset transistor) according to the second embodiment of the present invention.

  The charge transfer device according to the second embodiment is the same as the charge transfer device according to the first embodiment of the present invention except that the channel depth suppression layer is arranged to be biased toward the floating diffusion layer. Are denoted by the same or corresponding reference numerals, and the description thereof will be simplified or omitted.

  As shown in FIG. 5, the channel depth suppression layer 92 of the charge transfer element 70 of the second embodiment is such that the center of the length W2 along the signal charge transfer direction is the center of the length W1 of the reset gate portion 90. Therefore, it is biased toward the floating diffusion layer 78 by ΔL. As a result, the channel depth suppression layer 92 can be disposed at a position separated from the reset drain portion 80, the withstand voltage performance between the channel depth suppression layer 92 and the reset drain portion 80 is improved, and the parasitic capacitance F1 is reduced. be able to. The parasitic capacitance F2 between the floating diffusion layer 78 and the channel depth suppression layer 92 does not significantly affect the characteristics of the charge transfer element 70 because the potential of the floating diffusion layer 78 is low.

  Therefore, while increasing the withstand voltage performance, the resistance when the charge transfer element 70 is turned on is reduced, and when it is turned off, the charge drain element 70 is surely turned off to suppress charge leakage to the reset drain unit 80, thereby generating parasitics caused by bias conditions and the like. It is possible to obtain a charge transfer element 70 with low noise by suppressing excessive charge / discharge with respect to the capacitance. Since other operations and effects are the same as those of the charge transfer element 70 of the first embodiment, description thereof will be omitted.

  Note that the charge transfer element of the present invention and the solid-state imaging device including the charge transfer element can be easily manufactured by a conventional manufacturing technique such as a photomask or an ion implantation method, and no special capital investment is required. Therefore, the manufacturing cost can be suppressed.

  Next, an imaging apparatus equipped with the solid-state imaging device according to the present invention will be described. FIG. 6 is a block diagram of a digital camera (imaging device) equipped with a CCD solid-state imaging device 100 according to an embodiment of the present invention.

  As shown in FIG. 6, the digital camera 200 of this embodiment includes a photographing lens 102, a solid-state image sensor (CCD solid-state image sensor) 100, a diaphragm 104 provided between the two, an infrared cut filter 106, and the like. And an optical low-pass filter 108. The CPU 110 that controls the entire digital camera 200 controls the flash light emitting unit 112 and the light receiving unit 114, controls the lens driving unit 116 to adjust the position of the photographing lens 102 to the focus position (AF control), and drives the diaphragm. The exposure amount is adjusted by controlling the opening amount of the stop 104 (AE control) via the unit 118. The imaging lens 102, the diaphragm 104, the infrared cut filter 106, and the optical low-pass filter 108 function as an optical system that forms an optical image on the solid-state imaging device 100.

  Further, the CPU 110 drives the solid-state image sensor 100 via the image sensor driving unit 120 and outputs a subject image captured through the photographing lens 102 as a color signal. An instruction signal from the user is input to the CPU 110 through the operation unit 122, and the CPU 110 performs various controls according to the instruction.

  The electric control system of the digital camera 200 includes an analog signal processing unit 124 connected to the output of the solid-state imaging device 100, and an A / D conversion that converts RGB color signals output from the analog signal processing unit 124 into digital signals. The circuit 126 is provided, and these are controlled by the CPU 110.

  Further, the electric control system of the digital camera 200 includes a memory control unit 130 connected to a main memory (frame memory) 128 and a digital signal for performing image processing such as gamma correction calculation, RGB / YC conversion processing, and image composition processing. A processing unit 132; a compression / decompression processing unit 134 that compresses the captured image into a JPEG image or expands the compressed image; and an integration unit 136 that integrates photometric data and obtains a gain for white balance correction performed by the digital signal processing unit 132. And an external memory control unit 140 to which a detachable recording medium 138 is connected, and a display control unit 144 to which a display unit 142 mounted on the back of the camera or the like is connected. These include a control bus 146 and data They are connected to each other by a bus 148 and controlled by a command from the CPU 110.

  Since the imaging apparatus 200 of the present invention includes the solid-state imaging element 100 having the charge transfer element 70 already described in FIGS. 1 to 5, it is possible to capture a high-quality image in which noise generation is suppressed. .

  In addition, this invention is not limited to each embodiment mentioned above, A deformation | transformation, improvement, etc. are possible suitably.

  The present invention relates to a charge transfer element (reset transistor) of a charge detection unit formed of a depletion type MOS transistor, which reduces on-resistance during reset to reliably discharge residual signal charge and charge transfer element during signal charge accumulation. Can be applied to a charge transfer element having both reset characteristics and low noise characteristics, a solid-state image sensor having the charge transfer element, and an image pickup apparatus including the charge transfer element. It is effective for use with a camera or a portable terminal.

1 is a schematic plan view of a solid-state imaging device according to a first embodiment of the present invention. It is typical sectional drawing which shows the structure of the floating diffusion amplifier in the solid-state image sensor shown in FIG. FIG. 3 is an enlarged view of a depletion type MOS reset transistor (charge transfer element) shown in FIG. 2. It is a figure which shows the potential potential in the A1-A2 cross section shown in FIG. It is an enlarged view of a depletion type MOS reset transistor according to a second embodiment of the present invention. It is a block diagram of the imaging device using the solid-state image sensor of this invention. It is a typical cross-sectional enlarged view of a conventional reset transistor. 7 shows a state in which a negative voltage is applied to the reset gate of the reset transistor shown in FIG. 7, (a) shows a state where the applied voltage is small and the off state is insufficient, and (b) shows a state where the large voltage is applied and the off state is turned off. It is a figure. It is a figure which shows the potential potential in the B1-B2 cross section shown in FIG.

Explanation of symbols

56 Light receiving area (light receiving part)
58 Horizontal charge transfer unit 60 Amplifier (output unit)
64 photoelectric conversion unit 68 vertical charge transfer unit 70 charge transfer element (depletion type MOS transistor, reset transistor)
72 P-type well layer (conductive-type well layer)
74 Charge transfer channel layer 78 Floating diffusion layer (charge injection part)
80 reset drain section 90 reset gate section 92 channel depth suppression layer 94 depletion layer 100 solid-state imaging device 200 digital camera (imaging apparatus)
Q signal charge

Claims (7)

  1. A charge injection unit for injecting signal charges and detecting potential changes;
    A reset drain part for receiving signal charges injected into the charge injection part;
    A charge transfer element comprising: a reset gate unit that discharges the signal charge injected into the charge injection unit to the reset drain unit and resets the potential of the charge injection unit,
    Below the reset gate, a charge transfer channel layer and a high-resistance conductivity type well layer are formed in this order,
    A channel depth suppression layer for limiting a depletion layer depth of the charge transfer channel layer is disposed below the reset gate at a position shallower than the conductivity type well layer, or more impurity than the conductivity type well layer. A charge transfer element formed so as to satisfy at least one of arrangement with a high concentration.
  2. The charge transfer device according to claim 1, wherein
    The charge transfer element in which the channel depth suppression layer below the reset gate is formed over the entire length from the charge injection portion to the reset drain.
  3. The charge transfer device according to claim 1, wherein
    The channel depth suppression layer below the reset gate is such that the center of the length along the signal charge transfer direction from the charge injection portion to the reset drain is biased from the center of the reset gate toward the charge injection portion. The charge transfer element is arranged.
  4. The charge transfer device according to any one of claims 1 to 3, wherein
    The charge injection portion and the reset drain portion are N-type semiconductor layers;
    A charge transfer element in which the conductive well layer and the channel depth suppression layer are made of a P-type semiconductor layer.
  5.   A charge transfer element in which a reset transistor including the reset gate, the charge injection unit, and the reset drain is a depletion type MOS transistor.
  6. A light receiving unit having a plurality of photoelectric conversion units, a plurality of vertical charge transfer units that transfer signal charges read from the plurality of photoelectric conversion units in a column direction, and a signal charge that has been transferred through the vertical charge transfer units A solid-state imaging device comprising: a horizontal charge transfer unit that transfers a horizontal charge transfer unit in a row direction orthogonal to the column direction; and an output unit connected downstream of the horizontal charge transfer unit in the charge transfer direction,
    The output unit includes the charge transfer element according to any one of claims 1 to 5, and the charge injection unit is a floating diffusion that detects a signal charge transferred through the horizontal charge transfer unit. element.
  7. A solid-state imaging device according to claim 5;
    An optical system for forming an optical image on the solid-state imaging device;
    An imaging apparatus comprising:
JP2007256704A 2007-09-28 2007-09-28 Charge transfer element, solid-state image sensor and imaging device Withdrawn JP2009088288A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934463A (en) * 2014-03-19 2015-09-23 旺宏电子股份有限公司 Semiconductor device having deep implantation region and method of fabricating same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934463A (en) * 2014-03-19 2015-09-23 旺宏电子股份有限公司 Semiconductor device having deep implantation region and method of fabricating same

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