JPH09275525A - Method for driving mos type imager - Google Patents

Abstract

PROBLEM TO BE SOLVED: To drive the imager in both interlace and noninterlace ways by using the MOS imager of the same configuration. SOLUTION: In the 1st mode, charges fed from pixels 2 by two horizontal lines adjacent to each other along the vertical direction of a matrix are stored in two capacitor groups ca, cb, charges of the capacitors in pairs in the vertical direction of the matrix of the capacitor groups ca, cb are added and the summed charge is outputted sequentially along the horizontal direction of the matrix. In the 2nd mode, charges sent in the unit of lines from the pixel 2 by one horizontal line of the matrix are stored at least in any of the two capacitor groups ca, cb and the charge from each capacitor is outputted sequentially along the horizontal direction of the matrix.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a MOS type imager in which a plurality of pixels are arranged in a matrix.

[0002]

2. Description of the Related Art Conventionally, in a CCD imager, an interlace type in which charges of pixels for two horizontal lines are added and read out for two fields to output an image of one frame, and a charge of all pixels is There is a non-interlaced type that reads sequentially.

The interlaced type is suitable for outputting a moving image because one frame of image is composed of two fields, and the non-interlaced type is for outputting a still image by sequentially reading charges of all pixels. Suitable for

[0004]

However, CCDs
The interlaced type of imager has a register structure that collects charges of pixels that form a pair in the vertical direction of pixels for two horizontal lines and sequentially transfers the collected charges in the vertical direction. It is impossible to perform interlaced type reading.
That is, a problem arises in that an imager having a structure for performing interlaced type reading cannot also be used for non-interlaced type reading.

[0005]

SUMMARY OF THE INVENTION The present invention is a method of driving a MOS type imager, which is made to solve the above problems. That is, according to the present invention, a plurality of pixels are arranged in a matrix, and two capacitor groups each including a plurality of capacitors corresponding to the number of pixels for one line in the horizontal direction of the matrix are provided in the vertical direction of the matrix. This is a method of driving a MOS type imager, and in the first mode, two adjacent horizontal directions along the vertical direction of the matrix are used.
After accumulating the electric charges sent from the pixels for each line on a line-by-line basis in each of the two capacitor groups, the electric charges of the capacitors that form a pair in the vertical direction of the matrix of each capacitor group are added, and the added charges are matrixed. In the second mode, and in the second mode, the charges sent in line units from the pixels for one line in the horizontal direction of the matrix are accumulated in at least one of the two capacitor groups, and then each capacitor in the capacitor group is Is sequentially output along the horizontal direction of the matrix.

In the present invention, the charge transfer structure in the MOS imager is utilized to enable both interlace type read and non-interlace type read.

That is, a plurality of pixels are arranged in a matrix form, and two capacitor groups each including a plurality of capacitors corresponding to the number of pixels in one line in the horizontal direction of the matrix are provided in the vertical direction of the matrix.
In the S-type imager, two capacitors are arranged in the horizontal direction 2
Interlace type reading is achieved by accumulating the charges for each line, adding and outputting the charges, and by accumulating and outputting the charges for one line in the horizontal direction in at least one of the two capacitor groups, the non-interlace type It becomes possible to read.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION A method of driving a MOS imager according to the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram illustrating a driving method of a MOS imager of the present embodiment, FIG. 2 is a timing chart in the case of an interlace type, and FIGS. 3 and 4 are timing charts in the case of a non-interlace type.

First, based on FIG. 1, a MOS to be driven is formed.
The configuration of the mold imager 1 will be described. That is, this MO
The S-type imager 1 has a plurality of pixels 2 arranged in a matrix.
(In this example, four in the horizontal direction and four in the vertical direction) are arranged, and a capacitor group ca composed of a plurality of capacitors ca1 to ca4 corresponding to the number of pixels 2 for one line in the horizontal direction of the matrix, and a plurality of capacitors ca. Capacitors cb1 to cb4
And a capacitor group capacitor cb consisting of

Electric charges are generated in each pixel 2 in accordance with the intensity of light, and the electric charges are accumulated in the capacitor groups ca and cb in line units along the horizontal direction of the matrix. Then, the charges accumulated in the capacitor groups ca and cb are output to the outside via the output amplifier 4.

Further, in the MOS type imager 1, in order to transfer the charges from each pixel 2 to the capacitor groups ca and cb, the signal lines y1 to y4 for sequentially moving the charges line by line in the horizontal direction are driven, And capacitor group c
The vertical scanning circuit 5 that drives the signal lines SH1 and SH2 that accumulates charges in a and cb, and the capacitor groups ca and cb.
Signal line x for sequentially transferring the charge accumulated in the output line to the output line
The horizontal scanning circuit 6 that drives a1 to xa4 and xb1 to xb4 is provided, and the timing generator 7 that controls the drive timing of the vertical scanning circuit 5 and the horizontal scanning circuit 6 is provided.

In order to perform the interlace type drive using this MOS type imager 1, the timing of the signal lines as shown in FIG. 2 is applied. That is, at this timing, the charges of the pixels 2 of the odd line and the even line are separately sampled and held in line units along the horizontal direction of the plurality of pixels 2 arranged in a matrix, and then the charges of both lines are charged. Is added and output.

Specifically, first, the signal line y1 and the signal line S
By setting H1 and High to (1,1),
Capacitors ca1 and ca at positions corresponding to the charges of the four pixels 2 of (2,1), (3,1), and (4,1), respectively.
2, ca3, and ca4, and then the signal line y2 and the signal line SH2 are set to the high level, so that (1,
2), (2,2), (3,2), and (4,2) of the four pixels 2 of the charge corresponding to the respective capacitors cb
It is stored in 1, cb2, cb3, cb4.

In this state, the signal lines xa1 and xb1 are simultaneously set to the high level to add the charges accumulated in the capacitors ca1 and cb1 and output them to the output line, and then to the signal lines xa2 and xb2. Hi at the same time
By setting it to the gh level, the charges accumulated in the capacitors ca2 and cb2 are added and output to the output line, and then the signal lines xa3 and xb3 are simultaneously set to the high level, whereby the capacitors ca3 and cb3.
Are added to each other and output to the output line, and then the signal lines xa4 and xb4 are simultaneously set to the high level to add the charges accumulated in the capacitors ca4 and cb4 and output to the output line. To do.

As a result, an output obtained by adding the electric charge of the pixel 2 of (1,1) and the electric charge of the pixel 2 of (1,2),
The output obtained by adding the charge of the pixel 2 of (2,1) and the charge of the pixel 2 of (2,2), the charge of the pixel 2 of (3,1) and the charge of the pixel 2 of (3,2) The added output and the output of the charge of the pixel 2 of (4, 1) and the charge of the pixel 2 of (4, 2) are sequentially performed.

Next, the signal line y3 and the signal line SH1 are connected to Hi.
By setting to gh level, (1,3), (2,3),
Capacitors ca1, ca2, ca3, at positions corresponding to the electric charges of the four pixels 2 of (3, 3) and (4, 3), respectively.
Then, the signal lines y4 and SH2 are set to a high level, so that (1, 4), (2,
4), (3,4), and (4,4) of the four pixels 2 of the electric charge of the capacitors cb1, cb2, c at positions corresponding respectively
It is stored in b3 and cb4.

In this state, the signal lines xa1 and xb1 are simultaneously set to the high level, the charges accumulated in the capacitors ca1 and cb1 are added and output to the output line, and then the signal lines xa2 and xb2 are output. Hi at the same time
By setting to gh level, the electric charges accumulated in the capacitors ca2 and cb2 are added and output to the output line, and then the signal lines xa3 and xb3 are simultaneously set to High level, so that the capacitors ca3 and cb3
The charges accumulated in the capacitor are added and output to the output line, and then the signal lines xa4 and xb4 are simultaneously set to the high level to add the charges accumulated in the capacitors ca4 and cb3 and output to the output line. To do.

As a result, an output obtained by adding the charges of the pixel 2 of (1, 3) and the charges of the pixel 2 of (1, 4),
The output obtained by adding the electric charge of the pixel 2 of (2,3) and the electric charge of the pixel 2 of (2,4), the electric charge of the pixel 2 of (3,3) and the electric charge of the pixel 2 of (3,4) The summed output and the sum of the charges of the pixel 2 of (4, 3) and the charges of the pixel 2 of (4, 4) are sequentially output.

By repeating such timing, the MOS type imager 1 can be driven by the interlace type.

Next, a case where non-interlaced type driving is performed in the same configuration as the MOS imager 1 shown in FIG. 1 will be described. The present embodiment is characterized in that the interlace type and the non-interlace type can be easily selected only by changing the timing of the signal lines in the vertical scanning circuit 5 and the horizontal scanning circuit 6.

First, the timing shown in FIG. 3 will be described.
At this timing, the charges of the pixels 2 on the same line are continuously sampled and held in separate capacitor groups ca and cb, and then added and output.

Specifically, first, while the signal line y1 is at the high level, the signal lines SH1 and SH2 are sequentially set to H level.
Set to high level. As a result, (1,1), (2,
1), (3, 1), and (4, 1) are the capacitors ca1, ca2, c at the positions where the charges of the four pixels 2 respectively correspond.
a3, ca4 and capacitors cb1, cb2, cb3,
It will be stored in two capacitor groups ca and cb with cb4.

Then, in this state, the signal lines xa1 and xb
By simultaneously setting 1 and High level, the charges accumulated in the capacitors ca1 and cb1, that is, the charges of the pixel 2 of (1, 1) are doubled and sent to the output line, and then the signal line xa2. And xb2 at the same time Hi
By setting to gh level, the charges accumulated in the capacitors ca2 and cb2, that is, the charges of the pixel 2 of (2,1) are doubled and sent to the output line, and then the signal lines xa3 and xb3 are connected. At the same time, the high level causes the charges accumulated in the capacitors ca3 and cb3, that is, the charges of the pixel 2 of (3, 1) to be 2
Doubled and sent to the output line, then the signal lines xa4 and x
By simultaneously setting b4 and High level, the charges accumulated in the capacitors ca4 and cb4, that is, the charges of the pixel 2 of (4, 1) are doubled and sent to the output line.

As a result, the charge of the pixel 2 of (1,1), the charge of the pixel 2 of (2,1), the charge of the pixel 2 of (3,1), and the charge of the pixel 2 of (4,1) are It will be output sequentially.

Similarly, the signal lines SH1 and SH2 are sequentially set to High while the signal line y2 is set to High level.
H level, (1, 2), (2, 2), (3, 2),
The charges of the four pixels 2 of (4, 2) are accumulated in the capacitors ca1, ca2, ca3, ca4 at the corresponding positions and the two capacitor groups ca, cb of the capacitors cb1, cb2, cb3, cb4.

After that, the signal lines xa1 and xb1 are simultaneously set to the high level, so that the charges accumulated in the capacitors ca1 and cb1, that is, the charges of the pixel 2 of (1, 2) are doubled and the output line Sent to
Next, the signal lines xa2 and xb2 are simultaneously set to the high level, so that the charges accumulated in the capacitors ca2 and cb2, that is, the charges of the pixel 2 of (2,2) are doubled and sent to the output line. , Then signal line xa3
And xb3 are simultaneously set to the high level, the charges accumulated in the capacitors ca3 and cb3, that is, the charges of the pixel 2 of (3, 2) are doubled and sent to the output line, and then the signal line. By simultaneously setting xa4 and xb4 to the high level, the charges accumulated in the capacitors ca4 and cb4, that is, (4, 2)
The electric charge of pixel 2 is doubled and sent to the output line.

In FIG. 3, (1, 1), (2,
1), (3,1), (4,1) outputs the charges of the pixel 2, and outputs (1,2), (2,2), (3,2), (4,
The timing up to the output of the electric charge of the pixel 2 in 2) is shown, but the same applies to the case of outputting the electric charge of the pixel 2 constituting the subsequent lines.

With such a timing, non-interlaced type driving can be performed by using the MOS type imager 1 which performs interlaced type driving.

The timing shown in FIG. 4 is also an example in which non-interlace type driving is performed. In this example, S
Always keep the switches for H2 and xb1 to xb4 open.
The electric charge for one line is stored in only one capacitor group (in this example, the capacitor group ca) and output after being set to F.

Specifically, first, the signal line SH1 is set to the high level while the signal line y1 is set to the high level. As a result, (1,1), (2,1), (3,
Capacitors ca1, ca2, ca3, ca4 at positions where the electric charges of the four pixels 2 of 1) and (4, 1) respectively correspond.
Will be accumulated.

Then, in this state, the signal line xa1 is set to Hi.
The charge stored in the capacitor ca1, that is, the charge of the pixel 2 of (1,1) is sent to the output line by setting the gh level, and then stored in the capacitor ca2 by setting the signal line xa2 to the High level. The generated charge, that is, the charge of the pixel 2 of (2,1) is sent to the output line, and then the signal line xa3 is set to the High level,
The charge accumulated in the capacitor ca3, that is, (3
The charge of the pixel 2 of 1) is sent to the output line, and then the signal line xa4 is simultaneously set to the high level, so that the charge accumulated in the capacitor ca4, that is, the charge of the pixel 2 of (4, 1) is output line. Sent to.

As a result, the charge of the pixel 2 of (1,1), the charge of the pixel 2 of (2,1), the charge of the pixel 2 of (3,1), and the charge of the pixel 2 of (4,1) are It will be output sequentially.

Similarly, while the signal line y2 is at the high level, the signal line SH1 is at the high level,
4 of (1,2), (2,2), (3,2), (4,2)
The charges of one pixel 2 are stored in capacitors ca1, ca2, ca3, and ca4 at corresponding positions.

After that, by setting the signal line xa1 to the high level, the charge accumulated in the capacitor ca1, that is, the charge of the pixel 2 of (1, 2) is sent to the output line, and then the signal line xa2 is set to the high level. By
The charge accumulated in the capacitor ca2, that is, (2,
The electric charge of the pixel 2 of 2) is sent to the output line, and then the electric charge accumulated in the capacitor ca3, that is, the electric charge of the pixel 2 of (3, 2) is sent to the output line by setting the signal line xa3 to the High level. Then, the signal line xa4 is simultaneously set to the high level, so that the capacitor ca4
The charge stored in the pixel, that is, the charge of the pixel 2 of (4, 2) is sent to the output line.

Incidentally, also in FIG. As in FIG. 3, the charges of the pixel 2 of (1,1), (2,1), (3,1), (4,1) are output, and (1,2), (2,2),
Although the timing until the charges of the pixel 2 of (3, 2) and (4, 2) are output is shown, the same applies to the case of outputting the charges of the pixel 2 that configures the subsequent lines.

Even at such timing, non-interlaced type driving can be performed using the MOS type imager 1 which performs interlaced type driving.

In this embodiment, the pixel 2 has 4 ×
An example in which the MOS type imager 1 having four matrixes and one output line is driven is taken as an example, but the present invention is also applicable to other matrixes and the case where there are two or more output lines. Further, the present invention is also applicable to a MOS imager having a mechanism for canceling fixed pattern noise of each pixel 2.

[0038]

As described above, the MOS imager driving method of the present invention has the following effects.
That is, in the MOS type imager having the same structure, it is possible to selectively use an interlaced type drive and a non-interlaced type drive, and to manufacture a camera capable of handling both still and moving images using a single imager. Become.

Further, if only the interlaced type MOS imager is manufactured, the non-interlaced type drive can be supported, so that the number of types of MOS type imager to be manufactured can be reduced, which simplifies the manufacturing and reduces the cost. Can be achieved.

[Brief description of drawings]

FIG. 1 is a configuration diagram illustrating an embodiment.

FIG. 2 is a timing chart for explaining interlace type driving.

FIG. 3 is a timing chart (No. 1) for explaining non-interlaced type driving.

FIG. 4 is a timing chart (No. 2) for explaining non-interlaced type driving.

[Explanation of symbols]

1 MOS type imager 2 pixel 4 output amplifier 5 vertical scanning circuit 6 horizontal scanning circuit 7 timing generator ca, cb capacitor group ca1 to ca4, cb1
~ Cb4 capacitor

Claims (3)

[Claims] 1. A plurality of pixels are arranged in a matrix, and two capacitor groups each including a plurality of capacitors corresponding to the number of pixels of one line in the horizontal direction of the matrix are provided in the vertical direction of the matrix. In a first mode, the method is a method of driving a MOS type imager, and in the first mode, charges sent in line units from pixels of two horizontal lines adjacent to each other in the vertical direction of the matrix are respectively stored in the two capacitor groups. After that, the charges of the capacitors forming a pair in the vertical direction of the matrix of each capacitor group are added, and the added charges are sequentially output along the horizontal direction of the matrix. In the second mode, the matrix After accumulating electric charges sent in line units from the pixels for one line in the horizontal direction in at least one of the two capacitor groups The driving method of a MOS imager, characterized in that the charge from each capacitor of said capacitor group sequentially outputs along the horizontal direction of the matrix. 2. In the second mode, charges stored in line units from pixels for one line in the horizontal direction of the matrix are accumulated in both of the two capacitor groups, and then the matrix of each capacitor group is vertically aligned. 2. The method of driving a MOS type imager according to claim 1, wherein charges of respective capacitors forming a pair are added in a direction, and the added charges are sequentially output along the horizontal direction of the matrix. 3. In the second mode, after the charges sent in line units from pixels for one line in the horizontal direction of the matrix are accumulated in only one of the two capacitor groups, the capacitors in which the charges are accumulated are accumulated. 2. The method for driving a MOS imager according to claim 1, wherein the electric charges are sequentially output from each capacitor of the group along the horizontal direction of the matrix.