JPH11146280A - Image signal processor and image signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fast read an image signal that is picked up on a solid-state image pickup device by reading charge as an image signal from a secondary transfer path with a 2nd direction as a horizontal scanning direction and a 1st direction as a vertical scanning direction and outputting the read image signal to a monitor with the horizontal scanning direction and the vertical scanning direction exchanged. SOLUTION: A solid-state image pickup device 1 has the number of vertical pixels which is larger than the number of vertical pixels. The horizontal and vertical directions of an image correspond to the vertical and horizontal directions of the device 1. About charge transfer, a horizontal scanning direction MD scans in the vertical direction of an image to raster scan and next, a vertical scanning direction SD scans in the horizontal direction of the image. The direction MD is a direction in which scan is performed in a short cycle. The directions MD and SD on the device 1 differ from the directions MD and SD on a monitor 14. Then, an image signal which is read from the device 1 is shown with the directions MD and SD reversed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image signal processing technique, and more particularly to a technique for processing an image signal picked up by a solid-state image sensor.

[0002]

2. Description of the Related Art FIG. 18 is a diagram showing a configuration of a conventional image signal processing apparatus.

[0005] The solid-state imaging device 51 has a pixel section 52, a horizontal transfer path 53, and an amplifier 54. The pixel unit 52 has photodiodes arranged two-dimensionally and a plurality of columns of vertical transfer paths extending vertically.

[0004] An image 55 is captured on the pixel section 52.
The photodiode converts a light signal of the captured image 55 into electric charge. The charge is transferred from the photodiode to the vertical transfer path. The vertical transfer path transfers charges in the vertical direction in the figure.

The horizontal transfer path 53 receives charges for one row (arrangement of pixels in the horizontal direction) from a plurality of vertical transfer paths, and transfers the charges in the horizontal direction. The amplifier 54 amplifies the charge transferred by the horizontal transfer path 53 and outputs the amplified charge to the processing unit 61. Subsequently, the horizontal transfer path 53 receives the charges of the next one row from the plurality of vertical transfer paths and transfers the charges in the horizontal direction. Hereinafter, the same processing is performed, and a two-dimensional image signal is output to the processing unit 61.

As a flow of electric charges representing image information, first, electric charges read from the photodiode are transferred to a vertical transfer path which is a primary transfer path for transferring the electric charges in a first direction, and a vertical direction which is a first direction. Transfer in the direction. Next, the transfer to the horizontal transfer path, which is a secondary transfer path for transferring the electric charge in the second direction, is performed.
In the horizontal direction.

[0007] In the above-described charge transfer, image scanning similar to raster scanning is performed. That is, first, scanning is performed in the horizontal direction as the main scanning direction MD. Next, scanning is performed in the vertical direction as the sub-scanning direction SD, and the next row is again scanned in the main scanning direction (horizontal direction) MD. This scanning is repeated to scan the two-dimensional image 55.

The amplifier 54 outputs an analog electric signal to the processing section 61. The processing unit 61 has an A / D converter and the like, converts an electric signal from an analog format to a digital format, and outputs the converted signal to the monitor 64.

An image 65 is displayed on the monitor 64 by raster scanning. That is, first, the image is scanned in the horizontal direction as the main scanning direction MD. Next, the image is scanned in the vertical direction as the sub-scanning direction SD, and the next line is again scanned in the main scanning direction (image horizontal direction) MD. This scanning is repeated to display a two-dimensional image 65 on the monitor 64.

The main scanning direction MD and sub-scanning direction SD on the solid-state image sensor 51 are the same as the main scanning direction MD and sub-scanning direction SD on the monitor 64.

FIGS. 19A and 19B are diagrams for explaining image signal processing of the interlaced system according to the prior art. In the interlace method, one frame is composed of two fields, an A field FA and a B field FB.

FIG. 19A is a diagram showing interlaced scanning on the solid-state image sensor 51. On the solid-state imaging device 51, first, an A-field FA consisting of a group of odd-numbered rows is transferred, and then a B-field FB consisting of a group of even-numbered rows is transferred. One row is an array of pixels scanned in the main scanning direction (image horizontal direction) MD. Depending on the position in the sub-scanning direction (image vertical direction) SD, A
Either the field FA or the B field FB is determined.

FIG. 19B is a diagram showing interlaced scanning on the monitor 54. On the monitor 54, first, the A field FA consisting of a group of odd-numbered rows is scanned, and then the B field FB consisting of a group of even-numbered rows is scanned. Like the solid-state imaging device 51, one row is an array of pixels scanned in the main scanning direction (image horizontal direction) MD, and depends on the position in the sub-scanning direction (image vertical direction) SD. One of the fields FB is determined.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to provide an image signal processing apparatus or an image signal processing method capable of reading out an image signal picked up on a solid-state image sensor at a high speed.

[0015]

According to one aspect of the present invention, there is provided a solid-state imaging device having a plurality of primary transfer paths and one secondary transfer path, and capable of capturing a two-dimensional image. ,
The plurality of primary transfer paths each have a plurality of transfer stages capable of accumulating charges corresponding to the photoelectric conversion units, and can transfer charges in a first direction. A solid-state imaging device having a plurality of transfer stages each capable of accumulating electric charges and capable of receiving electric charges on the plurality of primary transfer paths and transferring the electric charges in a second direction; Reading means for reading out the charge as an image signal from the secondary transfer path with the second direction being the main scanning direction and the first direction being the sub-scanning direction in the two-dimensional image, and reading the read image signal in the main scanning direction and the sub-scanning direction And an output means for outputting the image signal to a monitor after replacing the image signal.

The solid-state imaging device can transfer charges in the primary direction at a higher speed as the number of primary transfer paths (the number of horizontal pixels) is smaller. For example, in a horizontally long two-dimensional image represented by the NTSC format, the number of pixels in the horizontal direction is generally larger than the number of pixels in the vertical direction. In the solid-state imaging device according to the related art, the number of horizontal pixels is larger than the number of vertical pixels according to the NTSC format or the like. According to the present invention, by making the number of horizontal pixels of the solid-state imaging device smaller than the number of vertical pixels, it is possible to read out the charges accumulated on the solid-state imaging device at high speed without lowering the resolution. When outputting to the monitor, the main scanning direction and the sub-scanning direction of the image signal are exchanged, so that the monitor can display a horizontally long image such as the NTSC format in which the number of horizontal pixels is larger than the number of vertical pixels. it can.

According to another aspect of the present invention, (a) a primary transfer path for transferring charges in a first direction and a secondary transfer for receiving charges from the primary transfer path and transferring the charges in a second direction. In a two-dimensional image captured on a solid-state imaging device having a path, the second
And (b) outputting the read image signal to a monitor by exchanging the main scanning direction and the sub-scanning direction with the main scanning direction and the first direction as the sub-scanning direction. An image signal processing method is provided.

[0018]

FIG. 1 is a diagram showing the configuration of an image signal processing apparatus according to an embodiment of the present invention.

The solid-state image pickup device 1 is different from the solid-state image pickup device 51 in FIG.
Placed in a rotated position. Thereby, charges can be read from the solid-state imaging device 1 at a higher speed than in the solid-state imaging device 51 shown in FIG. The reason will be described later.

Since the solid-state image pickup device 1 is placed at a position rotated by 90 °, if an image is displayed on the monitor in this state, the image rotated by 90 ° will be displayed. Therefore, pixel position conversion for reversing the horizontal direction and the vertical direction of the image is required. Hereinafter, the details will be described.

The solid-state imaging device 1 has a pixel section 2, a horizontal transfer path 3, and an amplifier 4. The pixel unit 2 has photodiodes arranged two-dimensionally and a plurality of columns of vertical transfer paths extending vertically. In the solid-state imaging device 1, since the names of the vertical transfer path and the horizontal transfer path are generally used,
In the present specification, in the solid-state imaging device 1, the direction in which the vertical transfer path transfers charges (horizontal direction in the figure) is referred to as the vertical direction, and the direction in which the horizontal transfer path 3 transfers charges (vertical direction in the figure) is horizontal. Called direction.

The solid-state imaging device 1 has a larger number of pixels in the vertical direction than in the horizontal direction. The image 5 is captured on the pixel unit 2. The image horizontal direction (horizontal direction in the figure) corresponds to the vertical direction of the solid-state imaging device 1, and the image vertical direction (vertical direction in the figure) corresponds to the horizontal direction of the solid-state imaging device 1.

The photodiode converts a light signal of the captured image 5 into electric charge. The charge is transferred from the photodiode to the vertical transfer path. The vertical transfer path transfers charges in the vertical direction. The photodiode and the vertical transfer path will be described later in detail with reference to FIG.

The horizontal transfer path 3 is one of a plurality of vertical transfer paths.
Receive the charge for the column (the vertical arrangement of pixels in the figure)
The charges are transferred in the horizontal direction (vertical direction in the figure). The amplifier 4 amplifies the charge transferred on the horizontal transfer path 3 and
Output to the / D converter 11. Subsequently, the horizontal transfer path 3
The next one column of electric charges is received from the plurality of vertical transfer paths, and is transferred in the horizontal direction. Hereinafter, similar processing is performed, and a two-dimensional image signal is output to the A / D converter 11.

In the above-described charge transfer, the main scanning direction MD and the sub-scanning direction SD are different from the raster scan. That is, first, scanning is performed in the image vertical direction (vertical direction in the figure) as the main scanning direction MD. Next, scanning is performed in the image horizontal direction (horizontal direction in the drawing) as the sub-scanning direction SD, and the next row is again scanned in the main scanning direction MD. Repeat this scan,
The dimensional image 5 is scanned.

Here, the main scanning direction MD refers to a scanning direction in a short cycle, and the sub scanning direction SD refers to a scanning direction in a long cycle.

The amplifier 4 outputs an analog electric signal to the A / D converter 11. The A / D converter 11 converts an electric signal from an analog format to a digital format and outputs the signal to the signal processing unit 12. The digital image signal is subjected to processing such as white balance in the signal processing unit 12 and stored in the frame memory 13.

An image signal on the frame memory 13 is scanned by a raster scan on the monitor 14, and an image 15 is displayed on the monitor 14. The monitor 14 has a larger number of pixels in the horizontal direction than in the vertical direction. In the raster scan, first, the image is scanned in the horizontal direction as the main scanning direction MD. Next, the image is scanned in the vertical direction as the sub-scanning direction SD, and the next row (horizontal direction in the figure) is again scanned in the main scanning direction (image horizontal direction) MD. This scanning is repeated, and the two-dimensional image 5 is displayed on the monitor 14.

The main scanning direction MD and sub-scanning direction SD on the solid-state imaging device 1 are different from the main scanning direction MD and sub-scanning direction SD on the monitor 14. Main scanning direction MD on solid-state imaging device 1
Corresponds to the sub-scanning direction SD on the monitor 14, and the sub-scanning direction SD on the solid-state imaging device 1 is the main scanning direction M on the monitor 14.
D.

Therefore, it is necessary to display the image signal read from the solid-state imaging device 1 on the monitor 14 with the main scanning direction MD and the sub-scanning direction SD reversed. Specifically, an image is displayed on the monitor 14 by performing pixel position conversion based on the difference in the scanning direction. This pixel position conversion corresponds to a process of rotating an image by 90 °. The details of this processing will be described later in detail.

FIGS. 2A and 2B are diagrams for explaining the interlaced image signal processing according to the present embodiment. In the interlace method, one frame is composed of two fields, an A field FA and a B field FB.

FIG. 2A is a diagram showing interlaced scanning on the solid-state image pickup device 1. FIG. 2A illustrates the solid-state imaging device 1 of FIG. 1 rotated by 90 °. On the solid-state imaging device 1, first, an A-field FA composed of a group of odd-numbered columns (array of pixels in the vertical direction) is transferred, and then a B-field FB composed of a collection of even-numbered columns is transferred. Do. One column is an arrangement of pixels scanned in the sub-scanning direction (image horizontal direction) SD. By changing the position in the main scanning direction (image vertical direction) MD, either the A field FA or the B field FB is determined.

FIG. 2B is a diagram showing interlaced scanning on the monitor 14. First, on the monitor 14,
A field FA consisting of a group of odd-numbered rows (image horizontal direction) is scanned, and then a B field FB consisting of a group of even-numbered rows is scanned. Unlike the solid-state imaging device 1, one row is in the main scanning direction (image horizontal direction).
A row of pixels to be scanned in the MD, depending on the position in the sub-scanning direction (image vertical direction) SD, A field FA or B field
One of the fields FB is determined.

In FIG. 2A, the pixel section 2 has a plurality of unit pixel sections 20 arranged two-dimensionally. The unit pixel section 20 corresponds to one pixel.

FIG. 3 shows the unit pixel section 20 shown in FIG.
FIG. 3 is a diagram showing the configuration of FIG. The unit pixel section 20 has a photodiode PD and a vertical transfer path VR. The photodiode PD converts the received light into electric charges, and transfers the electric charges to the vertical transfer path VR via the gate. Vertical transfer path VR
Are driven in four phases by four electrodes V1, V2, V3, and V4, and transfer charges in the vertical direction 21. The charges on the vertical transfer path VR are transferred onto the horizontal transfer path 3. Horizontal transfer path 3
Transfer charges in the horizontal direction 22.

FIG. 4 is a timing chart showing pulse signals applied to the electrodes V1 to V4. The overlap time between the pulse signal of one electrode and the pulse signal of another electrode is t
1, the time t1 on the horizontal axis is defined as t1 as a unit time.
Is shown.

FIG. 5 is a potential transition diagram of the vertical transfer path when the time t is set on the vertical axis. The vertical axis is FIG.
, And the horizontal axis indicates the vertical position on the vertical transfer path. For example, eight photodiodes PD1 to PD8
They are arranged in the vertical direction and connected to one vertical transfer path. On the vertical transfer path, four electrodes V1 to V4 are arranged for each photodiode PD. Electric charges are stored in a low potential area. It can be seen that the charge is transferred on the vertical transfer path according to the potential transition.

Next, the reason why the solid-state imaging device 1 (FIG. 1) according to the present embodiment can transfer charges at a higher speed than the solid-state imaging device 51 (FIG. 18) according to the prior art will be described.

FIG. 6A shows electrodes V1 to V4, H1, H
2 shows a configuration of the solid-state imaging device 1 to which the image pickup device 2 is connected. Electrode V1
V4 are electrodes for driving the vertical transfer path as described above, and terminals are provided at both ends of the pixel portion 2 in the horizontal direction. The electrodes H1 and H2 are electrodes for driving the horizontal transfer path 4, and are connected to the horizontal transfer path 4.

FIG. 6B is an electrical equivalent circuit diagram of the electrode wiring section 25 between the left end terminal and the right end terminal of the electrode V1 in FIG. 6A. The resistance R0 is a resistance per pixel, and the capacitance C0 is a capacitance per pixel. Assuming that the number of pixels in the horizontal direction is Nh, Nh resistors R0 are connected in series to the wiring section 25, and Nh capacitors C0 are connected in parallel.

The total capacitance Ct and the total resistance Rt of the wiring section 25 are:
It looks like this: Ct = Nh × C0 (1) Rt = Nh × R0 (2)

The CR time constant τ of the wiring section 25 is as follows. τ = Ct × Rt = Nh ² × C0 × R0 (3)

The time constant τ of the wiring section 25 is equal to the number of horizontal pixels Nh.
Is proportional to the square of The smaller the number of horizontal pixels Nh, the smaller the CR
The time constant is reduced, and the vertical transfer path can be driven at high speed.

FIG. 6C is a diagram showing clock waveforms S 1 and S 2 in the wiring section 25. The clock waveform S1 is a waveform at the end of the wiring section 25 shown in FIG.
The clock waveform S2 is a waveform at the center of the wiring section 25 shown in FIG. If the clock cycle is shortened with respect to the above CR time constant, the waveform S2 at the center becomes dull,
The amount of charge that can be transferred is reduced, and the transfer efficiency is deteriorated.

Next, the solid-state image pickup device 51 according to the prior art
The CR time constant of the solid-state imaging device 1 (FIG. 1) of FIG. The CR time constant is calculated using a solid-state imaging device having a pixel portion of 1530 × 1024 pixels (aspect ratio 3: 2) as an example.

In the solid-state imaging devices 1 and 51, the number of pixels in the horizontal direction and the number of pixels in the vertical direction are opposite. In the solid-state imaging device 51, the number of horizontal pixels is 1530 and the number of vertical pixels is 1024. In the solid-state imaging device 1, the number of horizontal pixels is one.
024 and the number of vertical pixels is 1530.

First, the time constant of the conventional solid-state imaging device 51 is determined. Number of horizontal pixels Nh of solid-state imaging device 51
Is 1530. The CR time constant τ1 is as follows using Expression (3).

Τ1 = Nh ² × C0 × R0 = 1530 ² × C0 × R0

Next, the time constant of the solid-state imaging device 1 according to the present embodiment is determined. The number of horizontal pixels Nh of the solid-state imaging device 1 is 1
024. The CR time constant τ2 is as follows using Expression (3).

Τ ² = Nh ² × C 0 × R 0 = 1024 ² × C 0 × R 0

The ratio τ2 / τ1 of the two time constants is as follows. ^{τ2 / τ1 = 1024 2/1530} 2 ≒ 1 / 2.23

The time constant τ2 of the solid-state image sensor 1 is about 1 / 2.23 compared to the time constant τ1 of the solid-state image sensor 51. The solid-state imaging device 1 has a vertical transfer speed about 2.23 times faster than the solid-state imaging device 51.

The solid-state image pickup devices 1 and 51 can both take an image of the same size (for example, 1530 × 1024). Vertical transfer can be performed.

The solid-state imaging device 1 according to the present embodiment can be configured such that the number of horizontal pixels Nh is smaller than the number of vertical pixels Nv. By setting the smaller number of pixels in the two-dimensional direction (vertical direction and horizontal direction) as the horizontal pixel number Nh, high-speed charge transfer can be performed. Nh / Nv
Is preferably smaller than 1, more preferably smaller than 2/3.

The solid-state imaging device 1 has two read modes. The first mode is an all-pixel reading mode, in which all pixels of 1530 × 1024 pixels are read. First
Is used, for example, when printing a high-definition image on a printer.

The second mode is a thinning-out reading mode, in which an image of 1530 × 1024 pixels is thinned out to 384.
Read an image of × 512 pixels. In the horizontal direction, 1530 pixels are reduced to 384 pixels by thinning out 3 pixels every 4 pixels, and in the vertical direction, 1024 pixels are reduced to 3 pixels every 4 pixels to be 256 pixels per field (512 pixels per frame). The second mode is used, for example, when displaying an image on a small liquid crystal display mounted on a camera to adjust the angle of view, or when reading an image to perform autofocus.

The second mode of the first and second modes will be described as an example. FIG. 7 shows an operation of reading an image signal of the A field from the solid-state imaging device, and FIG. 8 shows an operation of reading an image signal of the B field from the same solid-state imaging device. 7 and 8 each show a part of the solid-state imaging device.

The vertical charge transfer paths VR1 to VR9 transfer charges in the vertical direction. The horizontal charge transfer path 3 has a plurality of transfer stages H1 to H12, and transfers charges in the horizontal direction. The amplifier 4 amplifies the charge transferred from the horizontal transfer path 3 and outputs the amplified charge.

The electric charges on the vertical transfer paths VR1 to VR9 are transferred to the horizontal transfer stages H4 to H4 via the drains D1 to D9, respectively.
Transferred to H12. Horizontal transfer stages H1, H2, H3, H
4 does not have a corresponding vertical transfer path VR.

Hereinafter, the drains D1 to D9, the horizontal transfer stage H
Any one or all of the vertical transfer paths VR1 to VR9 are referred to as a drain D, a horizontal transfer stage H, and a vertical transfer path VR, respectively.

The drain D is provided between the vertical transfer path VR and the horizontal transfer stage H. When the drain D is turned on, the charge transferred from the vertical transfer path VR is discharged to the drain D, and the charge is not transferred to the horizontal transfer stage H. When the drain D is turned off, the charges transferred from the vertical transfer path VR pass over the drain D and reach the horizontal transfer stage H.

First, the reading operation of the A field FA will be described with reference to FIG. The pixel unit 2 has a plurality of photodiodes arranged two-dimensionally. Electric charges corresponding to the received light are accumulated in the photodiode. The accumulated charges are transferred to the vertical transfer paths VR1, VR5, V
The data is transferred from the corresponding photodiode to R9. FIG. 7 shows the state at that time.

The vertical transfer path VR has a plurality of vertical transfer stages arranged in the vertical direction. The pixel section 2 shows charges on the vertical transfer stages arranged two-dimensionally. FIG. 9A shows an arrangement of the charges. Charges 101 and 10 surrounded by solid lines
5 and the like indicate charges to be read, and charge 1 surrounded by a broken line
02, 103, etc. indicate the charges to be thinned out.

By turning off the drains D1, D5 and D9 and turning on the drains D2 to D4 and D6 to D8, only the charges on the vertical transfer paths VR1, VR5 and VR9 can be transferred to the horizontal transfer path 3. it can. That is, one pixel is read out every four pixels in the horizontal direction, and three pixels can be thinned out.

In the vertical direction, one pixel is read out every four pixels and three pixels are thinned out. The charge region 2a indicates charges transferred simultaneously in the first transfer on the horizontal transfer path 3, and the charge region 2b indicates charges transferred simultaneously in the second transfer on the horizontal transfer path 3. These methods will be described later with reference to FIGS.

Next, a read operation of the B field FB will be described with reference to FIG. A field F above
After the reading of A is completed, reading of the B field FB is performed. Electric charges are transferred from the photodiodes to the vertical transfer paths VR3 and VR7. FIG. 8 shows the state at that time.

The pixel section 2 shows the charges on the vertical transfer stages arranged two-dimensionally, and FIG. 9A shows the arrangement of the charges. Charges 301, 305, and the like shown by solid lines indicate charges to be read, and charges 302, 303, and the like shown by broken lines indicate charges to be thinned out.

By turning off the drains D3, D7 and turning on the drains D1, D2, D4 to D6, D8, D9, only the charges on the vertical transfer paths VR3, VR7 can be transferred to the horizontal transfer path 3. it can. That is, one pixel is read out every four pixels in the horizontal direction, and three pixels can be thinned out.

In the vertical direction, one pixel is read out every four pixels and three pixels are thinned out. The charge region 2a indicates charges transferred simultaneously in the first transfer on the horizontal transfer path 3, and the charge region 2b indicates charges transferred simultaneously in the second transfer on the horizontal transfer path 3.

Next, with reference to FIGS.
The reading procedure of the field FA will be described. First, FIG.
As shown in FIG.
Is read out. Thereafter, the charges on the vertical transfer path VR are transferred one stage in the vertical direction (downward in the figure).

As shown in FIG. 10, the electric charge 101 is transferred from the vertical transfer path VR1 to the horizontal transfer stage H4 via the drain D1 which is off. The electric charge 501 is transferred from the vertical transfer path VR5 to the horizontal transfer stage H8 via the drain D5 which is off. Drains D2 to D4, D5 to D8
Are on, the horizontal transfer stages H5 to H7, H9 to H1
No charge flows into 1.

Next, all the drains D1 to D8 are turned on, charges on the vertical transfer path VR are vertically transferred in three stages, and charges for three stages are discharged to the drains D1 to D8. Charges 102 to 104 and 502 to 504 are discharged to drains D1 and D5, respectively.

The charges on the horizontal transfer path 3 are transferred one stage in the horizontal direction. After that, similarly to the above, the drains D1 and D5 are turned off, and the charges on the vertical transfer path VR are transferred one stage in the vertical direction.

As shown in FIG. 11, the charge 101 is stored in the horizontal transfer stage H3, and the charge 105 is stored in the horizontal transfer stage H4. Charges 501 and 505 are stored in horizontal transfer stages H7 and H8, respectively. The charge 901 is transferred to the horizontal transfer stage H1.
1 is stored.

Next, as described above, all the drains D1
To D8, the charge on the vertical transfer path VR is vertically transferred in three stages, and the charges for the three stages are discharged to the drains D1 to D8. Then, after the charges on the horizontal transfer path 3 are transferred one stage in the horizontal direction, the drains D1 and D5 are turned off, and the charges on the vertical transfer path VR are transferred one step in the vertical direction.

As shown in FIG. 12, charges 101, 10
5,109 are stored in horizontal transfer stages H2, H3, H4,
The charges 501, 505, 509 are transferred to the horizontal transfer stages H6, H7,
The charges 901 and 905 stored in H8 are transferred to the horizontal transfer stage H1.
0 and H11.

Next, all the drains D1 to D8 are turned on again, the charges on the vertical transfer path VR are transferred in three stages in the vertical direction, and the charges for three stages are discharged to the drains D1 to D8. Then, after the charges on the horizontal transfer path 3 are transferred one stage in the horizontal direction, the drains D1 and D5 are turned off, and the charges on the vertical transfer path VR are transferred one step in the vertical direction.

As shown in FIG. 13, horizontal transfer stages H1 to H
11, electric charges 101, 105, 109, 113, 50
1,505,509,513,901,905,909
Is accumulated. All the horizontal transfer stages H1 to H11 are filled with the above pixel charges. This state is shown in FIG. 1
One horizontal transfer stage H has two charge storage areas (packets). When charge is accumulated in one of the regions, the remaining one region is always an empty region. As described above, without at least two regions, charges cannot be transferred in the horizontal direction.

Next, the horizontal transfer path 3 is driven, and all charges on the horizontal transfer path 3 are sequentially output from the amplifier 4 and written into the frame memory 13 (FIG. 1). By outputting charges on the horizontal transfer path 3 in a state where all the horizontal transfer stages H are buried, efficient horizontal transfer can be performed.

As shown in the first row of FIG. 9B, the above-described arrangement of the electric charges is written into the frame memory 13 as pixel values. The arrangement of the pixel values is shown in FIG. 7 or FIG.
Corresponds to the electric charge of the region 2a.

Next, the same procedure as above is repeated, and a pixel value corresponding to the electric charge in the area 2b is written in the frame memory 13. As shown in the second row of FIG. 9B, the charges 117, 121, 125,.
The pixel value corresponding to... Is written.

Thereafter, the same procedure is repeated, and all the pixel values corresponding to the charges of the A field FA on the vertical transfer path VR are written in the frame memory 13.

After writing the pixel value of the A field FA to the frame memory 13, the pixel value of the B field FB is written to the frame memory 13 by the same procedure. In the first and second rows of the B field FB in the frame memory 13 (FIG. 9B), the pixel values (FIG. 8 or FIG. 9A) of the areas 2a and 2b are written.

The pixel values in the field memory 13 shown in FIG. 9B are read after being converted in pixel arrangement and supplied to the monitor 14. An image is displayed on the monitor 14 in the pixel array shown in FIG. This pixel array conversion corresponds to performing a procedure reverse to the procedure of reading out from the solid-state imaging device 1 described above. By this conversion, an image having a normal pixel arrangement is restored on the monitor 14 and displayed on the monitor 14.

The pixel section 2 of the solid-state imaging device 1 shown in FIG. 9A is actually rotated by 90 ° clockwise as shown in FIG. And the directions of the images on the monitor 14 match. The image on the solid-state imaging device 1 is reduced and displayed on the monitor 13.

As shown in FIG. 13, by outputting charges on the horizontal transfer path 3 in a state where all the horizontal transfer stages H are buried, efficient horizontal transfer can be performed. As shown in FIG. 10, if all the charges on the horizontal transfer path 3 are output in a state in which the data is transferred one stage in the vertical direction (a state in which the horizontal transfer stages H are not completely buried), only the number of pixels in the vertical direction is obtained. It is necessary to repeat the operation of outputting the charges on the horizontal transfer path 3. According to this embodiment, four pixels in the vertical direction can be simultaneously transferred on the horizontal transfer path 3, so that the reading speed of one field can be increased about four times.

In this embodiment, a case has been described in which four pixels in the vertical direction are transferred horizontally at the same time, but any number of pixels can be transferred as long as the number of pixels is four or less. However, four pixels are the most efficient. When one pixel is read out every n pixels in the horizontal direction, n pixels in the vertical direction can be transferred horizontally at the same time.

Although the case of the interlaced system has been described as an example, an image of one frame can be read out from the solid-state image pickup device by the same method in the case of the non-interlaced system.

Next, according to the above embodiment, the time required for reading out the image signal of one field from the solid-state imaging device 1 is obtained.

The solid-state imaging device 1 has 1024 pixels in the horizontal direction and 1536 pixels in the vertical direction. That is, the image captured on the solid-state imaging device 1 has a horizontal direction of 153.
Six pixels, 1024 pixels in the vertical direction. Monitor 14
Has 384 pixels in the horizontal direction and 512 pixels in the vertical direction.

The thinning rate in the vertical direction at the time of reading from the solid-state imaging device 1 is as follows. 1536 pixels / 384 pixels = 4 That is, one pixel may be read out for every four pixels arranged on the vertical transfer path.

The thinning rate in the horizontal direction when reading from the solid-state imaging device 1 is as follows. 1024 pixels / 512 pixels = 2 This value is a thinning rate in one frame. The thinning rate in one field is 2 × 2 = 4. That is, one pixel may be read out for every four pixels (four vertical transfer paths).

Assuming that the charge transfer frequency is 14 MHz, the transfer pulse period 1fH is as follows. 1fH = 1/14 MHz ≒ 70 ns The transfer pulse overlap time t1 (FIG. 4) is set to 10fH.

The transfer time T1 per vertical transfer path is:
t1 × 8 times. In order to transfer four stages (for four pixels) on the vertical transfer path, 16 cycles are required as shown in FIG. The transfer time T2 is T1 × 16 cycles × 70n
s.

The total pixel transfer time T3 on the horizontal transfer path is 1
It is 024 pixels × 1fH × 70 ns.

One horizontal period (1H) is T2 + T3 = 16
1.3 μs. In the vertical direction, 384 pixels are transferred in 4-pixel units, so that the readout time for one field is 1
61.3 μs × 384/4 = 15 ms.

If the reading time of one field is 15 ms, it is shorter than 1/60 second (about 16.7 ms), so that it can be displayed on the monitor in the NTSC format.

In FIG. 7, the drain D is provided between the vertical transfer path VR and the horizontal transfer path H. However, as shown in FIG. 15, the horizontal transfer step H is located between the drain D and the vertical transfer path VR. As described above, the drain D may be provided. At that time, FIG.
In this case, it is necessary to discharge charges on the vertical transfer path VR to the drain D via empty packets in the horizontal transfer stage H.

FIG. 16 shows an example of a solid-state image pickup device without using a drain. The horizontal transfer path 3 includes horizontal transfer stages H1 to H9.
Having. Vertical transfer paths V1, VR2, VR3, VR4
Are connected to the even-numbered horizontal transfer stages H2, H4, H6, H8. That is, two horizontal transfer stages H are assigned to one vertical transfer path VR.

Next, a non-interlaced reading method will be described as an example. The charges on the vertical transfer path VR are transferred one stage in the vertical direction, and the charges 101, 201, 301, and 401 are transferred to the horizontal transfer stages H2, H4, H6, and H8. next,
The charges on the horizontal transfer path 3 are transferred one stage in the horizontal direction. Next, the charge on the vertical transfer path VR is vertically transferred one stage,
The charges 102, 202, 302, 402 are transferred to the horizontal transfer stage H.
2, H4, H6, and H8.

As shown in FIG. 17, horizontal transfer stages H1 to H
9 has electric charges 101, 102, 201, 202, 30
1,302,401,402,501 are accumulated. In this state, the horizontal transfer path 3 is driven, and all charges on the horizontal transfer path 3 are output from the amplifier 4. Thereafter, by repeating the same procedure as above, an image of one frame can be read.

In the solid-state image pickup device, n horizontal transfer stages H are assigned to one vertical transfer path VR. n is an integer of 2 or more. On the horizontal transfer path 3, n charges can be simultaneously transferred in the horizontal direction, so that the charges can be transferred horizontally efficiently.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0104]

As described above, according to the present invention,
By making the number of primary transfer paths (the number of horizontal pixels) of the solid-state imaging device smaller than the number of vertical pixels, it is possible to read out the charges accumulated on the solid-state imaging device at high speed without lowering the resolution. When outputting to the monitor, the main scanning direction and the sub-scanning direction of the image signal are exchanged, so that the monitor can display a horizontally long image such as the NTSC format in which the number of horizontal pixels is larger than the number of vertical pixels. it can.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an image signal processing device according to an embodiment of the present invention.

2A is a diagram illustrating interlaced scanning on the solid-state imaging device in FIG. 1, and FIG. 2B is a diagram illustrating interlaced scanning on a monitor in FIG.

FIG. 3 is a plan view illustrating a configuration of a unit pixel unit of the solid-state imaging device.

FIG. 4 is a timing chart showing pulse signals applied to electrodes V1 to V4.

FIG. 5 is a potential transition diagram of a vertical transfer path.

6 (A) is a plan view showing a configuration of a solid-state imaging device to which electrodes are connected, FIG. 6 (B) is an electrical equivalent circuit diagram of electrode wiring, and FIG. 6 (C) is FIG. 3 is a waveform diagram of an electrode clock signal.

FIG. 7 is a plan view of the solid-state imaging device when an A-field image signal is read from the solid-state imaging device.

FIG. 8 is a plan view of the solid-state imaging device when reading a B-field image signal from the solid-state imaging device.

FIG. 9A shows a pixel array on a solid-state imaging device, FIG. 9B shows a pixel array on a frame memory,
FIG. 9C is a chart showing the pixel arrangement on the monitor.

FIG. 10 is a plan view of the solid-state imaging device showing a read operation following FIG. 7;

FIG. 11 is a plan view of the solid-state imaging device showing a read operation following FIG. 10;

FIG. 12 is a plan view of the solid-state imaging device showing a read operation following FIG. 11;

FIG. 13 is a plan view of the solid-state imaging device showing a read operation following FIG. 12;

FIG. 14 is a potential diagram showing a charge accumulation state of the horizontal transfer path shown in FIG.

FIG. 15 is a plan view of another solid-state imaging device having a different drain position.

FIG. 16 is a plan view of a solid-state imaging device having no drain.

FIG. 17 is a plan view of the solid-state imaging device showing a read operation following FIG. 16;

FIG. 18 is a diagram illustrating a configuration of an image signal processing device according to a conventional technique.

19A is a diagram illustrating interlaced scanning on the solid-state imaging device in FIG. 18; FIG. 19B is a diagram illustrating interlaced scanning on the monitor in FIG. 18;

[Explanation of symbols]

 Reference Signs List 1,51 solid-state imaging device 2,52 pixel unit 3,53 horizontal transfer path 4,54 amplifier 5,55 image 11 A / D converter 12 signal processing unit 13 frame memory 14,64 monitor 15,65 image 20 unit pixel unit 25 electrode wiring section 61 processing section PD photodiode VR vertical transfer path V1 to V4 vertical electrode H1, H2 horizontal electrode MD main scanning direction SD sub scanning direction FA A field FB B field

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor: Masashi Inaya 3--11-46 Izumi, Asaka-shi, Saitama Prefecture Inside Fujisha Shin Film Co., Ltd.

Claims (6)

[Claims] 1. A solid-state imaging device having a plurality of primary transfer paths and one secondary transfer path and capable of capturing a two-dimensional image, wherein each of the plurality of primary transfer paths is photoelectrically converted. A plurality of transfer stages capable of accumulating electric charges corresponding to the respective sections, and capable of transferring electric charges in the first direction. The one secondary transfer path includes a plurality of transfer stages each capable of accumulating electric charges. A solid-state imaging device having a charge in the plurality of primary transfer paths and capable of transferring the charge in a second direction; a two-dimensional image on the solid-state imaging device having a second direction as a main scanning direction. Reading means for reading out the charge from the secondary transfer path as an image signal with the first direction as a sub-scanning direction; and output means for outputting the read-out image signal to a monitor by exchanging the main scanning direction and the sub-scanning direction. Image signal processing device having the same. 2. The image signal processing device according to claim 1, wherein said primary transfer path has n transfer stages, and said secondary transfer path has m transfer stages smaller than n. 3. The solid-state imaging device is arranged two-dimensionally in the first direction more than in the second direction, converts received light into electric charges, and converts the electric charges into the plurality of primary transfer paths. 3. The image signal processing device according to claim 1, further comprising a photoelectric conversion unit capable of transferring the image signal to the image signal processing unit. 4. The apparatus according to claim 1, further comprising storage means for storing an image signal read by said reading means, wherein said output means reads and outputs the image signal stored in said storage means. The image signal processing device according to any one of the preceding claims. 5. A photoelectric conversion means which is arranged two-dimensionally in a first direction more than a second direction and converts received light into electric charges, and has n transfer stages and is converted by said photoelectric conversion means. A plurality of primary transfer paths capable of transferring the charges to be transferred in the first direction; 2 that can transfer charges
A solid-state imaging device having a next transfer path. 6. A solid-state imaging device having a primary transfer path for transferring charges in a first direction and a secondary transfer path for receiving charges from the primary transfer path and transferring the charges in a second direction. In the two-dimensional image to be captured, the second direction is set to the main scanning direction,
And (b) outputting the read image signal to a monitor by exchanging the main scanning direction and the sub-scanning direction with each other as a sub-scanning direction.