JP3484468B2 - Solid-state imaging device and charge transfer method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer technique, and more particularly to a charge transfer technique for charges accumulated on a solid-state image sensor.

[0002]

2. Description of the Related Art FIG. 18 is a diagram showing the structure of an image signal processing device according to the prior art.

The solid-state image pickup device 51 has a pixel portion 52, a horizontal transfer path 53 and an amplifier 54. The pixel portion 52 has photodiodes arranged two-dimensionally and a plurality of columns of vertical transfer paths extending in the vertical direction.

The image 55 is picked up on the pixel portion 52.
The photodiode converts the optical signal of the captured image 55 into electric charge. The charge is transferred from the photodiode to the vertical transfer path. The vertical transfer path transfers charges in the vertical direction in the figure.

The horizontal transfer path 53 receives electric charges for one row (arrangement of pixels in the horizontal direction) from a plurality of vertical transfer paths and transfers the electric charges in the horizontal direction. The amplifier 54 amplifies the charge transferred by the horizontal transfer path 53 and outputs the amplified charge to the processing unit 61. Subsequently, the horizontal transfer path 53 receives the charges for the next one row from the plurality of vertical transfer paths and transfers the charges in the horizontal direction. Thereafter, similar processing is performed, and a two-dimensional image signal is output to the processing unit 61.

As a flow of charges representing image information, charges read from a photodiode are first transferred to a vertical transfer path which is a primary transfer path for transferring in a first direction, and then a vertical direction which is a first direction. Transfer in the direction. Next, the charge is transferred to a horizontal transfer path that is a secondary transfer path that transfers charges in the second direction, and
Transfer in the horizontal direction, which is the direction of.

The above charge transfer means that image scanning similar to raster scanning is performed. That is, first, horizontal scanning is performed as the main scanning direction MD. Next, the sub-scanning direction SD is scanned in the vertical direction, and the next row is scanned again in the main scanning direction (horizontal direction) MD. This scanning is repeated to scan the two-dimensional image 55.

The amplifier 54 outputs an analog electric signal to the processing section 61. The processing unit 61 has an A / D converter and the like, converts an electric signal from an analog format to a digital format, and outputs it to the monitor 64.

An image 65 is displayed on the monitor 64 by raster scanning. That is, first, the image is scanned in the horizontal direction as the main scanning direction MD. Next, the sub-scanning direction SD is scanned in the image vertical direction, and the next line is scanned again in the main scanning direction (image horizontal direction) MD. This scanning is repeated and the two-dimensional image 65 is displayed on the monitor 64.

The main scanning direction MD and the sub scanning direction SD on the solid-state image pickup device 51 are the same as the main scanning direction MD and the sub scanning direction SD on the monitor 64.

FIGS. 19A and 19B are views for explaining the interlaced image signal processing according to the prior art. In the interlace method, one frame is composed of two fields, A field FA and B field FB.

FIG. 19A is a diagram showing interlaced scanning on the solid-state image pickup device 51. On the solid-state image sensor 51, first, the A field FA including a group of odd-numbered rows is transferred, and then the B field FB including a group of even-numbered rows is transferred. One row is an array of pixels scanned in the main scanning direction (image horizontal direction) MD. Depending on the position in the sub-scanning direction (vertical direction of the image) SD, A
Either the field FA or the B field FB is determined.

FIG. 19B is a diagram showing interlaced scanning on the monitor 54. On the monitor 54, first, the A field FA consisting of a group of odd-numbered rows is scanned, and then the B field FB consisting of a group of even-numbered rows is scanned. Similar to the solid-state image sensor 51, one row is an array of pixels scanned in the main scanning direction (horizontal image direction) MD, and the A field FA or B depending on the position in the sub scanning direction (vertical image direction) SD. Either field FB is determined.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state image pickup device or a charge transfer method capable of efficiently transferring charges accumulated on the solid-state image pickup device.

Another object of the present invention is to provide a solid-state image pickup device or charge transfer method capable of efficiently transferring charges when generating thinned-out image signals.

[0016]

According to one aspect of the present invention, a plurality of photodiodes arranged in a row direction and a column direction and a plurality of photodiodes arranged in proximity to each column of the photodiodes are provided. A plurality of vertical transfer paths capable of receiving charges and transferring the charges in the vertical direction, and a horizontal transfer path capable of receiving charges of one row from the plurality of vertical transfer paths and transferring the charges in the horizontal direction , A plurality of drains capable of selectively discharging charges when the charges are transferred from the vertical transfer paths to the horizontal transfer path, and the charges in the row direction are reduced to 1 / n (n ≧ 2) by the drains. At the same time as thinning out, the charges transferred on the horizontal transfer path are moved in the horizontal direction within the horizontal transfer path by a distance equal to or less than the distance between adjacent charges, and charges for a plurality of rows are accumulated in the horizontal transfer path and read out collectively. Yo The solid-state imaging device is provided with a control circuit that can be controlled.

According to another aspect of the present invention, a plurality of photodiodes arranged in a row direction and a column direction, a plurality of vertical transfer paths arranged adjacent to each column of the photodiodes, and the vertical transfer path. , A plurality of drains capable of selectively discharging charges when transferring charges from the vertical transfer path to the horizontal transfer path, and the drain, while controlling the drain. In a solid-state imaging device having a control circuit for controlling charge transfer from a vertical transfer path to a horizontal transfer path, (a) transferring the charges accumulated in the photodiode onto the vertical transfer path;
(B) transferring the charges on the vertical transfer path in the vertical direction; and (c) using the control circuit, 1 / n (of the charges for one row accumulated on the vertical transfer path). n ≧
The charge on the vertical transfer path of the column 2) is transferred to the horizontal transfer path, and the charge on the vertical transfer path of the other column is discharged to the drain, and (d) the charge transferred to the horizontal transfer path is adjacent to The step of horizontally moving in the horizontal transfer path by a distance equal to or less than the distance of the electric charge to be stored, and (e) transferring the electric charge of the next row accumulated on the vertical transfer path of the 1 / n column to the horizontal transfer path. There is provided a charge transfer method including a step of transferring and (f) a step of horizontally transferring and reading out the charges accumulated on the horizontal transfer path.

[0018]

[0019]

[0020]

1 is a diagram showing the configuration of an image signal processing apparatus according to an embodiment of the present invention.

The solid-state image pickup device 1 is 90 ° in the main scanning direction MD and the sub-scanning direction SD as compared with the solid-state image pickup device 51 of FIG.
It is placed in the rotated position. As a result, the electric charges can be read out from the solid-state image sensor 1 at a higher speed than in the solid-state image sensor 51 shown in FIG. The reason will be described later.

Since the solid-state image pickup device 1 is placed at a position rotated by 90 °, if an image is displayed on the monitor in this state, the image rotated by 90 ° will be displayed. Therefore, pixel position conversion is required to reverse the horizontal and vertical directions of the image. The details will be described below.

The solid-state image pickup device 1 has a pixel portion 2, a horizontal transfer path 3 and an amplifier 4. The pixel unit 2 has photodiodes arranged two-dimensionally and a plurality of columns of vertical transfer paths extending in the vertical direction. In the solid-state image sensor 1, the names of the vertical transfer path and the horizontal transfer path are generally used,
In the present specification, in the solid-state imaging device 1, the direction in which the vertical transfer path transfers charges (horizontal direction in the figure) is called the vertical direction, and the direction in which the horizontal transfer path 3 transfers charges (vertical direction in the figure) is horizontal. Call it direction.

The solid-state image sensor 1 has more pixels in the vertical direction than in the horizontal direction. The image 5 is captured on the pixel unit 2. The image horizontal direction (horizontal direction in the figure) corresponds to the vertical direction of the solid-state image sensor 1, and the image vertical direction (vertical direction in the figure) corresponds to the horizontal direction of the solid-state image sensor 1.

The photodiode converts the optical signal of the captured image 5 into electric charges. The charge is transferred from the photodiode to the vertical transfer path. The vertical transfer path transfers charges in the vertical direction. The photodiode and the vertical transfer path will be described in detail later with reference to FIG.

The horizontal transfer path 3 is composed of a plurality of vertical transfer paths.
Receives electric charges for columns (pixels in the vertical direction in the figure),
The charges are transferred horizontally (vertical direction in the figure). The amplifier 4 amplifies the charges transferred on the horizontal transfer path 3 to
Output to the / D converter 11. Then, the horizontal transfer path 3 is
The charges for the next one column are received from the plurality of vertical transfer paths and transferred in the horizontal direction. Thereafter, similar processing is performed and a two-dimensional image signal is output to the A / D converter 11.

The above charge transfer differs from the raster scan in the main scanning direction MD and the sub scanning direction SD. That is, first, scanning is performed in the image vertical direction (vertical direction in the drawing) as the main scanning direction MD. Next, the image is scanned in the horizontal direction of the image (horizontal direction in the figure) as the sub-scanning direction SD, and again in the main scanning direction MD for the next column. Repeat this scan 2
The three-dimensional image 5 is scanned.

Here, the main scanning direction MD refers to the scanning direction with a short period, and the sub-scanning direction SD refers to the scanning direction with a long period.

The amplifier 4 outputs an analog electric signal to the A / D converter 11. The A / D converter 11 converts the electric signal from an analog format to a digital format and outputs it to the signal processing unit 12. The image signal in digital format is subjected to processing such as white balance in the signal processing unit 12 and stored in the frame memory 13.

An image signal on the frame memory 13 is scanned by raster scanning on the monitor 14, and an image 15 is displayed on the monitor 14. The monitor 14 has more pixels in the horizontal direction than in the vertical direction. The raster scan first scans in the image horizontal direction as the main scanning direction MD. Next, the sub-scanning direction SD is scanned in the image vertical direction, and the next row (horizontal direction in the drawing) is scanned again in the main scanning direction (image horizontal direction) MD. This scanning is repeated and the two-dimensional image 5 is displayed on the monitor 14.

The main scanning direction MD and the sub scanning direction SD on the solid-state image pickup device 1 are different from the main scanning direction MD and the sub scanning direction SD on the monitor 14. Main scanning direction MD on solid-state image sensor 1
Corresponds to the sub scanning direction SD on the monitor 14, and the sub scanning direction SD on the solid-state image sensor 1 is the main scanning direction M on the monitor 14.
Equivalent to D.

Therefore, it is necessary to display the image signal read from the solid-state image pickup device 1 on the monitor 14 with the main scanning direction MD and the sub scanning direction SD reversed. Specifically, the pixel position conversion based on the difference in the scanning direction is performed, and the image is displayed on the monitor 14. This pixel position conversion corresponds to the process of rotating the image by 90 °. Details of this processing will be described later in detail.

FIGS. 2A and 2B are diagrams for explaining the interlaced image signal processing according to this embodiment. In the interlace method, one frame is composed of two fields, A field FA and B field FB.

FIG. 2A is a diagram showing interlaced scanning on the solid-state image sensor 1. In FIG. 2A, the solid-state imaging device 1 of FIG. 1 is shown rotated by 90 °. On the solid-state image sensor 1, first, the A field FA consisting of a group of odd-numbered columns (pixel arrangement in the vertical direction) is transferred, and then the B field FB consisting of a group of even-numbered columns is transferred. To do. One column is an array of pixels scanned in the sub-scanning direction (image horizontal direction) SD. By changing the position in the main scanning direction (vertical direction of the image) MD, either the A field FA or the B field FB is determined.

FIG. 2B is a diagram showing interlaced scanning on the monitor 14. First, on the monitor 14,
A field FA consisting of a group of odd-numbered rows (image horizontal direction) is scanned, and then a field B FB consisting of a group of even-numbered rows is scanned. Unlike the solid-state image sensor 1, one row is in the main scanning direction (horizontal image direction).
It is an array of pixels scanned in the MD, and depending on the position in the sub-scanning direction (image vertical direction) SD, the A field FA or B
Either field FB is determined.

In FIG. 2A, the pixel section 2 has a plurality of unit pixel sections 20 arranged two-dimensionally. The unit pixel portion 20 corresponds to one pixel.

FIG. 3 shows the unit pixel portion 20 shown in FIG.
It is a figure which shows the structure of. The unit pixel section 20 has a photodiode PD and a vertical transfer path VR. The photodiode PD converts the received light into an electric charge and transfers the electric charge to the vertical transfer path VR via the gate. Vertical transfer path VR
Is driven in four phases by four electrodes V1, V2, V3 and V4, and transfers charges in the vertical direction 21. The charges on the vertical transfer path VR are transferred to the horizontal transfer path 3. Horizontal transfer path 3
Transfers charge in the horizontal direction 22.

FIG. 4 is a timing chart showing pulse signals applied to the electrodes V1 to V4. The overlapping time of the pulse signal of one electrode and the pulse signal of another electrode is t
When set to 1, the time t on the horizontal axis is the time t1 as a unit time.
Indicates.

FIG. 5 is a potential transition diagram of the vertical transfer path when the time t is plotted on the vertical axis. The vertical axis is FIG.
Of time, and the horizontal axis represents the vertical position on the vertical transfer path. For example, the eight photodiodes PD1 to PD8 are
They are arranged in the vertical direction and connected to one vertical transfer path. On the vertical transfer path, four electrodes V1 to V4 are arranged for each photodiode PD. Electric charges are accumulated where the potential is low. It can be seen that the charges are transferred on the vertical transfer path according to the potential transition.

Next, the reason why the solid-state image pickup device 1 (FIG. 1) according to the present embodiment can transfer charges faster than the conventional solid-state image pickup device 51 (FIG. 18) will be described.

FIG. 6A shows electrodes V1 to V4, H1 and H.
The structure of the solid-state image sensor 1 to which 2 is connected is shown. Electrode V1
V4 are electrodes for driving the vertical transfer path as described above, and terminals are provided at both ends of the pixel unit 2 in the horizontal direction. The electrodes H1 and H2 are electrodes for driving the horizontal transfer path 4 and are connected to the horizontal transfer path 4.

FIG. 6B shows an electrically equivalent circuit diagram of the electrode wiring portion 25 between the left end terminal and the right end terminal of the electrode V1 of FIG. 6A. The resistor R0 is a resistor per pixel, and the capacitor C0 is a capacitor per pixel. When the number of pixels in the horizontal direction is Nh, Nh resistors R0 are connected in series and Nh capacitors C0 are connected in parallel to the wiring section 25.

The total capacitance Ct and the total resistance Rt of the wiring portion 25 are
It looks like this: Ct = Nh × C0 (1) Rt = Nh × R0 (2)

The CR time constant τ of the wiring section 25 is as follows. τ = Ct × Rt = Nh ² × C0 × R0 (3)

The time constant τ of the wiring portion 25 is determined by the number of horizontal pixels Nh.
Proportional to the square of. The smaller the number of horizontal pixels Nh, the more CR
The time constant becomes small and the vertical transfer path can be driven at high speed.

FIG. 6C is a diagram showing clock waveforms S1 and S2 in the wiring section 25. The clock waveform S1 is a waveform at the end of the wiring portion 25 shown in FIG.
The clock waveform S2 is a waveform at the center of the wiring portion 25 shown in FIG. 6 (B). When the clock cycle is shortened with respect to the CR time constant, the waveform S2 in the central portion is rounded,
This reduces the amount of charge that can be transferred and deteriorates the transfer efficiency.

Next, the solid-state image pickup device 51 according to the prior art.
(FIG. 18) and the solid-state imaging device 1 of this embodiment (FIG. 1) are compared in CR time constant. The CR time constant is calculated by taking a solid-state image sensor having a pixel unit of 1530 × 1024 pixels (aspect ratio 3: 2) as an example.

In the solid-state image pickup devices 1 and 51, the number of pixels in the horizontal direction is opposite to the number of pixels in the vertical direction. In the solid-state imaging device 51, the number of horizontal pixels is 1530 and the number of vertical pixels is 1024. In the solid-state image sensor 1, the number of horizontal pixels is 1.
024, and the number of vertical pixels is 1530.

First, the time constant of the solid-state image pickup device 51 according to the prior art is obtained. Number of horizontal pixels Nh of the solid-state image sensor 51
Is 1530. The CR time constant τ1 is as follows using the equation (3).

Τ1 = Nh ² × C0 × R0 = 1530 ² × C0 × R0

Next, the time constant of the solid-state image pickup device 1 according to this embodiment will be determined. The number of horizontal pixels Nh of the solid-state image sensor 1 is 1
It is 024. The CR time constant τ2 is as follows using the equation (3).

Τ2 = Nh ² × C0 × R0 = 1024 ² × C0 × R0

The ratio τ2 / τ1 of the two time constants is as follows. ^{τ2 / τ1 = 1024 2/1530} 2 ≒ 1 / 2.23

The time constant τ2 of the solid-state image sensor 1 is about 1 / 2.23 as compared with the time constant τ1 of the solid-state image sensor 51. The vertical transfer speed of the solid-state image sensor 1 is about 2.23 times faster than that of the solid-state image sensor 51.

Both the solid-state image pickup devices 1 and 51 can pick up an image of the same size (for example, 1530 × 1024), but the solid-state image pickup device 1 has a smaller number of horizontal pixels than the solid-state image pickup device 51, and therefore can be operated at high speed. Vertical transfer can be performed.

The solid-state image pickup device 1 according to this embodiment can have a configuration in which the number of horizontal pixels Nh is smaller than the number of vertical pixels Nv. By setting the smaller number of pixels in the two-dimensional direction (vertical direction and horizontal direction) to the horizontal pixel number Nh, high-speed charge transfer can be performed. Nh / Nv
Is preferably less than 1 and more preferably less than 2/3.

The solid-state image pickup device 1 has two read modes. The first mode is the all-pixel reading mode, in which all the pixels of 1530 × 1024 pixels are read. First
This mode is used, for example, when printing a high-definition image on a printer.

The second mode is the thinning-out reading mode, in which an image of 1530 × 1024 pixels is thinned out to 384
An image of × 512 pixels is read out. In the horizontal direction, 1530 pixels are thinned out every 4 pixels to 3 pixels to make 384 pixels, and in the vertical direction, 1024 pixels are thinned out at every 4 pixels to 3 pixels to make 256 pixels per field (512 pixels per frame). The second mode is used, for example, when displaying an image on a small liquid crystal display mounted in the camera to adjust the angle of view, or when reading the image to perform autofocus.

Of the first and second modes, the second mode will be described as an example. FIG. 7 is a diagram showing an operation of reading an image signal of the A field from the solid-state image sensor, and FIG. 8 is a diagram showing an operation of reading an image signal of the B field from the same solid-state image sensor. 7 and 8 each show a part of the solid-state image sensor.

The vertical charge transfer paths VR1 to VR9 transfer charges in the vertical direction. The horizontal charge transfer path 3 has a plurality of transfer stages H1 to H12 and transfers charges in the horizontal direction. The amplifier 4 amplifies and outputs the charge transferred from the horizontal transfer path 3.

The charges on the vertical transfer paths VR1 to VR9 are transferred to the horizontal transfer stages H4 to H4 via the drains D1 to D9, respectively.
It is transferred to H12. Horizontal transfer stages H1, H2, H3, H
No corresponding vertical transfer path VR is provided in No. 4.

Hereinafter, the drains D1 to D9 and the horizontal transfer stage H
1 to H12 and any one or all of the vertical transfer paths VR1 to VR9 are referred to as a drain D, a horizontal transfer stage H, and a vertical transfer path VR, respectively.

The drain D is provided between the vertical transfer path VR and the horizontal transfer stage H. When the drain D is turned on, the charges transferred from the vertical transfer path VR are discharged to the drain D, and the charges are not transferred to the horizontal transfer stage H. When the drain D is turned off, the charges transferred from the vertical transfer path VR pass through the drain D and reach the horizontal transfer stage H.

First, the read operation of the A field FA will be described with reference to FIG. The pixel unit 2 has a plurality of photodiodes arranged two-dimensionally. Electric charges corresponding to the received light are accumulated in the photodiode. The accumulated charges are transferred to the vertical transfer paths VR1, VR5, V
The data is transferred to R9 from the corresponding photodiode. FIG. 7 shows the state at that time.

The vertical transfer path VR has a plurality of vertical transfer stages arranged in the vertical direction. The pixel portion 2 shows the charges on the vertical transfer stage arranged two-dimensionally. FIG. 9A shows the arrangement of these charges. Charges 101 and 10 surrounded by solid lines
5 and the like indicate the charges to be read, and the charges 1 surrounded by the broken line
02, 103 and the like indicate the thinned charges.

By turning off the drains D1, D5 and D9 and turning on the drains D2 to D4 and D6 to D8, only the charges on the vertical transfer paths VR1, VR5 and VR9 can be transferred to the horizontal transfer path 3. it can. That is, one pixel can be read out every four pixels in the horizontal direction and three pixels can be thinned out.

Also in the vertical direction, one pixel is read out every four pixels and three pixels are thinned out. The charge region 2a shows the charges simultaneously transferred in the first transfer on the horizontal transfer path 3, and the charge region 2b shows the charges transferred simultaneously in the second transfer on the horizontal transfer path 3. Those methods will be described later with reference to FIGS. 10 to 13.

Next, the read operation of the B field FB will be described with reference to FIG. A field F above
After the reading of A is completed, the B field FB is read. Charges are transferred from the photodiodes to the vertical transfer paths VR3 and VR7. FIG. 8 shows the state at that time.

The pixel section 2 shows charges on the vertical transfer stages arranged two-dimensionally, and FIG. 9A shows the arrangement of these charges. The charges 301, 305 and the like indicated by solid lines indicate the charges to be read, and the charges 302 and 303 and the like indicated by the broken lines indicate the thinned charges.

By turning off the drains D3 and D7 and turning on the drains D1, D2, D4 to D6, D8 and D9, only the charges on the vertical transfer paths VR3 and VR7 can be transferred to the horizontal transfer path 3. it can. That is, one pixel can be read out every four pixels in the horizontal direction and three pixels can be thinned out.

Also in the vertical direction, one pixel is read out every four pixels and three pixels are thinned out. The charge region 2a shows the charges simultaneously transferred in the first transfer on the horizontal transfer path 3, and the charge region 2b shows the charges transferred simultaneously in the second transfer on the horizontal transfer path 3.

Next, referring to FIGS.
The procedure for reading the field FA will be described. First, FIG.
As shown in, the vertical transfer path VR from the photodiode
The charges are read out. After that, the charges on the vertical transfer path VR are transferred one stage in the vertical direction (downward direction in the drawing).

As shown in FIG. 10, the charge 101 is transferred from the vertical transfer path VR1 to the horizontal transfer stage H4 via the drain D1 which is off. The charge 501 is transferred from the vertical transfer path VR5 to the horizontal transfer stage H8 via the drain D5 which is off. Drains D2 to D4, D5 to D8
Is on, the horizontal transfer stages H5 to H7 and H9 to H1
No charge flows into 1.

Next, all the drains D1 to D8 are turned on, the charges on the vertical transfer path VR are vertically transferred in three stages, and the charges of three stages are discharged to the drains D1 to D8. Charges 102-104 and 502-504 are discharged to drains D1 and D5, respectively.

The charges on the horizontal transfer path 3 are horizontally transferred one stage. Thereafter, similarly to the above, the drains D1 and D5 are turned off, and the charges on the vertical transfer path VR are transferred one stage in the vertical direction.

As shown in FIG. 11, the charge 101 is stored in the horizontal transfer stage H3, and the charge 105 is stored in the horizontal transfer stage H4. Charges 501 and 505 are stored in horizontal transfer stages H7 and H8, respectively. The electric charge 901 is the horizontal transfer stage H1.
Accumulated in 1.

Then, similarly to the above, all the drains D1 are
.About.D8 are turned on, the charges on the vertical transfer path VR are vertically transferred in three stages, and the charges for three stages are discharged to the drains D1 to D8. Then, after the charge on the horizontal transfer path 3 is transferred by one stage in the horizontal direction, the drains D1 and D5 are turned off and the charge on the vertical transfer path VR is transferred by one stage in the vertical direction.

As shown in FIG. 12, charges 101, 10
5, 109 are accumulated in the horizontal transfer stages H2, H3, H4,
The charges 501, 505, 509 are transferred to the horizontal transfer stages H6, H7,
The charges 901 and 905 accumulated in H8 are stored in the horizontal transfer stage H1.
It is stored in 0 and H11.

Next, all the drains D1 to D8 are turned on again, the charges on the vertical transfer path VR are vertically transferred in three stages, and the charges for three stages are discharged to the drains D1 to D8. Then, after the charge on the horizontal transfer path 3 is transferred by one stage in the horizontal direction, the drains D1 and D5 are turned off and the charge on the vertical transfer path VR is transferred by one stage in the vertical direction.

As shown in FIG. 13, horizontal transfer stages H1 to H
11 includes charges 101, 105, 109, 113, 50
1,505,509,513,901,905,909
Is accumulated. All the horizontal transfer stages H1 to H11 are filled with the pixel charges described above. This state is shown in FIG. 1
One horizontal transfer stage H has two regions (packets) capable of accumulating charges. When the charge is accumulated in one of the areas, the remaining one area is always an empty area. As described above, the charge cannot be transferred in the horizontal direction unless it has at least two regions.

Next, the horizontal transfer path 3 is driven, and all the charges on the horizontal transfer path 3 are sequentially output from the amplifier 4 and written in the frame memory 13 (FIG. 1). Efficient horizontal transfer can be performed by outputting the charges on the horizontal transfer path 3 with all the horizontal transfer stages H filled.

As shown in the first row of FIG. 9B, the above array of charges is written in the frame memory 13 as pixel values. This pixel value array is shown in FIG. 7 or FIG.
Corresponds to the electric charge of the region 2a shown in.

Next, the same procedure as above is repeated to write the pixel value corresponding to the electric charge of the region 2b into the frame memory 13. As shown in the second row of FIG. 9B, the charges 117, 121, 125, ...
.. The pixel value corresponding to is written.

Thereafter, the same procedure is repeated, and all pixel values corresponding to the charges of the A field FA on the vertical transfer path VR are written in the frame memory 13.

After the pixel value of the A field FA is written in the frame memory 13, the pixel value of the B field FB is written in the frame memory 13 by the same procedure. The pixel values (FIG. 8 or FIG. 9A) of the regions 2a and 2b are written in the first and second rows of the B field FB in the frame memory 13 (FIG. 9B).

The pixel value in the field memory 13 of FIG. 9B is converted into a pixel array, read out, and supplied to the monitor 14. An image is displayed on the monitor 14 in the pixel array shown in FIG. This pixel array conversion is equivalent to performing a procedure reverse to the above-described readout procedure from the solid-state image sensor 1. By this conversion, an image having a normal pixel arrangement is restored on the monitor 14 and displayed on the monitor 14.

Since the pixel portion 2 of the solid-state image sensor 1 shown in FIG. 9A is actually rotated by 90 ° clockwise as shown in FIG. And the orientation of the image on the monitor 14 match. The image on the solid-state image sensor 1 is reduced and displayed on the monitor 13.

As shown in FIG. 13, efficient horizontal transfer can be performed by outputting charges on the horizontal transfer path 3 with all the horizontal transfer stages H filled. If, as shown in FIG. 10, all the charges on the horizontal transfer path 3 are output in a state where one stage is transferred in the vertical direction (a state where all the horizontal transfer stages H are not filled), only the number of pixels in the vertical direction is output. It is necessary to repeat the operation of outputting the charges on the horizontal transfer path 3. According to the present embodiment, four pixels in the vertical direction can be simultaneously transferred on the horizontal transfer path 3, so that the reading speed of one field can be increased by about four times.

In this embodiment, the case where four pixels in the vertical direction are simultaneously transferred in the horizontal direction has been described, but any number of pixels can be transferred as long as they are four pixels or less. However, 4 pixels is the most efficient. When reading one pixel for every n pixels in the horizontal direction, the n pixels in the vertical direction can be horizontally transferred simultaneously.

The case of the interlace system has been described as an example, but in the case of non-interlace, one frame image can be read from the solid-state image pickup device by a similar method.

Next, the time required to read the image signal of one field from the solid-state image pickup device 1 is obtained by the above embodiment.

The solid-state image sensor 1 has 1024 pixels in the horizontal direction and 1536 pixels in the vertical direction. That is, the image picked up on the solid-state image pickup device 1 is 153 in the horizontal direction.
There are 6 pixels and 1024 pixels in the vertical direction. Monitor 14
Has 384 pixels in the horizontal direction and 512 pixels in the vertical direction.

The vertical thinning rate when reading from the solid-state image pickup device 1 is as follows. 1536 pixels / 38
4 pixels = 4, that is, 1 for every 4 pixels lined up on the vertical transfer path
It suffices to read out pixels.

The horizontal thinning rate when reading from the solid-state image sensor 1 is as follows. 1024 pixels / 51
2 pixels = 2 This value is the thinning rate in one frame. The thinning rate in one field is 2 × 2 = 4. That is, one pixel may be read out for every four pixels (four vertical transfer paths).

When the charge transfer frequency is 14 MHz, the transfer pulse period 1fH is as follows.

1fH = 1/14 MHz≈70 ns The transfer pulse overlap time t1 (FIG. 4) = 10 fH.

The transfer time T1 per vertical transfer path is
It is t1 × 8 times. To transfer four stages (four pixels) on the vertical transfer path, 16 cycles are required as shown in FIG. The transfer time T2 is T1 × 16 cycles × 70n
s.

The total pixel transfer time T3 on the horizontal transfer path is 1
It is 024 pixels × 1 fH × 70 ns.

In one horizontal period (1H), T2 + T3 = 16
It is 1.3 μs. Since 384 pixels are transferred in units of 4 pixels in the vertical direction, the read time for one field is 1
61.3 μs × 384/4 = 15 ms.

If the readout time for one field is 15 ms, it is shorter than 1/60 seconds (about 16.7 ms), and therefore, it can be displayed on the monitor in the NTSC format.

Although the drain D is provided between the vertical transfer path VR and the horizontal transfer stage H in FIG. 7, the horizontal transfer stage H is located between the drain D and the vertical transfer path VR as shown in FIG. Thus, the drain D may be provided. At that time, FIG.
In the above, it is necessary to discharge the charges on the vertical transfer path VR to the drain D through the empty packet in the horizontal transfer stage H.

FIG. 16 shows an example of a solid-state image sensor which does not use a drain. The horizontal transfer path 3 includes horizontal transfer stages H1 to H9.
Have. Vertical transfer paths V1, VR2, VR3, VR4
Are connected to even-numbered horizontal transfer stages H2, H4, H6, H8. That is, two horizontal transfer stages H are assigned to one vertical transfer path VR.

Next, a non-interlaced reading method will be described as an example. The charges on the vertical transfer path VR are transferred one stage in the vertical direction, and the charges 101, 201, 301, 401 are transferred to the horizontal transfer stages H2, H4, H6, H8. next,
The charges on the horizontal transfer path 3 are horizontally transferred one stage. Next, the charges on the vertical transfer path VR are transferred one stage in the vertical direction,
The charges 102, 202, 302, 402 are transferred to the horizontal transfer stage H.
2, H4, H6, H8.

As shown in FIG. 17, horizontal transfer stages H1 to H
9 includes charges 101, 102, 201, 202, 30
1, 302, 401, 402, 501 are accumulated. In this state, the horizontal transfer path 3 is driven, and all the charges on the horizontal transfer path 3 are output from the amplifier 4. Then, by repeating the same procedure as above, the image of one frame can be read.

In the solid-state image pickup device, n horizontal transfer stages H are assigned to each vertical transfer path VR. n is an integer of 2 or more. On the horizontal transfer path 3, since n charges can be transferred in the horizontal direction at the same time, the charges can be efficiently transferred horizontally.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0107]

As described above, according to the present invention,
Since charges of two or more packets can be transferred to the horizontal transfer path for each vertical transfer path before the horizontal transfer can be performed, it is possible to efficiently perform the horizontal transfer by reducing the space in the horizontal transfer stage.

Further, by selectively discharging the charges transferred from the vertical transfer path to the drain, it is possible to control whether or not the charge is supplied to the horizontal transfer path.
An image signal in which desired pixels are thinned out can be easily generated.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an image signal processing device according to an embodiment of the present invention.

2A is a diagram showing interlaced scanning on the solid-state image sensor of FIG. 1, and FIG. 2B is a diagram showing interlaced scanning on the monitor of FIG.

FIG. 3 is a plan view showing a configuration of a unit pixel portion of a solid-state image sensor.

FIG. 4 is a timing chart showing pulse signals applied to electrodes V1 to V4.

FIG. 5 is a potential transition diagram of a vertical transfer path.

6A is a plan view showing a configuration of a solid-state imaging device to which electrodes are connected, FIG. 6B is an electrical equivalent circuit diagram of electrode wiring, and FIG. It is a wave form diagram of an electrode clock signal.

FIG. 7 is a plan view of the solid-state imaging device when reading an A-field image signal from the solid-state imaging device.

FIG. 8 is a plan view of the solid-state image sensor when reading the B-field image signal from the solid-state image sensor.

FIG. 9 (A) shows a pixel array on a solid-state image sensor, and FIG. 9 (B) shows a pixel array on a frame memory.
FIG. 9C is a chart showing a pixel array on the monitor.

FIG. 10 is a plan view of the solid-state imaging device showing the read operation subsequent to FIG.

11 is a plan view of the solid-state image sensor showing the read operation subsequent to FIG.

FIG. 12 is a plan view of the solid-state imaging device showing the read operation subsequent to FIG. 11.

FIG. 13 is a plan view of the solid-state imaging device showing the read operation subsequent to FIG.

14 is a potential diagram showing a charge storage state of the horizontal transfer path shown in FIG.

FIG. 15 is a plan view of another solid-state image sensor having different drain positions.

FIG. 16 is a plan view of a solid-state image sensor having no drain.

FIG. 17 is a plan view of the solid-state imaging device showing the read operation subsequent to FIG.

FIG. 18 is a diagram showing a configuration of an image signal processing device according to a conventional technique.

19A is a diagram showing interlaced scanning on the solid-state imaging device of FIG. 18, and FIG. 19B is a diagram showing interlaced scanning on the monitor of FIG.

[Explanation of symbols]

1,51 Solid-state image sensor 2,52 pixels 3,53 horizontal transfer path 4,54 amp 5,55 images 11 A / D converter 12 Signal processing unit 13 frame memory 14,64 monitors 15,65 images 20 unit pixel section 25 electrode wiring section 61 Processing unit PD photodiode VR vertical transfer path V1-V4 vertical electrodes H1, H2 horizontal electrodes MD main scanning direction SD sub-scanning direction FA A field FB B field

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuo Yamada 1-6 Matsumatsudaira, Yamato-cho, Kurokawa-gun, Miyagi Prefecture Fujifilm Microdevice Stock Association In-house (72) Masafumi Inoya 3-1146 Izumi, Asaka-shi, Saitama No. Fuji Photo Film Co., Ltd. (56) Reference JP-A-5-199464 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/335 H01L 27/148

Claims (6)

(57) [Claims] 1. A plurality of photodiodes arranged in a row direction and a column direction, and a plurality of photodiodes arranged in proximity to each column of the photodiodes, capable of receiving charges from the photodiodes and transferring the charges in a vertical direction. A plurality of vertical transfer paths, a horizontal transfer path capable of horizontally transferring charges by receiving charges of one row from the plurality of vertical transfer paths, and a charge transfer from the vertical transfer paths to the horizontal transfer path. A plurality of drains capable of selectively discharging charges at the time of transfer, thinning the charges in the row direction to 1 / n (n ≧ 2) by the drains, and adjoining the charges transferred on the horizontal transfer path to each other. A control circuit that can be controlled to move in the horizontal direction within the horizontal transfer path by a distance equal to or less than the distance of the electric charges to be stored, to accumulate electric charges for a plurality of rows in the horizontal transfer path and to collectively read the electric charges. Solid-state image sensor. 2. The vertical transfer path has first and second vertical transfer paths, and in the first field, charges on the first vertical transfer path are supplied to the horizontal transfer path. The charge on the second vertical transfer path is discharged to the drain, the charge on the first vertical transfer path is discharged to the drain, and the charge on the second vertical transfer path is supplied to the horizontal transfer path in the second field. Interlaced charge transfer means for
The solid-state image sensor according to claim 1. 3. The solid-state imaging device according to claim 1, wherein the drain is provided between the vertical transfer path and the horizontal transfer path. 4. The solid-state imaging device according to claim 1, wherein the drain is provided on the opposite side of the horizontal transfer path from the vertical transfer path. 5. A plurality of photodiodes arranged in a row direction and a column direction, a plurality of vertical transfer paths arranged adjacent to each column of the photodiodes, and receiving charges for one row from the vertical transfer paths. A horizontal transfer path, a plurality of drains capable of selectively discharging charges when transferring charges from the vertical transfer path to the horizontal transfer path, and the vertical transfer path to the horizontal transfer path while controlling the drains. In a solid-state imaging device having a control circuit for controlling the charge transfer, (a) transferring the charges accumulated in the photodiode onto the vertical transfer path; and (b) vertically transferring the charge on the vertical transfer path. And (c) by using the control circuit, the charges on the vertical transfer path in the 1 / n (n ≧ 2) column among the charges for one row accumulated on the vertical transfer path are Horizontal transfer Transferred to the above,
Discharging the charges on the vertical transfer paths of the other columns to the drain; and (d) moving the charges transferred on the horizontal transfer paths in the horizontal direction within the horizontal transfer paths by a distance equal to or less than the distance between adjacent charges. (E) transferring the charges of the next row accumulated on the vertical transfer path of the 1 / n column to the horizontal transfer path, and (f) horizontally transferring the charges accumulated on the horizontal transfer path. Charge transfer method including the step of transferring and reading in the direction. 6. The vertical transfer path has first and second vertical transfer paths, and further, in the first field, charges on the first vertical transfer path are supplied to the horizontal transfer path. The charge on the vertical transfer path is discharged to the drain, the charge on the first vertical transfer path is discharged to the drain, and the charge on the second vertical transfer path is supplied to the horizontal transfer path in the second field. 6. The charge transfer method according to claim 5, further comprising the step of performing interlaced driving by means of an interlace drive.