JP2007166112A - Drive method of solid-state imaging apparatus and solid-state imaging element, and electronic information equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduces a vertical transfer time in the vertical pixel interleaving read mode, with respect to a solid-state imaging element wherein its mode can be switched between a full pixel read mode and a vertical pixel interleaving read mode. <P>SOLUTION: The allocation of quadruple phase drive signals ϕ1 to ϕ4 supplied to vertical transfer gate electrodes is differentiated between the full pixel read mode (first mode) and the vertical pixel interleaving read mode (second mode). In the case of the first mode, the quadruple phase drive signal is allocated to each of four consecutive vertical transfer gates, and in the case of the second mode, the quadruple phase drive signal is allocated to four sets of the vertical transfer gates, each set comprising two consecutive gates so that the vertical transfer time in the second mode can be halved in comparison with the vertical transfer time in the first mode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device including a solid-state imaging device such as an interline transfer system CCD or a frame interline transfer system, a driving method of the solid-state imaging device, and an electronic information device using the solid-state imaging device in an imaging unit. In particular, a solid-state imaging device including a solid-state imaging device and a driving method for the solid-state imaging device capable of reading signal charges from the photoelectric conversion means in different readout modes such as an all-pixel readout mode and a vertical pixel thinning readout mode, The present invention relates to an electronic information device such as a digital video camera and a digital still camera used in an imaging unit, an image input camera, a scanner, a facsimile, a camera-equipped mobile phone device, and the like.

  In this type of conventional solid-state imaging device such as an interline transfer type CCD, photoelectric conversion means (pixel portion) such as a photodiode PD is two-dimensionally formed in order to photoelectrically convert received light (subject light) into signal charges. A vertical transfer unit for sequentially transferring each signal charge read from each photodiode PD in the vertical direction is provided adjacent to each photodiode PD arranged in a matrix and arranged in the vertical direction. It has been. Each signal charge transferred in the vertical direction by the vertical transfer unit is transferred in the horizontal direction by a horizontal transfer unit connected to the end of the vertical transfer unit, and provided at the end of the horizontal transfer unit. A signal is output from the output unit as an imaging signal.

  In such a conventional solid-state imaging device, a high-definition still (still image) image can be obtained on the display screen by reading signal charges from all the photoelectric conversion means (pixel units). When displaying a moving image or the like, it is required to read out at a higher speed. Therefore, as a method for reading signal charges from the photoelectric conversion means, there is a solid-state imaging device capable of switching between the all-pixel reading mode as the first mode and the vertical pixel thinning-out reading mode as the second mode, and a driving method thereof. For example, it is disclosed in Patent Document 1. As this vertical pixel thinning readout mode, for example, there is a method of reading out signal charges by thinning out three pixels in each pixel unit arranged in the vertical direction. For example, in a digital camera, if the number of display pixels of the display unit is, for example, 360,000 pixels, the imaging data for 360,000 pixels may be used if only the display unit is displayed. In this case, the vertical pixel thinning readout mode is used. For example, when the shutter is released to obtain a still image (still image), the higher the number of pixels, the higher the resolution of the image, and the all-pixel readout mode is used.

  FIG. 5 shows a driving method of the solid-state imaging device that can switch between the all-pixel reading mode and the vertical pixel thinning-out reading mode.

  FIG. 5 is a diagram for explaining a conventional solid-state imaging device disclosed in Patent Document 1 and a driving method thereof. FIG. 5A is a diagram illustrating a solid-state imaging device in the all-pixel readout mode as a first mode. FIG. 5B is a schematic diagram showing the solid-state imaging device and the driving method thereof in the vertical pixel thinning readout mode as the second mode.

  5 (a) and 5 (b), the conventional solid-state imaging device is an interline transfer type CCD, and photoelectric conversion means (pixel unit) for converting received light (subject light) into signal charges. A plurality of photodiodes PD are arranged in a two-dimensional matrix, adjacent to the photodiodes PD1 to PD10 arranged in the vertical direction, and the signal charges read from the photodiodes PD are sequentially transferred in the vertical direction. For this purpose, a vertical transfer unit 1 is provided. In the vertical transfer portion 1, vertical transfer gate electrodes are arranged in the vertical direction, and four vertical transfer gate electrodes V1, V2, V3, and V4 are provided for each PD. The signal charge transferred by the vertical transfer unit 1 is transferred in the horizontal direction by the horizontal transfer unit 2 connected to the end of the vertical transfer unit 1, and the output unit 3 provided at the end of the horizontal transfer unit 2. The imaging signal is output from. In FIG. 5, only 10 photodiodes PD are arranged in the vertical direction, but this is for simplifying the description, and usually 10 or more photodiodes are arranged.

  In the all-pixel readout mode as the first mode shown in FIG. 5A, each signal charge generated by all the photodiodes PD arranged in the vertical direction is read out to the vertical transfer unit 1.

  In the vertical transfer unit 1, four vertical transfer drive clock signals of vertical transfer pulses φ1, φ2, φ3, and φ4 are assigned to four consecutive vertical transfer gate electrodes V1, V2, V3, and V4, respectively. Driven. As a result, the signal charges read from the photodiode PD are sequentially transferred in the vertical direction and transferred to the horizontal transfer unit 2. In the horizontal transfer unit 2, the signal charges are transferred in the horizontal direction and transferred to the output unit 3, and the signal charges of all the pixels are sequentially output from the output unit 3. This all-pixel readout mode of the first mode is used when a high-definition still image is obtained on the display screen.

  Next, in the vertical pixel thinning readout mode as the second mode shown in FIG. 5B, among all the photodiodes PD arranged in the vertical direction, the photodiodes PD1, PD6, and PD9 which are one pixel out of four pixels. Each signal charge generated in step (1) is read out to the vertical transfer unit 1. Here, in order to simplify the description, a case where signal charges are read out from one pixel portion by thinning out three pixels among four pixels arranged in the vertical direction is shown. In FIG. 5B, photodiodes PD1 and PD5 are read out. And the signal charge is read from PD9.

  At this time, in the vertical transfer unit 1, the four vertical transfer drive clock signals φ1, φ2, φ3, and φ4 are sequentially assigned to the continuous vertical transfer gate electrodes V1, V2, V3, and V4, respectively, and driven. The As a result, the signal charges read from the photodiode PD are sequentially transferred in the vertical direction and transferred to the horizontal transfer unit 2. In the horizontal transfer unit 2, signal charges are sequentially transferred in the horizontal direction and transferred to the output unit 3, and each signal charge is sequentially output from the output unit 3. This second mode is used when displaying at a high frame rate on the display screen with a smaller number of pixels than the first mode without changing the angle of view. For example, as a moving image, 1/30 second per field image is used. This is used when reading at a high speed of about 1/60 seconds is required.

  As described above, the conventional solid-state imaging device is driven by the same four-electrode four-phase driving method in both the first mode and the second mode.

  Next, the charge transfer state of signal charges by the above four-electrode four-phase driving method will be described.

  FIG. 6 is a diagram for explaining the charge transfer state of signal charges when the four-phase vertical transfer drive clock signals φ1 to φ4 are assigned to the continuous vertical transfer gate electrodes V1 to V4 in the solid-state imaging device of FIG. (A) is a timing chart of the four-phase vertical transfer drive clock signal, and (b) is a potential transition diagram of the vertical transfer unit. In FIG. 6A, the time t is plotted on the horizontal axis and the signal waveform is plotted on the vertical axis, where the overlapping time of a certain transfer pulse and another transfer pulse is a unit time. In FIG. 6B, the vertical axis indicates the time t, and the horizontal axis indicates the vertical position of the vertical transfer unit and its potential.

  For example, the photodiodes PD1 to PD10 are each arranged in the vertical direction and connected to one vertical transfer unit 1 as shown in FIG. The vertical transfer unit 1 is provided with four vertical transfer gate electrodes V1 to V4 for each photodiode PD, and four vertical transfer gates V1 to V4 are sequentially arranged in the direction of the horizontal transfer unit 2 side. An electrode is provided.

  Vertical transfer drive clock signals φ1 to φ4 are supplied to the four vertical transfer gate electrodes V1 to V4. In FIG. 6B, signal charges are accumulated at a low potential, and the state in which the signal charges 4 are sequentially transferred in the vertical transfer unit 1 according to the potential transition is indicated by hatching.

  At time t = 0, the signal charge 4 is located in the vertical transfer unit 1 adjacent to the photodiode PD5. As time passes, the signal charge 4 is transferred in the vertical direction (left direction in FIG. 6).

  At time t = 32, the signal charge 4 is located in the vertical transfer unit 1 adjacent to the photodiode PD1. Therefore, it can be seen that the time required for charge transfer of the signal charge 4 from the position adjacent to the photodiode PD5 to the position adjacent to the photodiode PD1 is 32 cycles.

  As described above, in the second mode in which signal charges are read out from one pixel by thinning out three pixels out of four pixels arranged in the vertical direction, 32 cycles are required to transfer vertical charges for four pixels, It takes a long time. Further, in a solid-state imaging device with higher pixels, the number of pixels arranged in the vertical direction increases, and thus the number of transfer stages increases, so that the charge transfer takes a long time. Therefore, in order to read out one field image earlier, it is necessary to reduce the transfer time. In particular, in the vertical pixel thinning readout mode in which a higher frame rate is required than in the all-pixel readout mode, the faster the vertical charge transfer time is required for a solid-state imaging device with higher pixels.

  A conventional technique for reducing the cycle time required for the vertical charge transfer is disclosed in Patent Document 2, for example.

  7A and 7B are diagrams for explaining a conventional solid-state imaging device disclosed in Patent Document 2, in which FIG. 7A is a schematic diagram illustrating the first mode, and FIG. 7B is a schematic diagram illustrating the second mode. It is.

  7A and 7B, the conventional solid-state imaging device uses a vertical transfer drive clock signal to be supplied to each vertical transfer gate electrode of the vertical transfer unit 1 of the CCD chip 11 in order to generate a vertical transfer drive clock signal. A charge transfer control unit 12 is provided. The vertical transfer control unit 12 includes a 4-phase drive control unit 12a that outputs 4-phase vertical transfer drive clock signals φ1 to φ4, and a 16-phase drive control unit 12b that outputs 16-phase vertical transfer drive clock signals φ1 to φ16. These are switched according to the mode signal.

  In the first mode shown in FIG. 7A, the first mode signal M1 is supplied to the CCD chip 11 and the vertical transfer control unit 12. The four-phase drive control unit 12a is connected to the vertical transfer unit 1, and the four-phase vertical transfer drive clock signals φ1 to φ4 are supplied to the four consecutive vertical transfer gate electrodes V1 to V4, respectively.

  In the second mode shown in FIG. 7B, the second mode signal M2 is supplied to the CCD chip 11 and the vertical drive control unit 12. A 16-phase drive control unit 12b is connected to the vertical transfer unit 1, and 16-phase vertical transfer drive clock signals φ1 to φ16 are supplied to each of the 16 consecutive vertical transfer gate electrodes V1 to V16.

As described above, the charge transfer time is increased by supplying the 16-phase vertical transfer drive clock signals φ1 to φ16 to the vertical transfer gate electrodes V1 to V16 in the second mode, and the conventional technique shown in FIG. The vertical transfer cycle time required for 32 cycles can be halved to 16 cycles, and high-speed charge transfer can be performed.
JP-A-9-298755 JP-A-11-164206

  However, the conventional technique has the following problems.

  When the number of pixels of the solid-state imaging device is increased, the solid-state imaging device tends to have a higher number of pixels because the still image becomes higher definition and the image is not roughened when the image is enlarged and enlarged. When the number of pixels of the solid-state imaging device is increased, the number of vertical transfer stages is also increased, and the vertical transfer time is delayed because it is necessary to transfer the signal charge from a further distance to the horizontal transfer unit. Therefore, when only the charge transfer time similar to the conventional one can be secured (for example, when displaying on the display unit of the apparatus), the charge transfer time of the vertical transfer unit to the horizontal transfer unit must be shortened.

  In the prior art disclosed in Patent Document 1, when the signal charge is read from one pixel by thinning out three pixels out of four pixels arranged in the vertical direction, 32 cycles are required in the second mode. There is a problem that it takes a long time from the request for shortening the charge transfer time. Therefore, in order to read out one field image faster, it is necessary to reduce the vertical transfer time.

  In order to solve this problem, the conventional technique disclosed in Patent Document 2 includes a 16-phase drive control unit used in the second mode in addition to the 4-phase drive control unit used in the first mode. Yes. For this reason, there is a problem that the solid-state imaging device (imaging module) is increased correspondingly, resulting in an increase in manufacturing cost and total power consumption. Furthermore, the solid-state imaging device (CCD) also has a problem that the chip size increases because the drive control unit needs to be connected to the 16 electrodes, so that the internal wiring increases and the number of electrode pads increases. .

  The present invention solves the above-described conventional problems, and a solid-state imaging device capable of shortening the vertical charge transfer time in the vertical pixel thinning readout mode without increasing the chip size, manufacturing cost and power consumption, and It is an object of the present invention to provide a method for driving a solid-state imaging device and an electronic information device using the method for an imaging unit.

  A solid-state imaging device according to the present invention includes a plurality of photoelectric conversion units that convert received light into signal charges, and a charge transfer unit that transfers each signal charge read from the plurality of photoelectric conversion units in a predetermined direction. Each of the charge transfer means constituting the charge transfer means according to the first mode and the second mode in which the signal charges are read from the solid-state imaging device and the photoelectric conversion means arranged in parallel with the predetermined direction. And a multi-phase drive control means for outputting a multi-phase drive signal for driving each charge transfer gate electrode by changing the output assignment of the multi-phase drive signal to the charge transfer gate electrode. Achieved.

  Preferably, the output allocation in the solid-state imaging device of the present invention is performed for each of the charge transfer gate electrodes for each of n (n; a natural number of 2 or more) consecutive charge transfer gate electrodes in the first mode. Each of the n-phase drive signals is allocated, and in the second mode, m × n (m is a natural number of 2 or more, n is a natural number of 3 or more) consecutive m pieces for each successive charge transfer gate electrode Each of the n-phase drive signals is assigned to each set, where n is a set.

  A solid-state imaging device according to the present invention includes a plurality of photoelectric conversion units that convert received light into signal charges, and a charge transfer unit that transfers each signal charge read from the plurality of photoelectric conversion units in a predetermined direction. A solid-state image pickup device, a multi-phase drive control means for outputting a multi-phase drive signal for driving each charge transfer gate electrode constituting the charge transfer means, and signals from the photoelectric conversion means arranged in parallel in the predetermined direction. Changeover means for switching the allocation of the multi-phase drive signals to the respective charge transfer gate electrodes in accordance with the first mode and the second mode, which are different from each other in how the charge is read. The above objective is achieved.

  Preferably, the change-over switch means in the solid-state imaging device according to the present invention provides each of the charge transfer gate electrodes for each of n (n; a natural number of 2 or more) consecutive charge transfer gate electrodes in the first mode. Each of n-phase drive signals is assigned to each of them, and in the second mode, m × n (m is a natural number of 2 or more, n is a natural number of 3 or more) consecutive m of consecutive charge transfer gate electrodes. Switching is made so that each of the n-phase drive signals is assigned to each set, with n sets each.

  Further, preferably, in the solid-state imaging device of the present invention, the multi-phase drive signal is assigned to each of the charge transfer gate electrodes so that the charge transfer speed is either a normal speed or a high speed.

  Further preferably, n in the solid-state imaging device of the present invention is 3 or 4.

  Further preferably, m in the solid-state imaging device of the present invention is 2 or 3.

  Further preferably, in the solid-state imaging device of the present invention, the first mode is the all-pixel readout mode and the charge transfer speed is the normal speed mode, and the second mode is the vertical pixel thinning readout mode and the charge transfer speed is the high-speed mode. It is.

  More preferably, in the second mode in the solid-state imaging device of the present invention, the previous signal charge is read out by thinning out three pixels for every four pixels of the photoelectric conversion means arranged in the vertical direction.

  Further preferably, the charge transfer means in the solid-state imaging device of the present invention is at least one of a vertical charge transfer means and a horizontal charge transfer means, and the predetermined direction is vertical when the charge transfer means is the vertical charge transfer means. A charge transfer direction, and when the charge transfer means is the horizontal charge transfer means, the predetermined direction is a horizontal charge transfer direction, and when the charge transfer means is the vertical charge transfer means and the horizontal charge transfer means, The predetermined directions are the vertical charge transfer direction and the horizontal charge transfer direction.

  Further preferably, the solid-state imaging device in the solid-state imaging device of the present invention is an interline transfer type CCD or a frame interline transfer type CCD.

  In the solid-state imaging device driving method of the present invention, the received light is converted into signal charges by the photoelectric conversion means, and the signal charges read from the photoelectric conversion means are predetermined by the charge transfer means using a plurality of phase drive signals. A method of driving a solid-state imaging device that transfers charges in a direction, depending on whether in a first mode or in a second mode, how to read out each signal charge from photoelectric conversion means arranged in parallel in the predetermined direction, The assignment of the multi-phase drive signal to each charge transfer gate electrode constituting the charge transfer means is switched, whereby the above object is achieved.

  Preferably, in the first mode of the driving method of the solid-state imaging device of the present invention, n for each of the charge transfer gate electrodes for every n (n; a natural number of 2 or more) consecutive charge transfer gate electrodes. In the second mode, m × n sheets (m is a natural number of 2 or more and n is a natural number of 3 or more) are consecutive m for each consecutive charge transfer gate electrode. Each of n-phase drive signals is assigned to each set as n sets.

  Further preferably, n is 3 or 4 in the driving method of the solid-state imaging device of the present invention.

  Further preferably, m is 2 or 3 in the driving method of the solid-state imaging device of the present invention.

  Further preferably, in the solid-state imaging device driving method of the present invention, the first mode is an all-pixel readout mode and the charge transfer speed is a normal speed mode, and the second mode is a vertical pixel thinning readout mode and the charge transfer speed is High speed mode.

  Further preferably, in the second mode of the driving method of the solid-state imaging device of the present invention, the signal charges are read by thinning out three pixels for every four pixels of the photoelectric conversion means arranged in the vertical direction.

  Further preferably, in the solid-state imaging device driving method of the present invention, the charge transfer means is at least one of a vertical charge transfer means and a horizontal charge transfer means, and the predetermined transfer when the charge transfer means is the vertical charge transfer means. The direction is a vertical charge transfer direction, and when the charge transfer means is the horizontal charge transfer means, the predetermined direction is a horizontal charge transfer direction, and the charge transfer means is connected to the vertical charge transfer means and the horizontal charge transfer means. In this case, the predetermined directions are the vertical charge transfer direction and the horizontal charge transfer direction.

  Further preferably, the solid-state image sensor in the driving method of the solid-state image sensor of the present invention is an interline transfer type CCD or a frame interline transfer type CCD.

  An electronic information device according to the present invention uses the solid-state imaging device according to the present invention as an imaging unit, thereby achieving the object.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, the vertical transfer gate electrode as the charge transfer gate electrode in the all-pixel read mode as the first mode and the vertical pixel thinning-out read mode as the second mode is a multi-phase drive signal, For example, it is driven by the same four-phase drive signal as in the prior art.

  For example, the assignment of a four-phase drive signal to each vertical transfer gate electrode is switched according to the first mode and the second mode. In the first mode, for example, each of four-phase drive signals is assigned to each of the four consecutive vertical transfer gate electrodes. Further, in the second mode, for example, each of the four-phase drive signals is assigned to each set, with two sets each including eight consecutive vertical transfer gate electrodes as four sets.

  In the second read mode, vertical transfer is performed by a four-phase drive signal with a set of two continuous vertical transfer gate electrodes as a set, and therefore vertical transfer is performed by a four-phase drive signal for each vertical transfer gate electrode. Compared with the prior art of Patent Document 1, the number of charge transfer stages is halved, and the charge transfer time can be halved.

  In addition, since the same four-phase vertical transfer drive control unit is used in the all-pixel read mode and the vertical pixel thinning-out read mode, multiple layers are separately provided for vertical charge transfer control as in the prior art of Patent Document 2. No drive controller is required.

  As described above, according to the present invention, in the vertical pixel thinning readout mode in which high-speed readout is required, vertical transfer is performed by a four-phase drive signal with two continuous vertical transfer gate electrodes as a set. Compared with the first prior art, the vertical charge transfer time can be shortened.

  In addition, since the same 4-phase vertical transfer drive controller as in the prior art is used in the all-pixel readout mode and the vertical pixel thinning readout mode, the 4-phase drive controller and the 16-phase drive as in the prior art of Patent Document 2 are used. The two drive control units of the control unit are no longer necessary, and the number of internal wirings and electrode pads for connecting the vertical transfer control unit and the vertical transfer gate electrode can be reduced. Manufacturing cost can be reduced, chip size can be reduced, and power consumption can be reduced.

  Embodiments of a solid-state imaging device and a solid-state imaging element driving method according to the present invention will be described below with reference to the drawings. In the following embodiment, for comparison with the prior art, as a method of reading the signal charge from the photodiode PD as the photoelectric conversion means, the all-pixel reading mode in the first mode and the four pixels arranged in the vertical direction are: An example will be described in which the vertical pixel thinning readout mode of the second mode in which signals are read from one pixel by thinning out three pixels can be switched. However, the present invention is not limited to this.

  FIG. 1 is a diagram for explaining a solid-state imaging device and a driving method thereof according to an embodiment of the present invention. FIG. 1A is a diagram illustrating a solid-state imaging device and a driving method thereof in an all-pixel readout mode as a first mode. FIG. 4B is a schematic diagram illustrating a solid-state imaging device and a driving method thereof in the vertical pixel thinning readout mode as the second mode.

  1A and 1B, the solid-state imaging device 10 of this embodiment is an interline transfer type CCD, and photoelectric conversion means for converting received light (subject light) into signal charges. A plurality of photodiodes PD are arranged in a two-dimensional matrix and adjacent to the photodiodes PD1 to PD10 arranged in the vertical direction to transfer the signal charges read from the photodiode PD in the vertical direction. A vertical transfer unit 1 constituting the charge transfer means is provided. A read gate electrode (not shown) is provided between the photodiode PD and the vertical transfer unit 1, and the drive voltage supplied to the read gate electrode is controlled to control each photodiode PD (pixel unit). The reading of the signal charge is controlled.

  In the vertical transfer unit 1, vertical transfer gate electrodes as charge transfer gate electrodes are arranged in the vertical direction, and four vertical transfer gate electrodes V1 to V4 or V5 to V8 are provided for each photodiode PD. . The vertical transfer gate electrodes V1 to V8 are arranged in the order of V1 to V8 in the direction toward the horizontal transfer unit 2 constituting the charge transfer means, and are vertically perpendicular to the eight gates extending across the two photodiodes PD. Transfer gate electrodes V1 to V8 are assigned. By controlling the drive control voltage (multiple phase drive signal; here four phases) supplied to the vertical transfer gate electrodes V1 to V8, the charge transfer in each vertical transfer unit 1 is controlled. Yes.

  The signal charge transferred by the vertical transfer unit 1 is transferred in the horizontal direction by the horizontal transfer unit 2 connected to the end of the vertical transfer unit 1, and the output unit 3 provided at the end of the horizontal transfer unit 2. Is output as an imaging signal. In FIG. 1, in order to simplify the description and compare with the prior art, an example in which ten photodiodes PD are arranged in the vertical direction has been described. However, more photodiodes PD may be arranged.

  With the above configuration, first, the all-pixel readout mode as the first mode will be described.

  In the all-pixel readout mode as the first mode shown in FIG. 1A, signal charges generated by all the photodiodes PD arranged in the vertical direction are read out to the vertical transfer unit 1 by the four-phase driving.

  In the vertical transfer unit 1, vertical transfer is performed on four consecutive vertical transfer gate electrodes V1, V2, V3, and V4 and on four consecutive vertical transfer gate electrodes V5, V6, V7, and V8, respectively. Drive control is performed by assigning four-phase vertical transfer drive clock signals of pulses φ1, φ2, φ3, and φ4. As a result, the signal charges read from all the photodiodes PD are transferred in the vertical direction and transferred to the horizontal transfer unit 2. In the horizontal transfer unit 2, signal charges are transferred in the horizontal direction and transferred to the output unit 3, and signal charges of all the pixels are sequentially output from the output unit 3 as imaging signals. This all-pixel readout mode of the first mode is used when obtaining a high-definition still image.

  In this all-pixel readout mode, although there are eight vertical transfer gate electrodes V1 to V8, the allocation state of the vertical transfer pulses φ1 to φ4 is the same as the prior art in which four vertical transfer gate electrodes are provided. The charge transfer method is substantially the same as the prior art.

  Next, the vertical pixel thinning readout mode as the second mode will be described.

  In the vertical pixel thinning readout mode as the second mode shown in FIG. 1B, signal charges generated by the photodiodes PD1, PD5, and PD9 among all the photodiodes PD arranged in the vertical direction are read out to the vertical transfer unit 1. It is. Here, in order to simplify the description, a case where signal charges are read from one pixel by thinning out three pixels among four pixels arranged in the vertical direction is shown. In FIG. 1B, photodiodes PD1, PD5, and The signal charge is read from PD9.

  At this time, in the vertical transfer unit 1, two sets of eight continuous vertical transfer gate electrodes are divided into four sets, and the vertical transfer gate electrodes V1 and V2, V3 and V4, V5 and V6, V7 Four-phase vertical transfer drive clock signals of φ1, φ2, φ3, and φ4 are assigned to V8 and controlled for driving. As a result, the signal charge read from each photodiode PD is transferred in the vertical direction and transferred to the horizontal transfer unit 2. In the horizontal transfer unit 2, signal charges are transferred in the horizontal direction and transferred to the output unit 3, and each signal charge is sequentially output as an imaging signal from the output unit 3. This second mode is used when displaying at a high frame rate with a smaller number of pixels than the first mode without changing the angle of view, and for example, as a moving image, 1/30 seconds to 1/60 seconds per field image. It is used when it is required to read at a high speed.

  As described above, in the solid-state imaging device 10 of the present embodiment, the four-phase transfer drive clock signals φ1 to φ4 are assigned to the eight vertical transfer gate electrodes V1 to V8 according to the first mode and the second mode. It has been switched.

  FIG. 2 is a block diagram showing a configuration example of a main part of a solid-state imaging device including the solid-state imaging device of FIG. 1 and a vertical transfer control unit that drives and controls the solid-state imaging device. FIG. Block diagram (b) is a block diagram showing the second mode.

  2A and 2B, the solid-state imaging device 20 according to the present embodiment includes each vertical transfer drive clock supplied to each vertical transfer gate electrode V1 to V8 of the vertical transfer unit 1 of the CCD chip 11. In order to generate a signal (multi-phase drive signal; n-phase drive signal, here n = 4), a vertical transfer control unit 12A is provided as multi-phase drive control means. This vertical transfer control unit 12A has a four-phase vertical transfer drive according to the four-phase drive control unit 12a that outputs the four-phase vertical transfer drive clock signals φ1 to φ4 and the first mode and the second mode. And a changeover switch means 13 for switching the allocation of the clock signal to the vertical transfer gate electrodes V1 to V8.

  FIG. 3 is a circuit diagram for explaining a configuration example of a vertical charge transfer control unit including the changeover switch means of FIG. 2, wherein (a) is a circuit diagram showing an operation state in the first mode, and (b). These are the circuit diagrams which show the operation state at the time of 2nd mode.

  In the first mode shown in FIGS. 2A and 3A, the first mode signal M1 is supplied to the CCD chip 11 and the vertical transfer control unit 12A. At this time, the changeover switch 13 causes the four vertical transfer gate electrodes V1, V2, V3 and V4 of the vertical transfer unit 1 and the four vertical transfer gate electrodes V5, V6, V7 and V8 to be continuous. Thus, four-phase vertical transfer drive clock signals φ1, φ2, φ3, and φ4 are assigned, respectively.

  In the second mode shown in FIGS. 2B and 3B, the second mode signal M2 is supplied to the CCD chip 11 and the drive control unit 12A. At this time, the changeover switch 13 makes four sets of eight consecutive vertical transfer gate electrodes into four sets, and sets the vertical transfer gate electrodes V1 and V2, V3 and V4, V5 and V6, and V7 and V8. Are assigned vertical transfer drive clock signals φ1, φ2, φ3 and φ4, respectively.

  Next, the signal charge transfer state by the above-mentioned 8-electrode 4-phase driving method will be described.

  FIG. 4 shows the driving method of the solid-state imaging device shown in FIG. 2, in which the four-phase vertical transfer driving clock signals φ1 to φ4 are supplied in succession for each of the eight continuous vertical transfer gate electrodes in the second mode. 4A and 4B are diagrams for explaining the transfer state of signal charges in the case where four sets are assigned, wherein FIG. 4A is a timing chart of the four-phase vertical transfer drive clock signal, and FIG. 4B is the potential of the vertical transfer unit. It is a transition diagram. In FIG. 4A, the horizontal axis indicates time t, the vertical axis indicates the signal waveform, and the vertical axis indicates the signal waveform, with the overlap time of one charge transfer pulse and another charge transfer pulse as a unit time. The vertical axis indicates the time t, and the horizontal axis indicates the vertical position of the vertical transfer unit and its potential.

  For example, the photodiodes PD1 to PD10 are arranged in the vertical direction and connected to one vertical transfer unit 1 as shown in FIG. In the vertical transfer unit 1, four vertical transfer gate electrodes are provided for each photodiode PD, and eight vertical transfer gate electrodes V1 to V8 are sequentially provided in the direction of the horizontal transfer unit 2. ing. Vertical transfer drive clock signals φ1 to φ4 are supplied to the eight vertical transfer gate electrodes. In FIG. 4B, signal charges are accumulated at a low potential, and the state in which the signal charges 4 are transferred in the vertical transfer unit 1 according to the potential transition is indicated by hatching.

  At time t = 0, the charge 4 is located in the vertical transfer unit 1 adjacent to the photodiode PD5. With the passage of time, the charge 4 is transferred in the vertical direction (left direction in the figure).

  At time t = 16, the charge 4 is located in the vertical transfer unit 1 adjacent to the photodiode PD1. Therefore, the time required for charge transfer of the signal charge 4 from the position adjacent to the photodiode PD5 to the position adjacent to the photodiode PD1 is 16 cycles.

  As described above, in the second mode, when compared with the vertical pixel thinning readout mode in which signal charges are read from one pixel by thinning out three pixels out of four pixels arranged in the vertical direction as in the prior art, it is adjacent to the photodiode PD5. The time required to transfer the signal charge 4 from the position to the position adjacent to the photodiode PD1 is 32 cycles in the prior art disclosed in Patent Document 1. On the other hand, in this embodiment, the number of cycles is 16 and the vertical transfer time can be halved compared to the prior art.

  Furthermore, according to the present embodiment, the vertical transfer time can be shortened in the same manner as the prior art disclosed in Patent Document 2. Further, according to the present embodiment, as shown in FIG. 2, the vertical transfer control unit 12A includes only the four-phase drive control unit 12a and does not require the 16-phase drive control unit disclosed in Patent Document 2. As for the number of electrodes of the solid-state imaging device, the 16 vertical transfer gate electrodes as disclosed in Patent Document 2 are not necessary and are 8 in this embodiment. In the solid-state imaging device including this, it is advantageous in reducing the manufacturing cost, reducing the chip size, and reducing the power consumption.

  In the vertical transfer control unit 12A of the above embodiment, a four-phase drive control unit 12a that outputs a four-phase drive signal for driving each vertical transfer gate electrode constituting the vertical transfer unit 1 as a charge transfer unit, and a vertical direction The allocation of the four-phase drive signal to each vertical transfer gate electrode is switched in accordance with the first mode and the second mode in which the readout of each signal charge from the photodiode PD as the photoelectric conversion means arranged in a row is different from each other However, the present invention is not limited to this, and the switching function of the changeover switch means 13 can be included in the four-phase drive control unit 12a. For example, when the four-phase drive signal is φ1 to φ4 and each vertical transfer gate electrode is V1 to V8, the four-phase drive control unit may be wired to each vertical transfer gate electrode V1 to V8. In the first mode, the 4-phase drive signal φ1 is applied to the vertical transfer gate electrodes V1 and V5, the 4-phase drive signal φ2 is applied to the vertical transfer gate electrodes V2 and V6, and the 4-phase drive signal φ3 is applied to the vertical transfer gate electrodes V3 and V7. The four-phase drive controller may control the output of the four-phase drive signals φ1 to φ4 so that the four-phase drive signal φ4 is applied to the vertical transfer gate electrodes V4 and V8. In the second mode, the 4-phase drive signal φ1 is applied to the vertical transfer gate electrodes V1 and V2, the 4-phase drive signal φ2 is applied to the vertical transfer gate electrodes V3 and V4, and the 4-phase drive signal φ3 is applied to the vertical transfer gate electrode V5. The four-phase drive control unit may control the output of the four-phase drive signals φ1 to φ4 so that the four-phase drive signal φ4 is applied to the vertical transfer gate electrodes V7 and V8 at V6.

  That is, the four-phase drive control means (four-phase drive control unit) as the multi-phase drive control means is different from each other in how to read each signal charge from the photodiode PD as the photoelectric conversion means arranged in the vertical direction. Depending on the mode and the second mode, the output allocation of the four-phase drive signals φ1 to φ4 as the multi-phase drive signals to the charge transfer gate electrodes V1 to V8 is changed, and each of the components constituting the vertical transfer unit 1 is changed. The output of the four-phase drive signals φ1 to φ4 for driving the charge transfer gate electrodes V1 to V8 is controlled. According to this mode, the output assignment of the four-phase drive signals φ1 to φ4 to the charge transfer gate electrodes V1 to V8 is performed for each of n (n; a natural number of 2 or more) charge transfer gate electrodes consecutive in the first mode. Each of the n-phase drive signals is assigned to each of the charge transfer gate electrodes, and in the second mode, each of the 2n consecutive charge transfer gate electrodes is divided into n sets, and n sets for each set. Assign each of the phase drive signals.

  In the above embodiment, the four-phase drive control unit 12a is a multi-phase control unit that controls the vertical transfer unit 1, the four-phase drive signals are φ1 to φ4, and the vertical transfer gate electrodes are V1 to V8. Although the case of the four-phase vertical drive method has been described, the present invention is not limited to this, and a three-electrode three-phase vertical drive method may be used, and three phases may be used because a barrier must be formed before and after the signal charge when the signal charge is read. Therefore, the multi-phase control means may be a three-phase drive control unit, the three-phase drive signal may be φ1 to φ3, and each vertical transfer gate electrode may be V1 to V6. In this case, in the first mode, the three-phase drive signal φ1 is applied to the vertical transfer gate electrodes V1 and V4, the three-phase drive signal φ2 is applied to the vertical transfer gate electrodes V2 and V5, and the three-phase drive signal φ3 is applied to the vertical transfer gate. The changeover switch means 13 may be controlled to be applied to the electrodes V3 and V6, or the phase drive control unit may control the output of the three-phase drive signals φ1 to φ3. In the second mode, the three-phase drive signal φ1 is applied to the vertical transfer gate electrodes V1 and V2, the three-phase drive signal φ2 is applied to the vertical transfer gate electrodes V3 and V4, and the three-phase drive signal φ3 is applied to the vertical transfer gate electrode V5. The changeover switch means 13 may be controlled to be applied to V6, or the three-phase drive control unit may control the output of the three-phase drive signals φ1 to φ3.

  Furthermore, in the above embodiment, as the second mode, the vertical pixel thinning readout mode in which signal charges are read from one pixel by thinning out three pixels out of four pixels arranged in the vertical direction has been described as an example. In both the vertical thinning rate and the vertical thinning method, the vertical transfer time can be greatly reduced as compared with the conventional four-electrode four-phase vertical driving method. Further, when the pixels to be read are thinned out and then subjected to pixel addition by a horizontal transfer unit or an adder provided separately, the vertical transfer time can be similarly reduced.

  Further, in the above-described embodiment, four-phase drive signals are assigned to the vertical transfer gate electrodes for each of the four vertical transfer gate electrodes that are continuous with each other in the first mode, and eight sheets are assigned in the second mode. Although a case has been described in which each of the two consecutive charge transfer gate electrodes is assigned to four sets, and each of the four-phase drive signals φ1 to φ4 is assigned to each set, the present invention is not limited to this, but the second mode In some cases, the present invention can also be applied to a case in which each of 3 × 4 consecutive charge transfer gate electrodes is assigned to each of four sets of four-phase drive signals φ1 to φ4. Thus, high-speed charge transfer can be performed in the vertical transfer unit 1. In other words, in general, in the second mode, m × n (m is a natural number of 2 or more, n is a natural number of 3 or more) n consecutive sets of m consecutive each charge transfer gate electrodes. The present invention can also be applied when each of the n-phase drive signals φ1 to φn is assigned to each set. In the above embodiment, two vertical transfer gate electrodes are used as one set. However, the number of the vertical transfer gate electrodes used as one set has a limit value in relation to the vertical thinning rate.

  Furthermore, in the above-described embodiment, the interline transfer type CCD is described as an example of the solid-state imaging device. However, the above effect can be similarly expected for a frame interline transfer type CCD having a storage area. Needless to say, you can.

  Furthermore, in the above embodiment, two vertical transfer gate electrodes are used as one set. However, the present invention is not limited to this, and as in the case of the vertical transfer gate electrodes, two horizontal transfer gate electrodes may be used as one set. Alternatively, two sets of vertical transfer gate electrodes and horizontal transfer gate electrodes (charge transfer gate electrodes) may be used as one set, and the charge transfer speed can be increased.

  Although not particularly described in the above embodiment, a digital camera such as a digital video camera or a digital still camera using the solid-state imaging device 20 of the above embodiment as an imaging unit, an image input camera, a scanner, a facsimile, An electronic information device such as a camera-equipped mobile phone device will be described. The electronic information apparatus of the present invention is a recording that records data after performing predetermined signal processing for recording high-quality image data obtained by using at least one of the solid-state imaging device 20 of the above-described embodiment of the present invention as an imaging unit. A memory unit such as a medium; display means such as a liquid crystal display device that displays the image data on a display screen such as a liquid crystal display screen after performing predetermined signal processing for display; and a predetermined signal for communication of the image data It has at least one of communication means such as a transmission / reception device that performs communication processing after processing and image output means for printing (printing) and outputting (printing out) the image data.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention includes a solid-state imaging device such as an interline transfer type CCD or a frame interline transfer type, and reads out charges from the photoelectric conversion means in different readout modes such as an all pixel readout mode and a vertical pixel thinning readout mode. In the solid-state imaging device and the solid-state imaging element driving method that can be performed, the vertical transfer time can be shortened in the vertical pixel thinning readout mode that requires high-speed readout, as compared with the prior art disclosed in Patent Document 1.

  Furthermore, compared with the prior art of Patent Document 2, the vertical transfer control unit does not require a 16-phase drive control unit with only a 4-phase drive control unit, and is used to connect the vertical transfer control unit and the vertical transfer gate electrode. Since the number of internal wirings and electrode pads may be small, the manufacturing cost of the solid-state imaging device and the solid-state imaging device can be reduced, reduced, and power consumption can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the solid-state image sensor which concerns on embodiment of this invention, and its drive method, Comprising: (a) is a schematic diagram which shows the solid-state image sensor and its drive method in the all-pixel read-out mode as 1st mode. (B) is a schematic diagram showing a solid-state imaging device and a driving method thereof in the vertical pixel thinning readout mode as the second mode. FIG. 2 is a block diagram illustrating a configuration example of a main part of a solid-state imaging device including the solid-state imaging device of FIG. 1 and a vertical transfer control unit that drives and controls the solid-state imaging device, wherein FIG. b) is a block diagram showing the second mode. FIGS. 3A and 3B are circuit diagrams for explaining a configuration example of a vertical charge transfer control unit including the changeover switch unit of FIG. 2, wherein FIG. 3A is a circuit diagram illustrating an operation state in a first mode, and FIG. It is a circuit diagram which shows the operation state at the time. In the solid-state imaging device driving method of FIG. 2, in the second mode, the four-phase vertical transfer drive clock signals φ1 to φ4 are set to four sets of eight consecutive vertical transfer gate electrodes. FIG. 4 is a diagram for explaining a signal charge transfer state in the case of assignment, where (a) is a timing chart of the four-phase vertical transfer drive clock signal, and (b) is a potential transition diagram of the vertical transfer unit. . FIG. 7 is a diagram for explaining a conventional solid-state imaging device disclosed in Patent Document 1 and a driving method thereof; FIG. 5A illustrates a solid-state imaging device and a driving method thereof in an all-pixel readout mode as a first mode. FIG. 5B is a schematic diagram illustrating a solid-state imaging device and a driving method thereof in the vertical pixel thinning readout mode as the second mode. FIG. 6 is a diagram for explaining the charge transfer state of signal charges when the four-phase vertical transfer drive clock signals φ1 to φ4 are assigned to the continuous vertical transfer gate electrodes V1 to V4 in the solid-state imaging device of FIG. (A) is a timing chart of the four-phase vertical transfer drive clock signal, and (b) is a potential transition diagram of the vertical transfer unit. It is a figure for demonstrating the conventional solid-state imaging device disclosed by patent document 2, Comprising: (a) shows the time of 1st mode, (b) is a schematic diagram which shows the time of 2nd mode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Vertical transfer part 2 Horizontal transfer part 3 Output part 4 Signal charge 10 Solid-state image sensor 11 CCD chip 12A Vertical transfer control part 12a Four-phase drive control part 13 Changeover switch 20 Solid-state imaging device PD Photodiode φ1-φ4 Four-phase drive signal M1 1st mode signal M2 2nd mode signal

Claims (20)

A solid-state imaging device having a plurality of photoelectric conversion means for converting received light into signal charges, and a charge transfer means for transferring each signal charge read from the plurality of photoelectric conversion means in a predetermined direction;
A plurality of charge transfer gate electrodes constituting the charge transfer means are provided in accordance with the first mode and the second mode in which the respective signal charges are read out from the photoelectric conversion means arranged in parallel with the predetermined direction. A solid-state imaging device comprising: a plurality of phase drive control means for outputting a plurality of phase drive signals for driving the charge transfer gate electrodes by changing the output assignment of the phase drive signals.   In the first mode, each of the n-phase drive signals is assigned to each of the charge transfer gate electrodes for each of n (n: a natural number of 2 or more) consecutive charge transfer gate electrodes in the first mode, In the second mode, m × n (m is a natural number of 2 or more, n is a natural number of 3 or more) n consecutive groups for each of the consecutive charge transfer gate electrodes, n for each set. The solid-state imaging device according to claim 1, wherein each of the phase drive signals is assigned. A solid-state imaging device having a plurality of photoelectric conversion means for converting received light into signal charges, and a charge transfer means for transferring each signal charge read from the plurality of photoelectric conversion means in a predetermined direction;
Multi-phase drive control means for outputting a multi-phase drive signal for driving each charge transfer gate electrode constituting the charge transfer means;
Allocation of the plurality of phase driving signals to the charge transfer gate electrodes in accordance with the first mode and the second mode in which the reading methods of the signal charges from the photoelectric conversion means arranged in parallel in the predetermined direction are different from each other. A solid-state imaging device having changeover switch means for switching between.   The change-over switch means assigns each of n-phase drive signals to each of the charge transfer gate electrodes for each of n (n; a natural number of 2 or more) continuous in the first mode. In the second mode, m × n (m is a natural number greater than or equal to 2 and n is a natural number greater than or equal to 3) n consecutive m for each of the consecutive charge transfer gate electrodes is set for each set. The solid-state imaging device according to claim 3, wherein switching is performed so as to assign each of the n-phase drive signals.   5. The solid-state imaging device according to claim 1, wherein the multi-phase drive signal is assigned to each of the charge transfer gate electrodes so that a charge transfer speed is a normal speed or a high speed.   5. The solid-state imaging device according to claim 2, wherein n is 3 or 4.   5. The solid-state imaging device according to claim 2, wherein m is 2 or 3.   6. The first mode is an all-pixel readout mode in which a charge transfer speed is a normal speed mode, and the second mode is a vertical pixel thinning readout mode in which the charge transfer speed is a high speed mode. The solid-state imaging device described.   The solid-state imaging device according to claim 8, wherein in the second mode, the signal charges are read out by thinning out three pixels for every four pixels of the photoelectric conversion means arranged in the vertical direction.   The charge transfer means is at least one of a vertical charge transfer means and a horizontal charge transfer means. When the charge transfer means is the vertical charge transfer means, the predetermined direction is a vertical charge transfer direction, and the charge transfer means is In the case of the horizontal charge transfer means, the predetermined direction is a horizontal charge transfer direction. When the charge transfer means is the vertical charge transfer means and the horizontal charge transfer means, the predetermined direction is the vertical charge transfer direction and the horizontal charge transfer direction. The solid-state imaging device according to claim 1, which is in a charge transfer direction.   The solid-state imaging device according to claim 1, wherein the solid-state imaging device is an interline transfer type CCD or a frame interline transfer type CCD. A solid-state imaging device driving method in which received light is converted into signal charges by photoelectric conversion means, and signal charges read from the photoelectric conversion means are transferred in a predetermined direction by charge transfer means using a plurality of phase drive signals Because
A plurality of phases with respect to each charge transfer gate electrode constituting the charge transfer means according to the first mode and the second mode, which differ in how the signal charges are read from the photoelectric conversion means arranged in parallel in the predetermined direction. A method for driving a solid-state imaging device that switches assignment of drive signals.   In the first mode, an n-phase drive signal is assigned to each of the n (n: a natural number greater than or equal to 2) charge transfer gate electrodes that are continuous with each other, and an n-phase drive signal is assigned to each of the charge transfer gate electrodes. , M × n (m is a natural number of 2 or more, n is a natural number of 3 or more) n consecutive sets of m consecutive charge transfer gate electrodes for each set, and an n-phase drive signal for each set The method for driving a solid-state imaging device according to claim 12, wherein each is assigned.   The method of driving a solid-state imaging device according to claim 13, wherein n is 3 or 4.   The method of driving a solid-state imaging device according to claim 13, wherein the m is 2 or 3.   The solid state according to claim 12 or 13, wherein the first mode is an all-pixel readout mode and a charge transfer speed is a normal speed mode, and the second mode is a vertical pixel thinning readout mode and the charge transfer speed is a high-speed mode. Driving method of image sensor.   The solid-state imaging device driving method according to claim 16, wherein in the second mode, the signal charges are read out by thinning out three pixels for every four pixels of the photoelectric conversion means arranged in the vertical direction.   The charge transfer means is at least one of a vertical charge transfer means and a horizontal charge transfer means. When the charge transfer means is the vertical charge transfer means, the predetermined direction is a vertical charge transfer direction, and the charge transfer means is In the case of the horizontal charge transfer means, the predetermined direction is a horizontal charge transfer direction. When the charge transfer means is the vertical charge transfer means and the horizontal charge transfer means, the predetermined direction is the vertical charge transfer direction and the horizontal charge transfer direction. The solid-state imaging device driving method according to claim 12, wherein the driving direction is a charge transfer direction.   The solid-state imaging device driving method according to claim 12, wherein the solid-state imaging device is an interline transfer type CCD or a frame interline transfer type CCD.   An electronic information device using the solid-state imaging device according to claim 1 for an imaging unit.

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