JP4149591B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device that outputs an increased number of lines of image signals obtained by a solid-state imaging device.
[0002]
[Prior art]
When monitoring a moving image taken with a solid-state imaging device with a display device, the number of pixels in the vertical direction of a CCD (Charge Coupled Device) image sensor (hereinafter referred to as CCD) in the solid-state imaging device is less than the number of lines of the display device The number of lines of the image signal output from the solid-state imaging device is smaller than the number of lines displayed on the display device. For this reason, in the display device, the image is displayed in the form of being crushed in the vertical direction at the upper part of the screen, and the lower part of the screen is not displayed. Conventionally, in order to solve such a problem, in a solid-state imaging device, an image signal read out from a CCD is temporarily stored in a frame image memory or a field image memory, and the stored image signal is read out appropriately to obtain a DSP (Digital Signal Processor). For example, every time 6 lines are output, the same image signal as the 6th line is output for the 7th line (simple interpolation), and the number of lines is adjusted to the number of lines of the display device and output to the display device. It was.
[0003]
[Problems to be solved by the invention]
However, since the above-described solid-state imaging device uses a large-capacity image memory such as a frame image memory or a field image memory, there is a problem that power consumption increases. In particular, in portable small movies, electronic still cameras, and the like, an increase in power consumption due to the image memory has been a problem.
[0004]
In the solid-state imaging device described above, a large amount of data read from the CCD is stored in the frame image memory or field image memory, or the stored data is read out and processed by the DSP, so that the data bus is used for the data transfer. There is a problem that the system performance is degraded because it is almost occupied.
[0005]
An object of the present invention is to provide a solid-state imaging device that solves the above-described drawbacks of the prior art and interpolates lines without using a frame image memory or a field image memory.
[0006]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides a plurality of photoelectric conversion elements arranged in a matrix, and a vertical transfer path that transfers signal charges accumulated in the photoelectric conversion elements in a vertical direction for each column according to a vertical drive pulse. And a horizontal transfer path for transferring the signal charge transferred in the vertical transfer path in the horizontal direction according to the horizontal drive pulse, and an output circuit for converting the signal charge transferred in the horizontal transfer path into an electric signal and outputting the electric signal In a solid-state imaging device having an imaging device and driving means for outputting a vertical driving pulse during a horizontal blanking period and repeatedly outputting a horizontal driving pulse during a horizontal scanning period, this device is based on a signal output from the solid-state imaging device. A signal processing unit that generates and outputs a display signal, a control unit that controls the driving unit to temporarily stop the output of the vertical driving pulse at a predetermined timing; And a line memory for storing a display signal for one horizontal scanning period generated immediately before the output of the vertical drive pulse is temporarily stopped by the processing means by the processing means. The signal processing means includes the vertical driving means of the control means. When the output of the vertical drive pulse is temporarily stopped according to the control, a display signal for one horizontal scanning period is read from the line memory and output.
[0007]
The present invention also includes a plurality of photoelectric conversion elements arranged in a matrix, a vertical transfer path for transferring signal charges accumulated in the photoelectric conversion elements in a vertical direction for each column according to a vertical drive pulse, and a vertical transfer path. A solid-state imaging device including a horizontal transfer path that transfers the transferred signal charge in the horizontal direction according to a horizontal drive pulse; an output circuit that converts the signal charge transferred through the horizontal transfer path into an electrical signal; In a solid-state imaging device having a driving unit that outputs a vertical driving pulse during a ranking period and repeatedly outputs a horizontal driving pulse during a horizontal scanning period, the apparatus includes three memories, and one memory is stored from the three memories. A signal for one horizontal scanning period output from the solid-state image pickup device is repeatedly selected in a predetermined order for each horizontal scanning period, and stored in the other two memories. A signal processing means for generating and outputting display signals for a horizontal scanning period of 1 / N for one line based on a signal of one horizontal scanning period, and controlling the driving means to output a vertical driving pulse at a predetermined timing. Control means for temporarily stopping at the time, the signal processing means, when the vertical drive means pauses the output of the vertical drive pulse according to the control of the control means, in the two memories that were not previously selected of the three memos A display signal having a horizontal scanning period of 1 / N is generated and output for N lines based on the signals stored in one horizontal scanning period.
[0008]
In the present invention, a plurality of pixels including photoelectric conversion elements and vertical selection switches are arranged in a matrix, and the plurality of pixels are connected by vertical signal lines for each column and connected by control lines for each row. Each pixel is provided with a pixel array for outputting a signal charge accumulated in the photoelectric conversion element to the vertical signal line by a vertical selection switch when a vertical scanning pulse is applied to the control line, and a horizontal scanning pulse for each vertical signal line. A plurality of horizontal selection switches for outputting a signal from the vertical signal line to the signal output line, a vertical scanning means for sequentially selecting a control line and applying a vertical scanning pulse, and a horizontal selection switch. A MOS type imaging device including a horizontal scanning means for applying a horizontal scanning pulse and a control means for controlling the vertical scanning means to temporarily stop selection of a control line at a predetermined timing. Vertical scanning means of the image elements, when the pause selection control lines according to the control of the control means, and applying again the vertical scanning signal to the last selected control lines.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0010]
FIG. 1 is a block diagram showing a first embodiment of a solid-state imaging device according to the present invention. In FIG. 1, reference numeral 10 denotes a solid-state image sensor that outputs an electrical signal corresponding to an optical image of a subject. FIG. 2 shows an example of the solid-state imaging device 10, which is a four-phase drive interline CCD. In the CCD 10, a large number of photoelectric conversion elements such as photodiodes 40 are arranged in a matrix in the imaging region, and a vertical transfer path 42 is arranged adjacent to each column of the photodiodes 40. Each photodiode 40 is connected to the vertical transfer path 42 via the transfer gate 44. The lower end of each vertical transfer path 42 is connected to the horizontal transfer path 46, and the left end of the horizontal transfer path 46 is connected to the output circuit 48.
[0011]
Each vertical transfer path 42 has a vertical drive pulse φ for transferring signal charges in the direction of the horizontal transfer path 46. _V1 ~ Φ _V4 Are supplied during the horizontal blanking period, and the horizontal transfer path 46 has a horizontal drive pulse φ for transferring the signal charge in the direction of the output circuit 48. _H1 , Φ _H2 Are repeatedly supplied during the horizontal scanning period. In the vertical blanking period, for example, when a field shift pulse is supplied to each transfer gate 44 in each odd-numbered row counted from the side closer to the horizontal transfer path 46, the signal charge accumulated in the photodiode 40 is transferred to the transfer gate. It is moved to the vertical transfer path 42 through 44.
[0012]
The vertical transfer path 42 has a vertical drive pulse φ _V1 ~ Φ _V4 The signal charges transferred from the respective photodiodes 40 are transferred for one row (one line) in the direction of the horizontal transfer path 46. The signal charge that has reached the horizontal transfer path 46 is transferred to the horizontal transfer path 46. The horizontal transfer path 46 has a horizontal drive pulse φ _H1 , Φ _H2 Accordingly, each signal charge transferred from the vertical transfer path 42 is transferred in the direction of the output circuit 48. As a result, the signal charge for one line transferred to the horizontal transfer path 46 sequentially reaches the output circuit 48 within the horizontal scanning period. The output circuit 48 converts the signal charges that arrive sequentially into an electric signal (analog signal) and outputs the electric signal.
[0013]
In this way, the CCD 10 has a vertical drive pulse φ _V1 ~ Φ _V4 Is supplied from the output circuit 48 for each line. When all the analog signals in one field are output, a field shift pulse is supplied to the even-numbered transfer gates 44 in the next blanking period, and the analog signal in the next field is output from the output circuit 48.
[0014]
Returning to FIG. 1, the A / D converter 12 receives the analog signal output from the CCD 10 and amplifies it to a predetermined level, and converts it into a digital signal (data) according to the timing signal from the timing signal generator 20. The data is converted and output to the DSP unit 14. The DSP unit 14 includes a microprocessor dedicated to digital signal processing, and performs predetermined processing on the data from the A / D conversion unit 12 to generate display data (or display image signals), which is then displayed on the display device 18. Output to.
[0015]
Further, the DSP unit 14 temporarily receives the data of one horizontal scanning period input from the A / D conversion unit 12 in the horizontal scanning period in the line memory 16 when the masking pulse generation notice signal 32 is given from the control circuit 28. When the masking pulse generation notification signal 34 is supplied from the control circuit 28, the data for one horizontal scanning period is read from the line memory 16 to generate display data, which is output to the display device 18. Since the DSP 14 usually has a built-in memory, if a part of the memory is used as the line memory 16, it is not necessary to provide a line memory separately. Further, when the data from the A / D converter 12 is stored in the line memory 16 for each horizontal scanning period, the above-described masking pulse generation notice signal 32 is not necessary.
[0016]
The display device 18 is, for example, a liquid crystal display, a CRT monitor, or the like, and displays an image based on display data output from the DSP unit 14. In the present embodiment, it is assumed that the number of lines of the display device 18 is larger than the number of photodiodes in the vertical direction in the CCD 10, that is, the number of lines. Therefore, the DSP 14 interpolates the lines so that the number of lines of display data matches the number of lines of the display device 18. The timing signal generation circuit 22 of the timing signal generation unit 20 generates a timing signal necessary for the operation of the A / D conversion unit 12 and the DSP unit 14, and also generates a timing signal necessary for generating a driving pulse of the CCD10. To do.
[0017]
The horizontal driving circuit 24 generates a horizontal driving pulse φ based on the timing signal generated by the timing generating circuit 22. _H1 , Φ _H2 Are repeatedly generated at a predetermined timing in each horizontal scanning period and output to the CCD 10. The vertical drive circuit 26 generates a vertical drive pulse φ based on the timing signal generated by the timing generation circuit 22. _V1 ~ Φ _V4 Are generated at a predetermined timing in each horizontal blanking period and output to the CCD 10. However, when the masking pulse 30 is given from the control circuit 28, the output is temporarily stopped. The vertical drive circuit 26 supplies a field shift pulse to the transfer gate 44 of the CCD 10 at a predetermined timing.
[0018]
The control circuit 28 generates a masking pulse 30 according to a predetermined procedure and outputs it to the vertical drive circuit 26. For example, depending on the ratio of the number of lines of the display device 18 and the number of lines of the CCD 10, the vertical drive pulse φ _V1 ~ Φ _V4 The masking pulse 30 is generated to stop the output at a rate of once every several times, or the masking pulse 30 is applied at a predetermined timing according to the difference between the number of lines of the display device 18 and the number of lines of the CCD 10 Generate.
[0019]
Further, the control circuit 28 outputs a masking pulse generation warning signal 32 for notifying the generation of the masking pulse 30 to the DSP unit 14 at the time one horizontal scanning period before the masking pulse 30 is output, and outputs the masking pulse 30. Then, a masking pulse generation notification signal 34 for notifying the generation of the masking pulse 30 is output to the DSP unit 14. However, as described above, when the data from the A / D converter 12 is stored in the line memory 16 for each horizontal scanning period in the DSP 14, the masking pulse generation warning signal 32 is unnecessary. The masking pulse 30 may be generated by the DSP 14 or another microcomputer. Alternatively, data may be given to the control circuit 28 from the outside, and the timing of the masking pulse 30 may be controlled based on the data.
[0020]
Next, the operation of the solid-state imaging device of FIG. 1 will be described using the timing chart of FIG. 3A to 3D show the vertical drive pulse φ supplied from the vertical drive circuit 26 to the CCD 10. _V1 ~ Φ _V4 FIG. 3E shows a horizontal drive pulse φ supplied from the horizontal drive circuit 24 to the CCD 10. _H1 Or φ _H2 It is. However, in FIG. 3, in the horizontal blanking period of the horizontal scanning period H4, the vertical drive pulse φ _V1 ~ Φ _V4 Output has been paused.
[0021]
First, in the horizontal scanning period H1, the vertical drive pulse φ is applied to CCD10. _V1 ~ Φ _V4 And horizontal drive pulse φ _H1 , Φ _H2 Is supplied, the analog signal is output from the CCD 10 to the A / D converter 12, and the digital signal (data) is output from the A / D converter 12 to the DSP unit 14. D in Fig. 3 (f) _n-1 Is data output from the A / D converter 12 (hereinafter referred to as CCD output data). The DSP unit 14 performs predetermined processing on the CCD output data from the A / D conversion unit 12 to generate display data (or display image signal), and outputs this to the display unit 18. D in Fig. 3 (h) _n-1 Is display data. Similarly, the display data D is displayed in the horizontal scanning period H2. _n However, during the horizontal scanning period H3, the display data D _{n + 1} Are respectively output from the DSP section 14.
[0022]
However, in the horizontal scanning period H3, a masking pulse generation warning signal 32 is output from the control circuit 28 to the DSP unit 14 during the horizontal blanking period. When this masking pulse generation warning signal 32 is given, the DSP unit 14 receives the CCD output data D from the A / D converter 12. _{n + 1} To display data D _{n + 1} And its CCD output data D _{n + 1} Is stored in the line memory 16. D in Fig. 3 (g) _{n + 1} Indicates data stored in the line memory 16. The generated display data D _{n + 1} May be stored in the line memory 16.
[0023]
In the horizontal scanning period H4, the masking pulse 30 is output from the control circuit 28 to the vertical drive circuit 26 in the horizontal blanking period. In the vertical drive circuit 26, the vertical drive pulse φ supplied to the CCD 10 in accordance with the masking pulse 30 _V1 ~ Φ _V4 Stop the output of. In vertical transfer path 42 of CCD10, vertical drive pulse φ _V1 ~ Φ _V4 Therefore, the transfer of signal charges is stopped. The signal charge in the vertical transfer path 42 is the next vertical drive pulse φ _V1 ~ Φ _V4 Until it is supplied to the CCD 10, there is no signal charge transferred from the vertical transfer path 42 to the horizontal transfer path 46. Therefore, there is no signal charge in the horizontal transfer path 46, and the horizontal drive pulse φ _H1 , Φ _H2 However, the analog signal is not output from the output circuit 48. Therefore, the CCD output data is not output from the A / D converter 12.
[0024]
In the horizontal scanning period H4, the control circuit 28 outputs a masking pulse generation notification signal 34 to the DSP unit 14 when outputting the masking pulse 30 to the vertical drive circuit 26. The DSP unit 14 receives the data D stored in the line memory 16 when the masking pulse generation notification signal 34 is given. _{n + 1} Is read out and subjected to predetermined processing to display data D _{n + 1} Is generated and output to the display device 18. Therefore, as shown in FIG. 3 (h), the DSP section 14 displays the display data D output in the horizontal scanning period H3 in the horizontal scanning period H4. _{n + 1} Display data D with the same content as _{n + 1} Is output, which is an increase of one line.
[0025]
The DSP unit 14 displays the display data D generated in the line memory 16 during the horizontal scanning period H3. _{n + 1} When the masking pulse generation notification signal 34 is given, the display data D stored in the line memory 16 is given. _{n + 1} May be read out and output to the display device 18 as it is. In the present embodiment, the display data D one line before in the horizontal scanning period H4. _{n + 1} Is output as it is (simple interpolation), but other interpolation methods may be employed.
[0026]
In the next horizontal scanning period H5, the vertical drive pulse φ is applied to CCD10. _V1 ~ Φ _V4 And horizontal drive pulse φ _H1 , Φ _H2 Is supplied. Therefore, the analog signal of the next line of the analog signal output in the horizontal scanning period H3 is output from the CCD 10, and the CCD output data D is output from the A / D converter 12. _{n + 2} Is output from the DSP section 14 to display data D. _{n + 2} Is output. In the horizontal scanning period H5, the display data D is sent from the DSP unit 14 in the same manner as in the horizontal scanning period H5. _{n + 3} Is output.
[0027]
Thus, in this embodiment, the vertical drive pulse φ for CCD10 _V1 ~ Φ _V4 By temporarily stopping the supply of the analog signal for one line, the display data output one line before is output. As a result, the number of lines of display data output to the display device 18 increases by one line. For example, when the number of photodiodes 40 in CCD10 is 525 and the number of lines in display 18 is 625, vertical drive pulse φ for CCD10 _V1 ~ Φ _V4 Is temporarily stopped at a rate of once every five times, and each time the display data for one line output one line before is output, the number of lines is increased from five to six, and from 525 Can convert to 625.
[0028]
Therefore, according to the present embodiment, the number of lines can be increased without using a large-capacity image memory such as a frame image memory or a field image memory, so that power consumption can be greatly reduced. If a part of the memory built in the DSP unit 14 is used as the line memory 16, it is not necessary to provide a new line memory.
[0029]
Next, a second embodiment of the solid-state imaging device according to the present invention will be described. This solid-state imaging device is basically the same as the configuration of the solid-state imaging device shown in FIG. 1, and will be described here with reference to FIG. However, in this embodiment, it is assumed that the CCD 10 in FIG. 1 is provided with a color filter array based on the Bayer method, which is one method of the color filter array. FIG. 4 shows an example of the color filter array according to this Bayer method.
[0030]
In FIG. 4, R 1, G 2, and B are color filters that transmit red, green, and blue, respectively. First, G 1 is arranged in a checkered pattern, R and B are arranged in a checkered pattern in the remaining portion, and further, In consideration of the race operation, the same color filter is arranged in two pixels in the vertical direction. In addition, when this color filter array is used, a signal delayed by one line and a signal at the original time are required to calculate a luminance signal. In this embodiment, it is assumed that the DSP 14 in FIG. 1 includes a line memory (hereinafter referred to as a built-in line memory) for delaying a signal by one line, in addition to the line memory 16.
[0031]
The operation of the solid-state imaging device according to this embodiment will be described with reference to the timing chart of FIG. 5A to 5D show the vertical drive pulse φ. _V1 ~ Φ _V4 The vertical drive pulse φ in FIGS. 1 (a) to 1 (d) _V1 ~ Φ _V4 5 (e) shows the horizontal drive pulse φ. _H1 Or φ _H2 The horizontal drive pulse φ in FIG. _H1 , Φ _H2 Is the same. Also, the vertical drive pulse φ _V1 ~ Φ _V4 The output is temporarily stopped in the flat scanning period H4.
[0032]
First, in the horizontal scanning period H1, the vertical drive pulse φ is applied to CCD10. _V1 ~ Φ _V4 And horizontal drive pulse φ _H1 , Φ _H2 Is supplied from the A / D converter 12 to the CCD output data D shown in FIG. _n-1 Is output and input to the DSP section 14. In the DSP unit 14, the CCD output data D from the A / D converter 12 _n-1 And CCD output data D delayed by one line in the built-in line memory _n-2 To execute a predetermined process and display data D _{n-2, n-1} Is output to the display device 18. FIG. 5 (h) shows the display data D _{n-2, n-1} Indicates. Also, the DSP unit 14 receives the input CCD output data D. _n-1 Built-in line memory CCD output data D _n-2 Are sequentially stored after the are read. FIG. 5 (g) shows data stored in the built-in line memory.
[0033]
In the horizontal scanning periods H2 and H3, the display data D is the same as in the horizontal scanning period H1. _{n-1, n} , D _{n, n + 1} Is output to the display device 18. However, in the horizontal scanning period H3, the control circuit 28 outputs a masking pulse output notice signal 32 to the DSP unit 14 in the horizontal blanking period. When this masking pulse output warning signal 32 is given, the DSP unit 14 generates the display data D generated. _n , _{n + 1} Data D with the same content as _n , _{n + 1} Is stored in the line memory 16. FIG. 5 (i) shows data D stored in the line memory 16. _n , _{n + 1} Indicates.
[0034]
In the horizontal scanning period H4, the vertical drive pulse φ _V1 ~ Φ _V4 Is not supplied. Therefore, no analog signal is output from the CCD 10 and no CCD output data is output from the A / D converter 12. However, the control circuit 28 outputs a masking pulse generation notification signal 34 to the DSP unit 14 during the horizontal blanking period. When this masking pulse generation notification signal 34 is given, the DSP unit 14 receives the data D stored in the line memory 16. _n , _{n + 1} And display this for display data D _n , _{n + 1} Output as. As a result, the number of lines of display data is increased by one line.
[0035]
In the next horizontal scanning period H5, the vertical drive pulse φ is applied to CCD10. _V1 ~ Φ _V4 And horizontal drive pulse φ _H1 , Φ _H2 Is supplied from the A / D converter 12 to the CCD output data D. _{n + 1} CCD output data D of the next line _{n + 2} Is output and input to the DSP section 14. In the DSP section 14, the CCD output data D _{n + 2} CCD output data D stored in the built-in line memory _{n + 1} Display data based on D _{n + 1} , _{n + 2} Is generated and output to the display device 18. Also, the DSP unit 14 receives the input CCD output data D. _{n + 2} Is stored in the built-in line memory. Similarly, in the horizontal scanning period H6, the display data D _{n + 2} , _{n + 3} Is output to the display device 18. Thus, also in this embodiment, the same effect as in the case of the first embodiment can be obtained.
[0036]
Next, a third embodiment of the solid-state imaging device according to the present invention will be described. This solid-state imaging device has basically the same configuration as the solid-state imaging device of the second embodiment. However, the CCD 10 is a multi-pixel imaging device including a very large number of photodiodes, and the horizontal scanning period is twice that of the display device 18 (for example, twice the horizontal scanning period of the television system of 64.5 μsec). In this embodiment, the DSP unit 14 converts the CCD output data into display data whose horizontal scanning period is ½, and the DSP unit 14 converts one line (for example, 127 μsec) for the conversion. It is assumed that three line memories for storing data (hereinafter referred to as built-in line memories A, B, and C) are incorporated. In this embodiment, the line memory 16 of FIG. 1 is not necessary.
[0037]
The operation of the solid-state imaging device according to this embodiment will be described with reference to the timing chart of FIG. 6A to 6D show the vertical drive pulse φ. _V1 ~ Φ _V4 The vertical drive pulse φ in FIGS. 5 (a) to 5 (d) _V1 ~ Φ _V4 6 (e) shows the horizontal drive pulse φ. _H1 Or φ _H2 And the horizontal drive pulse φ in FIG. _H1 , Φ _H2 Is the same. Also, the vertical drive pulse φ _V1 ~ Φ _V4 Assume that the output is temporarily stopped in the horizontal scanning period H4.
[0038]
First, in the horizontal scanning period H1, the vertical drive pulse φ is applied to CCD10. _V1 ~ Φ _V4 And horizontal drive pulse φ _H1 , Φ _H2 Is supplied from the A / D converter 12 to the CCD output data D. _n-2 Is output and input to the DSP section 14. In the DSP section 14, the input CCD output data D _n-2 Are stored in the built-in line memory B. In this embodiment, it is assumed that CCD output data is stored repeatedly in the order of the built-in line memories B 1, A 2, C 3, and B 3 for each horizontal scanning period. 6 (g) to 6 (i) show data stored in the built-in line memories A to C. FIG.
[0039]
In the DSP section 14, the CCD output data D two lines before stored in the built-in line memory A _n-4 And the CCD output data D one line before stored in the built-in line memory C _n-3 And display data D with a horizontal scanning period of 1/2 (for example, 63.5 μsec) _n-4 , _n-3 Are repeatedly generated and output to the display unit 18. Similarly, in the horizontal scanning periods H2 and H3, the DSP 14 uses the CCD output data 2 lines before and 1 line before to display data D. _n-3 , _n-2 , D _n-2 , _n-1 Are repeatedly generated and output to the display unit 18. FIG. 6 (j) shows display data.
[0040]
In the horizontal scanning period H4, the vertical drive pulse φ _V1 ~ Φ _V4 Is not supplied. Therefore, no analog signal is output from the CCD 10 and no CCD output data is output from the A / D converter 12. However, the control circuit 28 outputs a masking pulse generation notification signal 34 to the DSP unit 14 during the horizontal blanking period. When the DSP unit 14 is supplied with the masking pulse generation notification signal 34, it performs the same operation as in the horizontal scanning period H3 and displays the display data D. _n-2 , _n-1 Are repeatedly generated and output to the display unit 18. Therefore, in the horizontal scanning period H4, as shown in FIG. 6 (j), the display data D in the flat scanning period H4 is displayed. _n-2 , _n-1 Display data with the same content as _n-2 , _n-1 The data is repeatedly output, and the display data is interpolated by two lines.
[0041]
In the horizontal scanning periods H5 and H6, the display data D is sent from the DSP unit 14 in the same manner as in the horizontal scanning period H1. _n-1 , _n , D _n , _{n + 1} Is output. In this embodiment, since the lines are interpolated using the signal processing built-in line memories A to C built in the DSP unit 14, no line memory for interpolation is required.
[0042]
The above-described embodiment is a case where the horizontal scanning period of the signal output from the image sensor is converted to 1/2, but can also be applied to a case where the horizontal scanning period is converted to 1/3. The display data in this case is shown in FIG. For example, in the horizontal scanning period H1 in FIG. 6 (k), the DSP section 14 receives the CCD output data D two lines before stored in the built-in line memory A. _n-4 And the CCD output data D one line before stored in the built-in line memory C _n-3 And display data D with a horizontal scanning period of 1/3 _n-4 , _n-3 Are generated three times and output to the display unit 18.
[0043]
The present embodiment is not limited to the case where the horizontal scanning period is converted to 1/2 or 1/3, but the horizontal scanning period is converted to 1 / N (N is a natural number of 2 or more). Of course, it can be applied to. In this case, the DSP unit 14 repeatedly generates display data having a horizontal scanning period of 1 / N in each horizontal scanning period (H1, H2, H3,...) N times and outputs the display data to the display unit 18.
[0044]
Next, a fourth embodiment of the solid-state imaging device according to the present invention will be described. This solid-state imaging device uses a MOS type imaging device as a solid-state imaging device. FIG. 7 shows an example of a MOS type image sensor. In this MOS type image pickup device, a large number of pixels 50 including photodiodes and vertical selection switches are arranged in a matrix in the image pickup region. The vertical selection switch of each pixel 50 is connected to the vertical scanning circuit 52 via the control line 54 for each row and to the horizontal selection switch 58 via the vertical signal line 56 for each column. Each horizontal selection switch 58 is connected to a horizontal scanning circuit 60 and a horizontal signal line 62.
[0045]
A vertical clock 64 is supplied to the vertical scanning circuit 52 in each horizontal blanking period. The vertical scanning circuit 52 generates vertical scanning pulses for sequentially selecting the pixels 50 for each row based on the vertical clock 64, and sequentially outputs them to the corresponding control lines 54. However, when the masking pulse 66 is given from the control circuit (not shown) during the horizontal blanking period, the vertical scanning circuit 52 temporarily stops the selection of the control line and performs vertical scanning again on the control line 54 that has output the previous vertical scanning pulse. Output a pulse. Then, when the vertical clock 64 is supplied thereafter, the vertical scanning circuit 52 selects the control line 54 next to the control line 54 that previously output the vertical scanning pulse and outputs a vertical scanning signal. .
[0046]
In each pixel 50, when a vertical scanning pulse is applied to the connected control line 54, the vertical selection switch is turned on, and the signal charge voltage accumulated in the photodiode is output to the vertical signal line 56. The photodiode of the pixel 50 to which the vertical scanning pulse is not applied continues to accumulate charges. The horizontal scanning circuit 60 generates a horizontal scanning pulse for sequentially selecting the signal charge voltage of each vertical signal line 56 based on the horizontal clock 68 repeatedly supplied during the horizontal scanning period, and outputs the horizontal scanning pulse to the horizontal selection switch 58.
[0047]
In each horizontal selection switch 58, when a horizontal scanning pulse is given from the horizontal scanning circuit 60, the signal charge voltage of the connected vertical signal line 56 is selected and output to the horizontal signal line 62. As a result, the signal charge voltage of each vertical signal line 56 is sequentially selected and output to the horizontal signal line 62 within the horizontal scanning period. In this way, the signal charge voltage accumulated in the photodiode of each pixel 50 is selected, for example, in the order from the upper row to the lower row in FIG. 7, and in each row from the left pixel to the right pixel. 62 is output as an analog signal.
[0048]
In the present embodiment, by utilizing the fact that the MOS type image pickup device 50 can perform nondestructive readout, the signal charge voltage is read out from each pixel in the same row for each horizontal scanning period in two consecutive horizontal scanning periods. Interpolation is performed. Specifically, the masking pulse 66 is supplied from the control circuit to the vertical scanning circuit 52 at a predetermined timing. When the masking pulse 66 is input, the vertical scanning circuit 52 outputs the vertical scanning pulse again to the control line 54 that has output the previous vertical scanning pulse. Therefore, each pixel 50 connected to the control line 54 outputs the signal charge voltage accumulated in the photodiode again to the vertical signal line 56 following the previous horizontal scanning period.
[0049]
On the other hand, a horizontal clock 68 is supplied to the horizontal scanning circuit 60 regardless of the supply of the masking pulse 66 to the vertical scanning circuit 52. The horizontal scanning circuit 60 sequentially generates horizontal scanning pulses based on the horizontal clock 68 and outputs the horizontal scanning pulses to each horizontal selection switch 58. Each horizontal selection switch 58 selects the signal charge voltage of the vertical signal line 56 according to the horizontal scanning pulse and outputs it to the horizontal signal line 62. As a result, an analog signal having the same contents as the analog signal output in the previous horizontal scanning period is output again to the horizontal signal line 62, and the number of analog signal lines is increased by one line. The masking pulse 66 is generated, for example, according to the ratio of the number of lines of the MOS type image pickup device and the number of lines of the display device.
[0050]
As described above, in this embodiment, by supplying the masking pulse 66 to the vertical scanning circuit 52, in the horizontal scanning period, each pixel in the previously selected row is selected again, and the signal charge voltage is read and output. After that, since the next row is selected sequentially, the number of lines can be increased by one line. In this case, a line memory for line interpolation is not necessary.
[0051]
【The invention's effect】
As described above, according to the present invention, since the vertical transfer of the signal charge in the solid-state imaging device is temporarily stopped and the line is interpolated by outputting the signal of the previous line, the frame image memory or the frame image It is not necessary to use a large-capacity memory such as a memory, and power consumption can be reduced. In addition, since it is not necessary to write or read data in a large-capacity memory, it is possible to avoid a decrease in system performance due to data bus occupancy.
[0052]
Further, by using a MOS type image pickup device as a solid-state image pickup device and reading out signals from two lines of pixels in the same row, it is possible to interpolate lines without using a line memory.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a solid-state imaging device according to the present invention.
2 is a diagram illustrating an example of a CCD image sensor in the solid-state imaging device of FIG. 1;
3 is a timing chart showing the operation of the solid-state imaging device of FIG.
FIG. 4 is a diagram illustrating an arrangement of color filters by a Bayer method.
FIG. 5 is a timing chart showing the operation of the second embodiment of the solid-state imaging device according to the present invention;
FIG. 6 is a timing chart showing the operation of the third embodiment of the solid-state imaging device according to the present invention.
FIG. 7 is a diagram showing an example of a MOS type image pickup device in a fourth embodiment of the solid-state image pickup device according to the present invention.
[Explanation of symbols]
10 CCD
12 A / D converter
14 DSP section
16 line memory
18 Display
20 Timing signal generator
22 Timing signal generator
24 Horizontal drive circuit
26 Vertical drive circuit
28 Control circuit

Claims (7)

A plurality of photoelectric conversion elements arranged in a matrix, a vertical transfer path for transferring signal charges accumulated in the photoelectric conversion elements in a vertical direction for each column according to a vertical drive pulse, and a signal transferred through the vertical transfer path A solid-state imaging device including a horizontal transfer path that transfers charges in the horizontal direction according to a horizontal drive pulse, and an output circuit that converts the signal charge transferred through the horizontal transfer path into an electrical signal and outputs the electrical signal; and a horizontal blanking period In a solid-state imaging device having a driving unit that outputs the vertical driving pulse and repeatedly outputs the horizontal driving pulse during a horizontal scanning period, the device includes:
Signal processing means for generating and outputting a display signal based on a signal output from the solid-state imaging device;
Control means for controlling the drive means to mask the output of the vertical drive pulse at a predetermined timing;
A line memory storing a display signal for one horizontal scanning period generated immediately before masking the output of a vertical drive pulse by at least the drive means by the signal processing means,
The signal processing unit reads and outputs a display signal for one horizontal scanning period from the line memory when the vertical driving unit masks the output of a vertical driving pulse in accordance with the control of the control unit. Imaging device. The solid-state imaging device according to claim 1, wherein the solid-state imaging device includes a Bayer color filter array. 2. The solid-state imaging device according to claim 1, wherein the line memory is built in the signal processing means. 2. The solid-state imaging device according to claim 1, wherein the line memory stores a display signal generated by the signal processing means for each horizontal scanning period. A plurality of photoelectric conversion elements arranged in a matrix, a vertical transfer path for transferring signal charges accumulated in the photoelectric conversion elements in a vertical direction for each column according to a vertical drive pulse, and a signal transferred through the vertical transfer path A solid-state imaging device including a horizontal transfer path that transfers charges in the horizontal direction according to a horizontal drive pulse, and an output circuit that converts the signal charge transferred through the horizontal transfer path into an electrical signal and outputs the electrical signal; and a horizontal blanking period In a solid-state imaging device having a driving unit that outputs the vertical driving pulse and repeatedly outputs the horizontal driving pulse during a horizontal scanning period, the device includes:
It has three memories, one of the three memories is repeatedly selected in a predetermined order for each horizontal scanning period, stores a signal of one horizontal scanning period output from the solid-state imaging device, and stores the other two Signal processing means for generating and outputting N lines of display signals having a horizontal scanning period of 1 / N (N is a natural number of 2 or more) based on signals of one horizontal scanning period respectively stored in one memory;
Control means for controlling the drive means to temporarily stop the output of the vertical drive pulse at a predetermined timing,
The signal processing means are respectively stored in two memories that are not selected last time among the three memos when the vertical driving means temporarily stops the output of a vertical driving pulse in accordance with the control of the control means. A solid-state imaging device characterized in that a display signal having a horizontal scanning period of 1 / N is generated and output for N lines based on a signal of a horizontal scanning period. 6. The apparatus according to claim 1, wherein the control unit stops the output of the vertical drive pulse in accordance with a ratio between the number of lines of the solid-state imaging device and the number of lines of the display image signal. A solid-state imaging device. A plurality of pixels including photoelectric conversion elements and vertical selection switches are arranged in a matrix, and the plurality of pixels are connected by vertical signal lines for each column and connected by control lines for each row. a pixel array to nondestructive read to the vertical signal lines by the vertical selection switch a voltage of the signal charge accumulated in the photoelectric conversion element when the vertical scanning pulse is applied,
A plurality of horizontal selection switches provided for each of the vertical signal lines and outputting the signal voltage to a signal output line when a horizontal scanning pulse is applied;
Vertical scanning means for sequentially selecting the control lines and applying the vertical scanning pulse;
A MOS type image pickup device including horizontal scanning means for sequentially selecting the horizontal selection switch and applying a horizontal scanning pulse;
Control for controlling the vertical scanning means to temporarily stop selection of the control line at a predetermined timing according to a ratio between the number of lines of the pixel and the number of lines of the display device that displays the output of the MOS type image pickup device Means,
The vertical scanning unit of the MOS type imaging device applies a vertical scanning signal again to the previously selected control line when the selection of the control line is temporarily stopped according to the control of the control unit.

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