JP3666563B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus mainly for taking still images.
[0002]
[Prior art]
Conventionally, the high-quality still image pickup apparatus using the moving picture signal processing method, Japanese Unexamined 7-298140 discloses (hereinafter, prior art hereinafter) are known those described in.
[0003]
The conventional imaging apparatus will be described below.
[0004]
This conventional imaging apparatus includes a solid-state imaging device (hereinafter referred to as a CCD) having a plurality of photoelectric conversion elements arranged in a matrix, and a diaphragm having a light amount adjusting unit and a light shielding unit. And a field color difference line sequential type color filter.
[0005]
The operation timing in this conventional imaging apparatus will be described more specifically with reference to FIG.
[0006]
16, 401 VD signal as a reference signal in the vertical direction, 402 the still image shooting pulse, 403 shading operation, 404 and 405 is a drive pulse of the vertical transfer portion of the CCD. Reference numeral 404 denotes a stored charge reading gate of the odd-numbered photoelectric conversion element, and reference numeral 405 denotes a case of also serving as the stored charge reading gate of the even-numbered photoelectric conversion element. Also, 406 is the charge accumulation time of the odd-numbered photoelectric conversion elements, 407 is the charge accumulation time of the even-numbered photoelectric conversion elements, 408 is the CCD output timing, 409 is the memory write timing, 410 is the memory read and signal processing Represents timing.
[0007]
As shown in FIG. 16, after a subject is imaged by a CCD over a period of one field, the light is shielded by a light shielding means, and then the charge generated in the odd-numbered photoelectric conversion elements of the CCD and the even-numbered photoelectric conversion elements in reading generated charges in each time series, temporarily stored in a memory of the signal of the odd lines and even lines. Subsequently, addition processing both signals simultaneously read the written charge to the memory by the odd lines and even lines each one line.
[0008]
[Problems to be solved by the invention]
As described above, in the conventional example, in order to capture one still image, the odd-line signal readout period, the even-line signal readout period of the image sensor, and the odd-line and even-line signals It is necessary to have a period for performing the addition process using.
[0009]
Here, when the output signals of the odd lines and even lines from the image sensor have the number of lines (240 lines in the case of NTSC format) corresponding to the television system used for moving image shooting, in general, FIG. As described above, the signals of the odd lines and the even lines are read out in one field period (1/60 seconds in the case of NTSC), and signal processing is performed over two field periods, and a total of four field periods are required.
[0010]
Also, when the CCD has a high number of pixels for still image shooting, for example, when processing is performed at a frequency equivalent to that of moving image shooting using a pixel of 1280H × 960V, each processing has a period of four times (example) : readout period of the odd line signal is required about four fields), 16 field period is required to fit the whole process.
[0011]
That is, conventionally, the time required for obtaining a frame still image has been a relatively long.
[0012]
The present invention solves the above-described problems, and an object of the present invention is to provide an imaging apparatus capable of forming a frame still image promptly by shortening the time required for still image shooting as compared with the prior art.
[0013]
[Means for Solving the Problems]
In order to solve this problem, the imaging device of the present invention is configured as follows.
[0014]
According to a first aspect of the present invention, a solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix, and charge generated in each of the photoelectric conversion elements of the odd-numbered line and the even-numbered line of the solid-state imaging element As a solid-state image sensor drive circuit that outputs each of them independently in time series, a light-shielding means that blocks exposure to the solid-state image sensor in response to still image shooting, and a first timing when the light-shielding means is in a closed state, A first storage means for storing an imaging signal of one of the odd-numbered and even-numbered lines of the solid-state imaging device; and a second timing at which the light-shielding means is in a closed state; second storage means for storing an image signal, the at the second timing, the first image signal to obtain an output signal of the imaging signal stored in the first storage means and the solid-state imaging device at the same time Generates the at third timing subsequent to the second timing, the first to obtain the first image pickup signal stored in the the stored image signal a second storage means in storage means at the same time 2 Video signal generating means for generating the video signal.
[0015]
This makes it possible to obtain a blur-free frame still image having a reduced still image creation required time in the still image capturing apparatus having an image pickup device of the interlace drive method for an interlaced signal format.
[0016]
According to a third aspect of the invention, claim 1 or in addition to the configuration of the imaging apparatus according to claim 2, wherein said video signal generating means stored together generated first image signal and the second video signal Video signal storage means is provided.
[0017]
As a result, in a still image pickup apparatus having an interlaced drive type image pickup device, it is possible to obtain a blur-free frame still image in a progressive signal format in which the time required for creating a still image is shortened.
[0018]
According to a sixth aspect of the present invention, there is provided a solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix, and charges generated by the photoelectric conversion elements in the odd-numbered lines and even-numbered lines of the solid-state imaging elements. As a solid-state image sensor drive circuit that outputs each of them independently in time series, a light-shielding means that blocks exposure to the solid-state image sensor in response to still image shooting, and a first timing when the light-shielding means is in a closed state, A first storage means for storing an imaging signal of one of the odd-numbered and even-numbered lines of the solid-state imaging device; and a second timing at which the light-shielding means is in a closed state; second storage means for storing the image signal, in the second timing, shooting of one line stored in the other of the image signal line and the first storage unit of the solid-state imaging device And a interpolating means for interpolating a first means Ruru to generate a video signal to obtain a signal at the same time, the second time the two imaging signals over each 2-line period.
[0019]
As a result, in a still image pickup apparatus having an interlaced drive type image pickup device, it is possible to obtain a still frame-free still image in a progressive signal format that reduces the required memory capacity and shortens the time required to create a still image. it can.
[0020]
The invention of claim 8, wherein, in addition to the configuration of the imaging apparatus according to claim 6 or claim 7, wherein in the second timing, an image signal storage means for storing a video signal generated from said interpolation means output signal Provided.
[0021]
As a result, in a still image pickup apparatus having an interlace drive type image pickup device, it is possible to obtain a still frame-free still image in an interlaced signal format that reduces the required memory capacity and shortens the time required for creating a still image. Can do.
[0022]
The invention of claim 9, wherein, in the imaging apparatus according to claim 8, wherein the video signal storage means is to be shared by the first storage unit and a memory.
[0023]
As a result, in a still image pickup apparatus having an interlaced drive type image pickup device, the required memory capacity is reduced to the number of pixels of the image pickup device, and a still-frame-free still image that shortens the time required to create a still image is obtained. It can be obtained in interlaced signal format.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram of an imaging apparatus according to Embodiment 1 of the present invention.
[0025]
Imaging apparatus of the first embodiment, a lens 101, a diaphragm 102, an image sensor 103, image sensor driving circuit 104, the image pickup device drive control circuit 105, an analog processing circuit 106, an analog-digital converter (hereinafter A / D) 107 The selector 110 for selecting and outputting the output of the odd line memory 108, the even line memory 109, and the A / D 107 and the output of the even line memory 109, and the vertical addition circuit 111 for adding the output of the odd line memory 108 and the output of the selector 110 And a camera part signal processing circuit 112.
[0026]
Figure 2 (a), (b) are explanatory views of the operation of the readout moving image shooting of CCD103 used in the first embodiment.
[0027]
In FIG. 2A, a CCD 103 is a general IT type, 201 is a horizontal transfer unit (HCCD), 202 is a charge detection unit, 203 is a photoelectric conversion unit, and 204 is a vertical transfer unit (VCCD). is there.
[0028]
On this CCD 103, although the color filters of the color difference line sequential system and individually corresponding to each photoelectric conversion element is formed, here, for convenience of explanation, it is not shown.
[0029]
In the interlaced readout driving shown in FIG. 2A, the electric charge accumulated in the photoelectric conversion elements corresponding to all the pixels in one field period (about 1/60 second in the case of NTSC system) in the television signal. to read the signal, mixing the charge signals of two upper and lower adjacent pixels in the vertical direction in the vertical transfer unit 204, and switches the pair of mixing for each field. For example, in the first field, V11 = P11 + P12, V12 = P13 + P14,..., And in the second field, V11 = P12 + P13, P12 = P14 + P15,.
[0030]
Also shows the relationship between the spatial position of the output signal from CCD103 by switching the mixing pair for each field in FIG. 2 (b).
[0031]
As shown in FIG. 2 (b), in the case of the NTSC system, the number of lines in both the first and second fields is 240 lines, and the line interval is Vf. In the first field and the second field, Vf / The line phase is different by 2 minutes.
[0032]
Figure 3 (a), (b) are explanatory views of the operation of the reading time of still image shooting CCD103 used in the first embodiment.
[0033]
In Figure 3, on CCD103, a color filter of a color difference line sequential system is disposed. In FIG, Ye is yellow, Mg magenta, Cy cyan, G represents the color filters of green.
[0034]
Further, in FIG. 3, it is denoted by the same reference numerals to the same portions as the structure shown in FIG. In the case of still image shooting, the difference from the case of moving image shooting is that the output signal of the charge detection unit 202 passes through the analog processing circuit 106 and A / D 107 shown in FIG. It is configured to be connected to 109.
[0035]
In thus constructed imaging apparatus, it will be described here, especially the operation during still image shooting.
[0036]
Subject image passing through the lens 101 and the aperture 102 is photoelectrically converted by the CCD 103. In this case, one field period immediately before being blocked by the diaphragm 102 becomes the period for still image shooting. Then, by being shielded by the diaphragm 102, in the CCD 103, first, as shown in FIG. 3A, the charges of the odd-numbered line photoelectric conversion unit 203 move to the vertical transfer unit 204, transfer to the horizontal transfer unit 201, are output via the charge detecting unit 202, it is recorded in the odd line memory 108.
[0037]
Next, as shown in FIG. 3 (b), charges in the photoelectric conversion unit 203 of the even-numbered lines are moved to the vertical transfer unit 204 transfers the internal vertical transfer unit 204, the horizontal transfer unit 201, a charge detection unit 202 After that, it is output and recorded in the even line memory 109.
[0038]
Thus, it is possible to obtain the odd lines and even lines pixel signals of the exposure to the same timing is not performed in the vertical direction addition processing therein from CCD103 interlace driving method for moving image shooting. This is similar to the all-pixel readout imaging element other words, is equivalent to obtain the signal of all pixels independent exposure to the same timing.
[0039]
Such CCD103 imaging signal recorded in the odd line memory and the even line memory in the vertical adder circuit 111, is outputted through the camera unit signal processing circuit 112. This operation timing will be described with reference to FIGS.
[0040]
FIG. 4 is an operation timing chart of still image creation, FIG. 5 is an explanatory diagram of signal paths, FIG. 5 (a) shows an odd line process, and FIG. 5 (b) shows an even line process.
[0041]
4, reference numeral 401 denotes VD signal is a reference signal in the vertical direction, 402 the still image shooting pulse, 403 shading operation, 404 and 405 is a driving pulse VCCD of the solid-state imaging device. Reference numeral 404 denotes an odd-numbered photoelectric conversion element accumulated charge reading gate, and reference numeral 405 denotes an even-numbered photoelectric conversion element accumulated charge reading gate.
[0042]
406 is an odd-line photoelectric conversion element storage charge storage time, 407 is an even-line photoelectric conversion element storage charge storage time, 408 is an output timing of the CCD solid-state imaging device, 409 is a memory write timing, 410 is a read and signal from the memory This represents the processing timing.
[0043]
4 will be described below using FIG. 5 with a focus on differences from the conventional example.
[0044]
As shown in FIG. 4, first, assuming that the still image capturing pulse 402 is pressed during the f2 period, the diaphragm 102 is closed during the f3 period, the exposure state is changed to the light shielding state, and still image creation is started from the f4 period.
[0045]
That is, first, the odd lines of the signal of CCD103 to f4 period (A4) is recorded sequentially read to the odd line memory 108.
[0046]
Next, in the period f5, the odd line signal (A4) stored in the odd line memory 108 is read, and the selector 110 receives the field switching pulse and outputs the output of the A / D 107 in response thereto. Select a signal.
[0047]
Thus, at the same time the even lines of the signal (B4) are recorded is read out sequentially to the even line memory 109 from CCD 103, is input to the vertical adder circuit 111 via the selector 110.
[0048]
Thus, as shown in FIG. 5A, the vertical addition circuit 111 adds the odd line signal (A4) from the odd line memory 108 and the even line signal (B4) output from the CCD 103 in the vertical direction. Is done. Then, the luminance signal (Y) and color signal in the camera unit signal processing circuit 112 by using the sum signal (C) is generated.
[0049]
Next, in the period f6, the odd line signal (A4) stored in the odd line memory 108 is read, and the selector 110 receives the field switching pulse, and from the even line memory 109 in response thereto, The output signal (B4) to be read is selected.
[0050]
As a result, as shown in FIG. 5B, in the vertical adder 111, the odd line signal (A4) from the odd line memory 108 and the even line signal (B4) from the even line memory 109 in the vertical direction. Addition is performed. Then, the luminance signal (Y) and color signal in the camera unit signal processing circuit 112 by using the sum signal (C) is generated.
[0051]
In this case, as shown in FIG. 5 (a) (b), the odd line processing at a time of the even line processing, changing the combination of pixels in the vertical addition. That is, in order to obtain a signal equivalent to that in the case of interlace driving at the time of moving image shooting, the charge signals of the upper and lower lines adjacent to each other in the vertical direction are mixed in the vertical adder circuit 111. Switch to. For example, in the odd line processing, the signals of both the upper and lower odd and even lines are added such as (2n + 1) + (2n + 2), (2n + 3) + (2n + 4), (2n + 5) + (2n + 6). In the case of even line processing, signals on both the upper and lower odd and even lines are added such as (2n + 2) + (2n + 3), (2n + 4) + (2n + 5), (2n + 6) + (2n + 7),.
[0052]
Thus, in the case of the NTSC system, the total number of lines is 240 lines and the line interval is Vf in the odd line processing and the even line processing. In the odd line processing and the even line processing, The line phase is different by Vf / 2.
[0053]
Thus, since the same signal as in the case of interlace driving is obtained, the camera unit signal processing circuit 112, the signal processing for the same field image as in the ordinary dynamic picture can be performed. That is, the luminance signal (Y) and color signal (C), since the interlaced signal format and is then input to the recording medium or the like through the interlace signal processing circuit outside FIG. As the interlaced signal processing circuit, the moving image signal processing circuit, for example, there is a DV format recording signal processing circuit, a tape or the like as a recording medium.
[0054]
Further, since the signal read from the CCD103 in period f5 is completed, since than the period of f6, comprising 102 stop in preparation for the next shooting is opened from the light-shielding state and exposure state.
[0055]
As described above, in the first embodiment, signals of pixels on odd lines and even lines exposed at the same timing without performing vertical addition processing in the image sensor from an interlace drive type image sensor for moving image shooting. When the vertical addition circuit 111 performs vertical addition processing, the even line signal output from the CCD 103 is stored in the even line memory 109, and the even line signal is stored in the vertical addition circuit 111. Since the vertical addition processing is performed with respect to the output signal from the odd line memory 108, it is possible to reduce the time required for creating a still image from the conventional 4-field period to the 3-field period. In addition, a still image signal in the interlace signal format can be obtained.
[0056]
(Embodiment 2)
Figure 6 is a block diagram of an imaging apparatus according to a second embodiment of the present invention, the same reference numerals are assigned to the configurations corresponding to those of the first embodiment shown in FIG.
[0057]
6 differs from FIG. 1 in that a YC memory 113 is provided.
[0058]
Other structure is the same as that in the first embodiment, a detailed description thereof will be omitted.
[0059]
A still image capturing operation in the thus constructed image pickup apparatus will now be described with reference to the explanatory diagram of the preceding Figure 4, and the signal path shown in FIGS.
[0060]
As in the first embodiment, if the still image capturing pulse 402 is pressed during the f2 period, the diaphragm 102 is closed during the f3 period, the exposure state is changed to the light-shielding state, and still image creation is started from the f4 period.
[0061]
Then, first, the odd lines of the signal of CCD103 to f4 period (A4) is recorded in the odd line memory 108 is read out.
[0062]
Then, the field switch the input signal with even lines of a signal CCD103 to f5 period (B4) are recorded in the even line memory 109 is read out, the selector 110 is A / D107 output signal, i.e. the even line memory 109 Select by pulse.
[0063]
Thus, as shown in FIG. 7, the vertical addition circuit 111 in the vertical direction of the addition of the even lines of the signal from the signal of the odd lines and CCD103 from the odd line memory 108 is performed, the camera unit by using the sum signal luminance signal in the signal processing circuit 112 (Y) and color signal (C) is generated and recorded in the odd line region of the YC memory 113.
[0064]
Then, the selector 110 selects the field switching pulse output signal of the even line memory 109 to f6 period, as shown in FIG. 8, the odd lines of the signals from the odd line memory 108 in the vertical adder circuit 111 and the even line memory the vertical addition of the even lines of the signal is performed from the 109, the luminance signal (Y) and color signal by the camera unit signal processing circuit 112 by using the sum signal (C) is generated, even YC memory 113 Recorded in the line area.
[0065]
Here, in the even-line processing shown in the odd line processing and 8 shown in FIG. 7, as in the first embodiment, changing the combination of pixels in the vertical addition. Thus, in the case of the NTSC system, the total number of lines is 240 lines and the line interval is Vf in the odd line processing and the even line processing. In the odd line processing and the even line processing, The line phase is different by Vf / 2.
[0066]
Thus, since the same signal as in the case of interlace driving is obtained, the camera unit signal processing circuit 112, thereby performing signal processing for the same field image as normal video.
[0067]
Luminance signal of the interlaced signal format (Y) and is then stored respectively into an odd line region and the even line region of the chrominance signal (C) a YC memory 113, these luminance signal (Y) and color signal (C) by reading alternately from an odd line region and the even line region, it is possible to output a signal of the progressive signal format from the YC memory 113.
[0068]
As described above, in the second embodiment, it is possible as in the case of the first embodiment, to shorten the time required for the still images create from four field periods to 3 field period, moreover, then by storing the luminance signal (Y) and color signal (C) in the YC memory 113, it becomes possible to obtain a still image signal of the progressive signal format (non-interlaced signal format). Therefore, it is possible to input to a recording medium or the like thereafter through a progressive signal processing circuit. The progressive signal processing circuit includes a still image signal processing circuit such as JPEG signal processing, and the recording medium includes a memory card.
[0069]
(Embodiment 3)
Figure 9 is a block diagram of an imaging apparatus according to a third embodiment of the present invention, the same reference numerals are assigned to the configurations corresponding to those of the first embodiment shown in FIG.
[0070]
9 differs from FIG. 1 in that a 1H memory 114 is provided in place of the even line memory 109.
[0071]
Other structure is the same as that in the first embodiment, a detailed description thereof will be omitted.
[0072]
The operation of the imaging apparatus configured as described above during still image shooting will be described below with reference to FIGS.
[0073]
FIG. 10 is an operation timing diagram for creating a still image, FIG. 11 is an explanatory diagram of a signal path, and FIG. 12 is an explanatory diagram of an operation of the image sensor.
[0074]
10, wrote the same reference numerals in FIG. 4 the same parts of the first embodiment.
[0075]
As shown in FIG. 10, when the still image recording pulse 402 is pressed f2 period, the diaphragm 102 is closed to f3 period becomes a light shielding state from exposure state, a still image creation is started from f4 period.
[0076]
That is, first, the odd lines of the signal of CCD103 to f4 period (A4) is recorded sequentially read to the odd line memory 108.
[0077]
Next, the signal (B4) of the even line of the CCD 103 is sequentially read over two field periods from the f5 period to the f6 period. The even line signal (B4) is recorded in the 1H memory 114 for each line. The selector 110 each time the line switch pulse is input, alternately selects one of an output signal from the output signal and the 1H memory 114 of A / D107 accordingly. In parallel to this operation, the read address control for an odd line memory 108, the odd lines of the signal stored in the odd line memory 108 (A4) is read.
[0078]
As a result, the vertical adder circuit 111 performs vertical addition of the adjacent lines in the vertical direction as shown in FIG.
[0079]
First, in the first line, the vertical addition of the (2n + 2) line of the signal from the odd from the line memory 108 (2n + 1) line of the signal and CCD103 performed.
[0080]
In the second line, the vertical addition of the (2n + 2) line of the signal from the odd from the line memory 108 (2n + 3) line of the signal and the 1H memory 114 is performed.
[0081]
In the third line, the vertical addition of the (2n + 4) line of the signal from the odd lines (2n + 3) line of the signal and CCD103 from the odd line memory 108 is performed.
[0082]
In the fourth line, the vertical addition of the (2n + 4) line of the signal from the odd from the line memory 108 (2n + 5) line of the signal and the 1H memory 114 is performed.
[0083]
This, when viewed as a signal input to the vertical addition circuit 111, from the odd line memory 108, initially (2n + 1) the signal line is outputted, the subsequent, (2n + 3), (2n + 3), ( 2n + 5), (2n + 5),... Odd line signals are applied over a period of two lines. Further, from the selector 110, even line signals are given over two line periods, such as (2n + 2), (2n + 2), (2n + 4), (2n + 4), (2n + 6), (2n + 6),.
[0084]
Then, the addition signal obtained by the vertical addition circuit 111 is input to the camera unit signal processing circuit 112, the luminance signal (Y) and color signals in the camera unit signal processing circuit 112 (C) is generated.
[0085]
The charge signal reading operation from the CCD 103 when performing the above vertical addition processing will be described in more detail with reference to FIG.
[0086]
In FIG. 12, 901 is an HD signal which is a horizontal reference signal, 902 is a line switching pulse, and 903 is a VCCD driving pulse. Note that 903 represents the transfer pulse in the vertical direction. Reference numeral 904 denotes a driving pulse of the HCCD, and 905 denotes an output timing of the charge signal from the CCD 103 on the even line.
[0087]
As shown in FIG. 12, in the state of the line switching pulse 902 is "H", a drive pulse 903 is not generated for VCCD204, therefore, the vertical transfer is stopped. Therefore, even line signals output from the CCD 103 are output at intervals of two lines, as indicated by the CCD output timing 905.
[0088]
Thus, in f5 and f6 period, from CCD 103, since the signals of the even lines are outputted by the 2 line spacing, by a line switching pulse and the output signal of the selector 110 A / D107 output signal and 1H memories 114 it is to switch, the selector 110 can be output continuously for two line periods the same signal of the even lines of the CCD 103.
[0089]
As described above, the odd line memory 108 outputs an odd line signal over a period of two lines by read address control.
[0090]
Thus, in the first line, (2n + 1) area imaging signal (Ye, Cy) and (2n + 2) area imaging signal (Mg, G) and is added to the vertical direction in the vertical addition circuit 111 adds signals ( Ye + Mg, Cy + G), and this added signal is then output through the camera part signal processing circuit 112.
[0091]
Subsequently, in the second line, (2n + 2) area imaging signal (Mg, G) and (2n + 3) area imaging signal (Ye, Cy) and is added to the vertical direction in the vertical addition circuit 111 adds signals ( Ye + Mg, Cy + G), and this added signal is then output through the camera part signal processing circuit 112.
[0092]
Hereinafter, similarly, by changing the combination of pixels in the vertical addition for each line, resulting in the formation of the signal of the odd line signal and an even line when interlaced alternately driven, the camera unit signal processing circuit 112 in will make a signal processing for the frame image of one frame consists of 480 lines.
[0093]
Thus, the luminance signal (Y) and color signal (C) is a progressive signal format (non-interlaced signal format), then, is input to the recording medium or the like through the progressive signal processing circuit outside FIG. As the progressive signal processing circuit, a still picture signal processing circuit, for example, there is a JPEG signal processing circuit, a memory card or the like as a recording medium.
[0094]
As described above, in the embodiment 3, it is possible to shorten time required for the still images create from four field periods to 3 field period, moreover, to obtain a still image signal of the progressive signal format it can. Furthermore, it is possible to reduce the memory capacity of the image memory 114 as compared with the first and second embodiments.
[0095]
(Embodiment 4)
Figure 13 is a block diagram of an imaging apparatus according to the fourth embodiment of the present invention, the same reference numerals are assigned to the configurations corresponding to those of the third embodiment shown in FIG.
[0096]
The fourth embodiment is different from the configuration of the third embodiment shown in FIG. 9 in that a YC memory 113 is provided.
[0097]
Since other configurations are the same as those in the third embodiment, detailed description thereof is omitted here.
[0098]
The operation at the time of still image shooting in the thus constructed image pickup apparatus will now be described with reference to the explanatory diagram of a signal path shown in FIG. 14. Note that the operation timing of the still image creation is the same as the contents shown in FIGS. 10 and 11 of the third embodiment, since the operation of CCD103 the same as in FIG. 12 of the third embodiment, detailed description Is omitted.
[0099]
Also in the fourth embodiment, as in the case of the third embodiment, in the first line, the (2n + 1) area imaging signal (Ye, Cy) and (2n + 2) area imaging signal (Mg, G) is added to the vertical direction in the vertical addition circuit 111, the sum signal (Ye + Mg, Cy + G) is recorded in the (2n + 1) region of the YC memory 113 through the camera unit signal processing circuit 112.
[0100]
Subsequently, in the second line, (2n + 2) area imaging signal (Mg, G) and (2n + 3) area imaging signal (Ye, Cy) and is added to the vertical direction by the vertical addition circuit 111 adds the signal ( Ye + Mg, Cy + G) is recorded in the (2n + 2) area of the YC memory 113 via the camera unit signal processing circuit 112.
[0101]
Hereinafter, similarly, resulting in the formation of the signal of the odd and even lines of the signal in the interlace driving alternately by varying the combination of pixels in the vertical addition for each line, in the camera unit signal processing circuit 112 , it will perform signal processing for the frame image of one frame consists of 480 lines.
[0102]
Thus, the luminance signal (Y) and color signal (C) is a progressive signal format (non-interlaced signal format), then, YC luminance signal (Y) and color signals of the progressive signal format (C) By storing in the memory 113, the YC memory 113 can be in an interlace signal format. Therefore, it is possible to input to a recording medium or the like through an interlace signal processing circuit (not shown). As the interlaced signal processing circuit, the moving image signal processing circuit, for example, there is a DV format recording signal processing, tapes and the like as the recording medium.
[0103]
As described above, in the fourth embodiment, it is possible to shorten time required for the still images create from four field periods to 3 field period, moreover, the image memory as compared with embodiments 1 and 2 It is possible to reduce the memory capacity of 114. Further, by storing the luminance signal (Y) and the color signal (C) in the YC memory 113, it is possible to obtain a still image in the interlace signal format.
[0104]
(Embodiment 5)
FIG. 15 is a block diagram of an imaging apparatus according to Embodiment 5 of the present invention, and portions corresponding to those in the configuration of Embodiment 4 shown in FIG.
[0105]
The fifth embodiment differs from the fourth embodiment shown in FIG. 13 in that the selector 115 is provided between the A / D 107 and the odd line memory 108 and the output of the YC memory 113 is odd. The selector 116 for selecting the output of the line memory 108 is provided, and the memory capacity of the YC memory 113 is set to half that in the fourth embodiment (here, the memory capacity for 240 lines).
[0106]
Since the other configuration is the same as that of the fourth embodiment, detailed description thereof is omitted here.
[0107]
The operation at the time of still image shooting in the imaging apparatus configured as described above will be described below with reference to the signal path explanatory diagram shown in FIG. The operation timing for creating a still image is the same as that shown in FIGS. 10 and 11 of the third embodiment, and the reading operation of the CCD 103 is the same as that shown in FIG. 12 of the third embodiment. Because there is, detailed explanation is omitted.
[0108]
Since the selector 115 switches the connection so that the output of the A / D 107 is given to the odd line memory 108 in the period f4 shown in FIG. 10, the signal (A4) of the odd line of the CCD 103 is sequentially read and odd. Recorded in the line memory 108. After that, the selector 115 switches the connection so that the output of the camera unit signal processing circuit 112 is given to the odd line memory 108 until the still image signal processing for one frame is completed.
[0109]
As in the case of the third embodiment, in both periods f5 and f6 shown in FIG. 10, the output from the CCD 103 is two line intervals, the output signal of the A / D 107, the output signal of the 1H memory 114, and the selector 110. By switching at, the signal of the even line of the CCD 103 is output over a period of two lines.
[0110]
The odd line memory 108 outputs an odd line signal over two line periods by controlling a read address.
[0111]
As a result, first, in the first line, the (2n + 1) -line signal (Ye, Cy) from the odd-number line memory 108 and the (2n + 2) -line signal (Mg, G) from the CCD 103 are output in the vertical adder circuit 111. The signals are added in the vertical direction to become an addition signal (Ye + Mg, Cy + G). This addition signal is generated as a luminance signal (Y) and a color signal (C) by the camera unit signal processing circuit 112, and these signals are stored in the YC memory 113. Without being fed back to the selector 115 and recorded in the (2n + 1) area of the odd line memory 108.
[0112]
Next, in the second line, the (2n + 2) line signal (Mg, G) from the 1H memory 114 and the (2n + 3) line signal (Ye, Cy) from the odd line memory 108 are converted by the vertical adder circuit 111. Addition signals (Ye + Mg, Cy + G) are added in the vertical direction, and this addition signal is generated as a luminance signal (Y) and a color signal (C) by the camera unit signal processing circuit 112, and these signals are stored in the YC memory 113 ( 2n + 2) recorded in the area.
[0113]
In the third line, the (2n + 3) line signal (Ye, Cy) from the odd line memory 108 and the (2n + 4) line signal (G, Mg) from the CCD 103 are added in the vertical direction by the vertical adder circuit 111. The added signal (Ye + G, Cy + Mg) is generated as a luminance signal (Y) and a color signal (C) by the camera unit signal processing circuit 112. These signals are not stored in the YC memory 113 but are selected. The data is fed back to 115 and recorded in the (2n + 3) area of the odd line memory 108.
[0114]
Next, in the fourth line, the signal (G, Mg) on the (2n + 4) line from the 1H memory 114 and the signal (Ye, Cy) on the (2n + 5) line from the odd line memory 108 are output in the vertical adder circuit 111. Addition signals (Ye + G, Cy + Mg) are added in the vertical direction, and this addition signal is generated as a luminance signal (Y) and a color signal (C) by the camera unit signal processing circuit 112, and these signals are stored in the YC memory 113 ( 2n + 4) recorded in the area.
[0115]
Similarly, by changing the combination of pixels for vertical addition for each line, after the period of f5 and f6 in FIG. 10 elapses, the odd line memory 108 stores one field of odd lines ( The luminance signal (Y) and the color signal (C) for 240 lines are stored here, and the YC memory 113 stores the luminance signal (Y) and the luminance signal (Y) for one field (here 240 lines) of even lines. A color signal (C) is stored. Therefore, the YC memory 113 only needs to have a memory capacity equivalent to that of the odd line memory 108.
[0116]
Thereafter, by switching the selector 116 for each field, for example, the luminance signal (Y) and the color signal (C) for one field of the odd line are read from the odd line memory 108, and then the even line is read from the YC memory 113. If the luminance signal (Y) and color signal (C) for one field are read out, the interlace signal format can be obtained.
[0117]
Therefore, it is possible to input to a recording medium or the like through an interlace signal processing circuit (not shown). As the interlaced signal processing circuit, the moving image signal processing circuit, for example, there is a DV format recording signal processing circuit, a tape or the like as a recording medium.
[0118]
As described above, in the fifth embodiment, it is possible to reduce the time required for creating a still image from the conventional four-field period to the three-field period, and in addition to the case of the fourth embodiment, the image memory 113 is further reduced. It is possible to reduce the memory capacity. Furthermore, by storing the luminance signal (Y) and the color signal (C) in the odd line memory 108 and the YC memory 113, it is possible to obtain a still image in the interlace signal format.
[0119]
In the first to fifth embodiments described above, Ye, Mg, Cy, and G are shown as field color difference line sequential color filters of the CCD 103, but the present invention is not limited to this.
[0120]
In the above-described first to fifth embodiments, the operation timing at the time of creating a still image has been described with respect to the case where an odd line signal of the CCD 103 is read in one field period. However, the present invention is not limited to this. In the case of a high number of pixels, for example, when processing is performed at a frequency similar to that of moving image shooting using the CCD 103 having a number of pixels of 1280H × 960 V, each processing is four times as long (eg, an odd line signal readout period) About 4 fields), and in that case, the time required for taking a still image is shortened by four times as well.
[0121]
【The invention's effect】
As described above, in the imaging apparatus of the present invention, when an interlace-driven imaging element for moving image shooting is provided, the time required for creating a still image without blurring still image shooting is reduced. It is possible to realize.
[0122]
Furthermore, it is possible to reduce the memory capacity required for still image shooting while maintaining this effect.
[Brief description of the drawings]
FIG. 1 is a block diagram of an imaging apparatus according to Embodiment 1 of the present invention.
FIG. 2 is an explanatory diagram of a reading operation during moving image shooting of the image sensor according to the first embodiment.
FIG. 3 is an explanatory diagram of a reading operation at the time of still image shooting of the image sensor according to the first embodiment.
FIG. 4 is an operation timing chart when creating a still image in the first embodiment.
FIG. 5 is an explanatory diagram of a signal path when creating a still image according to the first embodiment.
FIG. 6 is a block diagram of an imaging apparatus according to Embodiment 2 of the present invention.
7 is an explanatory diagram of a signal path during odd line processing in Embodiment 2. FIG.
FIG. 8 is an explanatory diagram of a signal path during even line processing in the second embodiment;
FIG. 9 is a block diagram of an imaging apparatus according to Embodiment 3 of the present invention.
FIG. 10 is an operation timing chart when creating a still image according to the third embodiment.
FIG. 11 is an explanatory diagram of a signal path when creating a still image according to the third embodiment.
12 is an explanatory diagram of an even line read operation of the image sensor in Embodiment 3. FIG.
FIG. 13 is a block diagram of an imaging apparatus according to Embodiment 4 of the present invention.
FIG. 14 is an explanatory diagram of a signal path when creating a still image according to the fourth embodiment.
FIG. 15 is a block diagram of an imaging apparatus according to Embodiment 5 of the present invention.
FIG. 16 is an explanatory diagram of a signal path when creating a still image according to the fifth embodiment.
FIG. 17 is an operation timing chart when creating a still image in a conventional example.
[Explanation of symbols]
101 lens
102 Aperture
103 Image sensor
104 Image sensor driving circuit
105 Image sensor drive control circuit
106 Analog signal processor
107 A / D
108 odd line memory
109 Even line memory
110 Selector
112 Camera section signal processing circuit
113 YC memory
114 1H memory
115 selector
116 Selector

Claims (14)

A solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix; and
A solid-state image sensor driving circuit that outputs the charges generated in the photoelectric conversion elements of the odd-numbered lines and even-numbered lines of the solid-state image sensor independently in time series as imaging signals;
Light shielding means for blocking exposure to the solid-state imaging device in response to still image shooting;
First storage means for storing imaging signals of either odd or even lines of the solid-state imaging device at a first timing when the light shielding means is in a closed state;
Second storage means for storing an imaging signal of the other line of the solid-state imaging device at a second timing when the light shielding means is in a closed state;
At the second timing, the imaging signal stored in the first storage means and the output signal of the solid-state imaging device are simultaneously obtained to generate the first video signal, and the second timing following the second timing. Video signal generating means for simultaneously obtaining the imaging signal stored in the first storage means and the imaging signal stored in the second storage means to generate a second video signal at a timing of 3,
An imaging apparatus comprising: The first is generated by the video signal generating means, the second image signal, the imaging apparatus according to claim 1, characterized in that it is connected to the interlaced signal processing circuit. In addition to the configuration of the imaging device according to claim 1 or 2, video signal storage means for storing both the first video signal and the second video signal generated by the video signal generation means is provided. An imaging apparatus characterized by that. 4. The imaging apparatus according to claim 3, wherein the video signal storage means for storing both the first video signal and the second video signal is different from the first and second storage means. The imaging apparatus according to claim 3 or 4, wherein the first video signal and the second video signal read from the video signal storage unit are connected to a progressive signal processing circuit. A solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix; and
A solid-state image sensor driving circuit that outputs the charges generated in the photoelectric conversion elements of the odd-numbered lines and even-numbered lines of the solid-state image sensor independently in time series as imaging signals;
Light shielding means for blocking exposure to the solid-state imaging device in response to still image shooting;
First storage means for storing imaging signals of either odd or even lines of the solid-state imaging device at a first timing when the light shielding means is in a closed state;
Second storage means for storing an imaging signal of the other line of the solid-state imaging device at a second timing when the light shielding means is in a closed state;
At the second timing, an imaging signal of the other line of the solid-state imaging device and an imaging signal of one line stored in the first storage unit are simultaneously obtained to generate a first video signal. Means,
Interpolating means for interpolating the two imaging signals at the second timing over two line periods respectively;
An imaging apparatus comprising: In the second timing, the video signals generated from the two image pickup signals obtained at the same time, the imaging apparatus according to claim 6, characterized in that it is connected to a progressive signal processing circuit. In addition to the configuration of the image pickup apparatus according to claim 6 or 7, image signal storage means for storing a video signal generated from the output signal of the interpolation means at the second timing is provided. apparatus. The imaging device according to claim 8.
The imaging apparatus according to claim 1, wherein the video signal storage means shares a memory with the first storage means. The video signal stored in the video signal storage means, the image pickup apparatus according to claim 8 or claim 9, characterized in that it is connected to the interlaced signal processing circuit. The output signal from the solid-state imaging device in the second timing, the image pickup apparatus according to any one of claims 6, 8 and 9, characterized in that the intermittent signal. The interpolation means for the output signal of the solid-state imaging device has a memory having a capacity of approximately one line, and the interpolation means for the output signal of the first storage means has a memory control means for reading out signals in the same region. Item 10. The imaging device according to any one of Items 6, 8, and 9. The means for generating a video signal includes addition processing of signals of even lines and odd lines adjacent to each other on the solid-state imaging device. The imaging device described. Shielding means, the imaging device according to any one of claims 1,3,6,8,9, characterized in that a diaphragm capable of light quantity adjustment.

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