JP2001086514A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device that reduces time required for photographing a still picture so as to quickly generate a frame still picture. SOLUTION: The image pickup device is provided with a solid-state image pickup device 103 that has a plurality of photoelectric conversion elements arranged in a form of a matrix and an aperture 102 that has a light quantity adjustment means and a light shielding means, a solid-state image pickup device drive circuit 104 that reads electric charges generated from the photoelectric conversion elements of an odd number line of the solid-state image pickup device 103 and electric charges generated from the photoelectric conversion elements of an even number line of the solid-state image pickup device 103 in time series after the aperture 102 shields light, image memories 108, 109 that record image pickup signals of an odd number line and image pickup signals of an even number line respectively, and a signal processing means 112 that uses the image pickup signals of the odd number line and the even number line recorded in both the image memories 108, 109 and the image pickup signals of the even number line bypassing both the image memories 108, 109 to conduct an arithmetic processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image pickup apparatus for mainly photographing a still image.

[0002]

2. Description of the Related Art Conventionally, a high-quality still image pickup device using a moving image signal processing method is disclosed in Japanese Patent Application Laid-Open No. 7-29814.
No. 0 (hereinafter referred to as a conventional example) is known.

[0003] Hereinafter, this conventional imaging apparatus will be described.

[0004] This conventional imaging apparatus is a solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix (hereinafter, referred to as a solid-state imaging device).
CCD) and a stop having a light amount adjusting means and a light shielding means. The CCD has a color filter of a field color difference line sequential system.

The operation timing of the conventional imaging apparatus will be described more specifically with reference to FIG.

In FIG. 16, reference numeral 401 denotes a VD signal as a reference signal in the vertical direction;
03 is a light-shielding operation, and 404 and 405 are drive pulses for the vertical transfer section of the CCD. Note that reference numeral 404 denotes a case also serving as a storage charge reading gate of an odd-numbered photoelectric conversion element, and reference numeral 405 denotes a case also serving as a storage charge reading gate of an even-numbered photoelectric conversion element. 406 is the charge accumulation time of the odd-numbered line photoelectric conversion elements, 407 is the charge accumulation time of the even-numbered line photoelectric conversion elements, 408 is the CCD output timing, 409 is the memory write timing, 410
Represents the timing of reading from the memory and signal processing.

As shown in FIG. 16, after capturing an image of a subject with a CCD for a period of one field, the CCD is shielded from light by a light shielding means. The charges generated by the photoelectric conversion elements are read out in time series, and the signals of the odd-numbered lines and the even-numbered lines are temporarily stored in a memory. Subsequently, the electric charges written in the memory are read out simultaneously for each of the odd-numbered lines and the even-numbered lines, and both signals are added.

[0008]

As described above, in the conventional example, in order to capture a single still image, the readout period of the signal of the odd-numbered line and the readout period of the signal of the even-numbered line of the image sensor are required. A period for performing an addition process or the like using the signals of the odd lines and the even lines is required.

Here, the output signals of the odd-numbered lines and the even-numbered lines from the image sensor are determined by the number of lines (24 in the case of the NTSC format) corresponding to the television system used for moving image shooting.
0), generally, as shown in FIG.
In the field period (1/60 second in the case of NTSC), the signals of the odd lines and the even lines are read out, and the signal processing is performed over two field periods, which requires a total of four field periods.

When the CCD has a large number of pixels for photographing still images, for example, when a pixel of 1280H × 960 V is used to perform processing at a frequency similar to that of moving image photographing, each processing is quadrupled. A period (for example, the reading period of the odd line signal is about 4 fields) is required, and a total of 16 field periods are required for the entire processing.

That is, conventionally, the time required to obtain a frame still image has been relatively long.

An object of the present invention is to solve the above-mentioned problem, and to provide an image pickup apparatus capable of forming a frame still image quickly by shortening the time required for photographing a still image as compared with the related art. And

[0013]

The image pickup apparatus according to the present invention has the following configuration to solve this problem.

According to a first aspect of the present invention, there is provided a solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix, and a charge generated in each of the odd-numbered and even-numbered photoelectric conversion elements of the solid-state imaging element. A solid-state imaging device driving circuit that independently outputs time-sequentially as imaging signals, a light-shielding unit that shuts off exposure to the solid-state imaging device in response to still image shooting, and a first light-shielding unit in which the light-shielding unit is in a closed state. A first storage unit that stores, at a timing, an imaging signal of one of an odd-numbered line and an even-numbered line of the solid-state imaging device; and a second timing that the light-shielding unit is in a closed state. A second storage unit for storing the image signal of the line, and simultaneously obtaining the image signal stored in the first storage unit and the output signal of the solid-state image sensor at the second timing. To generate a first video signal,
At a third timing subsequent to the second timing, an image signal stored in the first storage unit and an image signal stored in the second storage unit are simultaneously obtained, and a second timing is obtained.
And a video signal generating means for generating the video signal.

[0015] Thus, in a still image pickup apparatus having an image pickup device of an interlace drive system, it is possible to obtain a frame-free still image in the interlaced signal format in which the time required for producing a still image is reduced.

According to a third aspect of the present invention, in addition to the configuration of the image pickup apparatus according to the first or second aspect, the first video signal and the second video signal generated by the video signal generating means are provided. Is stored together with video signal storage means.

Thus, in the still image pickup apparatus having the interlaced drive type image pickup device, it is possible to obtain a frame-free still image in a progressive signal format in which the time required for producing a still image is reduced.

According to a sixth aspect of the present invention, there is provided a solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix, and a charge generated in each of the odd-numbered and even-numbered photoelectric conversion elements of the solid-state imaging device. A solid-state imaging device driving circuit that independently outputs time-sequentially as imaging signals, a light-shielding unit that shuts off exposure to the solid-state imaging device in response to still image shooting, and a first light-shielding unit in which the light-shielding unit is in a closed state. A first storage unit that stores, at a timing, an imaging signal of one of an odd-numbered line and an even-numbered line of the solid-state imaging device; and a second timing that the light-shielding unit is in a closed state. A second storage means for storing the image signal of the line of the solid-state image sensor, and an image signal of the other line of the solid-state image sensor and the one stored in the first storage means at the second timing. And means Ruru to generate a first video signal to obtain an imaging signal lines at the same time, and interpolating means for interpolating over each 2-line period the two imaging signal of the second timing.

Thus, in a still image pickup apparatus having an interlaced drive type image pickup device, the required memory capacity is reduced, and a still frame-free still image in which the time required for forming a still image is shortened is converted into a progressive signal format. Obtainable.

According to an eighth aspect of the present invention, in addition to the configuration of the image pickup apparatus according to the sixth or seventh aspect, a video signal for storing a video signal generated from the interpolation means output signal at the second timing. Storage means is provided.

Thus, in a still image pickup apparatus having an image pickup device of the interlace drive system, the required memory capacity is reduced, and the time required for the creation of a still image is reduced. Can be obtained at

According to a ninth aspect of the present invention, in the imaging device of the eighth aspect, the video signal storage means shares a memory with the first storage means.

Thus, in a still image pickup apparatus having an interlace drive type image pickup device, the required memory capacity is reduced to the number of pixels of the image pickup device, and the time required for still image creation is shortened. Still images can be obtained in the form of interlaced signals.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of an imaging apparatus according to Embodiment 1 of the present invention.

The imaging apparatus according to the first embodiment includes a lens 1
01, aperture 102, image sensor 103, image sensor drive circuit 104, image sensor drive control circuit 105, analog processing circuit 106, analog / digital conversion circuit (hereinafter A / D) 1
07, odd line memory 108, even line memory 10
9, a selector 110 for selecting and outputting the output of the A / D 107 and the output of the even line memory 109, a vertical adding circuit 111 for adding the output of the odd line memory 108 and the output of the selector 110, and a camera unit signal processing circuit 112. Prepare.

FIGS. 2A and 2B are diagrams for explaining the read operation of the CCD 103 used in the first embodiment when shooting a moving image.

In FIG. 2A, a CCD 103 is of a general IT type, and 201 is a horizontal transfer unit (HCC).
D), 202 is a charge detection unit, 203 is a photoelectric conversion unit, 20
Reference numeral 4 denotes a vertical transfer unit (VCCD).

On the CCD 103, a color filter of a color difference line sequential system is formed for each photoelectric conversion element individually, but is not shown here for convenience of explanation.

In the interlaced read driving shown in FIG. 2A, in one field period (about 1/60 second in the case of the NTSC system) of the television signal, the photoelectric conversion elements corresponding to all the pixels are driven. In order to read out the stored charge signals, the charge signals of two vertically adjacent pixels are mixed in the vertical transfer unit 204, and this mixed pair is switched for each field. For example, in the first field, V11 = P11 + P12, V12 = P13 +
P14,..., And in the second field, V11 = P1
2 + P13, P12 = P14 + P15,...

FIG. 2 (b) shows the relationship of the spatial position of the output signal from the CCD 103 by switching the mixed pair for each field.

As shown in FIG. 2B, in the case of the NTSC system, the number of lines is 240 lines in both the first and second fields, and the line interval is Vf. , Vf / 2.

FIGS. 3 (a) and 3 (b) are illustrations of the read operation of the CCD 103 used in the first embodiment when shooting a still image.

In FIG. 3, a color filter of a color difference line sequential system is arranged on the CCD 103. In the figure, Ye is yellow, Mg is magenta, Cy is cyan, G
Represents each green color filter.

In FIG. 3, the same parts as those shown in FIG. 2 are denoted by the same reference numerals. The difference between the case of shooting a still image and the case of shooting a moving image is that
The configuration is such that the output signal of the charge detection unit 202 is connected to the odd memory 108 or the even line memory 109 via the analog processing circuit 106 and the A / D 107 shown in FIG.

[0035] In the imaging apparatus thus configured,
Here, an operation at the time of shooting a still image will be particularly described.

The subject image that has passed through the lens 101 and the aperture 102 is photoelectrically converted by the CCD 103. In this case, one field period immediately before the light is shielded by the aperture 102 is a period for photographing a still image. And the aperture 102
As shown in FIG. 3 (a), first, the CCD 103 in the odd-numbered line
03 moves to the vertical transfer unit 204 and the vertical transfer unit 2
04, the horizontal transfer unit 201 and the charge detection unit 202
And is recorded in the odd line memory 108.

Next, as shown in FIG. 3B, the charges of the photoelectric conversion units 203 on the even-numbered lines move to the vertical transfer unit 204, and are transferred inside the vertical transfer unit 204.
1. Output through the charge detection unit 202 and recorded in the even-numbered line memory 109.

Thus, it is possible to obtain from the CCD 103 of the interlaced drive system for capturing a moving image, signals of pixels of odd-numbered lines and even-numbered lines which are exposed at the same timing and in which vertical addition processing is not performed. this is,
In other words, this is equivalent to obtaining signals of all independent pixels exposed at the same timing as in the case of the all-pixel readout imaging device.

The image pickup signals of the CCD 103 recorded in the odd line memory and the even line memory in this manner are:
The signal is output through the vertical addition circuit 111 and the camera unit signal processing circuit 112. This operation timing will be described with reference to FIGS.

FIG. 4 is an operation timing chart of still image creation.
FIGS. 5A and 5B are explanatory diagrams of signal paths. FIG. 5A shows an odd line process, and FIG. 5B shows an even line process.

In FIG. 4, reference numeral 401 denotes a VD signal which is a reference signal in the vertical direction; 402, a still image photographing pulse;
Is a light shielding operation, and 404 and 405 are VCCDs of solid-state image sensors.
Are the driving pulses. Note that reference numeral 404 denotes a case where the gate also serves as a readout gate of the photoelectric conversion element accumulated charge of the odd-numbered line, and reference numeral 405 denotes a case where the gate also serves as a readout gate of the photoelectric conversion element accumulated charge of the even-numbered line.

Reference numeral 406 denotes an odd line photoelectric conversion element accumulated charge accumulation time; 407, an even line photoelectric conversion element accumulated charge accumulation time; 408, a CCD solid-state image sensor output timing; 409, a memory write timing; It shows readout and signal processing timing.

FIG. 4 will be described below with reference to FIG. 5, focusing on differences from the conventional example.

As shown in FIG. 4, assuming that the still image photographing pulse 402 is pressed during the period f2, the aperture 102 is closed during the period f3 to change from the exposure state to the light shielding state.
Still image creation is started from four periods.

That is, first, in the period f4, the CCD 103
Are sequentially read out and recorded in the odd-numbered line memory 108.

Next, during the period f5, the signal (A4) of the odd line stored in the odd line memory 108 is read out, and the selector 110 receives the field switching pulse and responds to the A / A signal. D107
Select the output signal of

As a result, the even-line signal (B4) is sequentially read from the CCD 103 and
9 and, at the same time, is input to the vertical addition circuit 111 via the selector 110.

As a result, as shown in FIG. 5A, in the vertical addition circuit 111, the vertical line signal (A4) of the odd line from the odd line memory 108 and the vertical line signal (B4) of the even line output from the CCD 103 are read. A direction addition is performed. Then, a luminance signal (Y) and a color signal (C) are generated in the camera unit signal processing circuit 112 using the added signal.

Next, during the period f6, the signal (A4) of the odd line stored in the odd line memory 108 is read out, and the selector 110 receives the field switching pulse and, in response to the input of the field switching pulse, responds to the even line. The output signal (B4) read from the memory 109 is selected.

As a result, as shown in FIG. 5B, in the vertical addition circuit 111, the signal of the odd line (A4) from the odd line memory 108 and the signal of the even line (B4) from the even line memory 109 are output. Vertical addition is performed. Then, a luminance signal (Y) and a color signal (C) are generated in the camera unit signal processing circuit 112 using the added signal.

In this case, as shown in FIGS. 5A and 5B, the combination of pixels for vertical addition is changed between the odd line processing and the even line processing. That is, in order to obtain a signal equivalent to that in the case of interlace driving at the time of moving image shooting, the charge signals of vertically adjacent lines are added to the vertical addition circuit 1 in the vertical direction.
The mixing is performed at 11, and at this time, this mixing pair is switched for each field. For example, at the time of odd line processing, (2n + 1) + (2n + 2), (2n + 3) + (2n +
4), (2n + 5) + (2n + 6),..., And the signals of both upper and lower odd and even lines are added. Also, at the time of even line processing, (2n + 2) + (2n + 3), (2n + 4) + (2
n + 5), (2n + 6) + (2n + 7),..., and the signals of both upper and lower odd and even lines are added.

Thus, in the case of the NTSC system, the total number of lines is 240 lines and the line interval is Vf at the time of odd-line processing and even-line processing. , The line phase differs by Vf / 2.

As described above, a signal equivalent to that in the case of the interlaced drive is obtained, so that the camera unit signal processing circuit 112
Thus, signal processing can be performed on the same field image as in the case of a normal moving image. That is, since the luminance signal (Y) and the chrominance signal (C) are in the form of an interlace signal, they are thereafter input to a recording medium or the like via an interlace signal processing circuit (not shown). The interlace signal processing circuit includes a moving image signal processing circuit, for example, a DV format recording signal processing circuit, and a recording medium such as a tape.

Since the signal reading from the CCD 103 is completed in the period f5, the period after the period f6 is shorter than that in the period f6.
The aperture 102 is opened to prepare for the next photographing, and the state is changed from the light shielding state to the exposure state.

As described above, in the first embodiment, the odd-numbered lines and the even-numbered lines exposed at the same timing from the interlaced drive type image pickup device for capturing a moving image are not subjected to vertical addition processing in the image pickup device. After obtaining the pixel signals, when the vertical addition circuit 111 performs vertical addition processing, the even-line signals output from the CCD 103 are stored in the even-line memory 109, and the even-line signals are vertically Since the vertical addition process is applied to the addition circuit 111 and the output signal from the odd-numbered line memory 108, the time required to generate a still image can be reduced from the conventional four-field period to the three-field period. In addition, a still image signal in an interlaced signal format can be obtained.

(Embodiment 2) FIG. 6 is a block diagram of an image pickup apparatus according to Embodiment 2 of the present invention, and portions corresponding to those in the configuration of Embodiment 1 shown in FIG. Is attached.

FIG. 6 differs from FIG. 1 in that a YC memory 113 is provided.

The other structure is the same as that of the first embodiment, and the detailed description is omitted here.

The still image photographing operation in the image pickup apparatus thus constructed will be described below with reference to FIG. 4 and the explanatory diagrams of the signal paths shown in FIGS. 7 and 8.

As in the first embodiment, assuming that the still image photographing pulse 402 is pressed during the period f2, the aperture 102 is closed during the period f3, and the state changes from the exposure state to the light shielding state.
Still image creation has started from the period.

Then, first, the signal (A4) of the odd line of the CCD 103 is read out and recorded in the odd line memory 108 during the period f4.

Next, during the period f5, the signal (B4) of the even line of the CCD 103 is read out and recorded in the even line memory 109, and the selector 110 outputs the A / D 107 output signal, that is, the input signal to the even line memory 109. Is selected by a field switching pulse.

As a result, as shown in FIG. 7, in the vertical addition circuit 111, the signal of the odd line from the odd line memory 108 and the signal of the even line from the CCD 103 are added in the vertical direction, and this added signal is used. The luminance signal (Y) and the color signal (C) in the camera unit signal processing circuit 112.
Is generated and recorded in the odd-numbered line area of the YC memory 113.

Next, during the period f6, the selector 110 selects the output signal of the even-numbered line memory 109 by the field switching pulse, and as shown in FIG.
In 1, the signal of the odd line from the odd line memory 108 and the signal of the even line from the even line memory 109 are added in the vertical direction, and the luminance signal (Y ) And color signal
(C) is generated and recorded in the even line area of the YC memory 113.

Here, in the odd-numbered line processing shown in FIG. 7 and the even-numbered line processing shown in FIG. 8, the combination of pixels for vertical addition is changed as in the first embodiment.
Accordingly, in the case of the NTSC system, the total number of lines is 240 in both odd-line processing and even-line processing, and the line interval is Vf. The line phase differs by Vf / 2.

As described above, a signal equivalent to that in the case of the interlaced drive is obtained.
Then, signal processing is performed on the same field image as a normal moving image.

The luminance signal (Y) in the interlace signal format
After the color signal (C) is stored in the odd line area and the even line area of the YC memory 113, the luminance signal (Y) and the color signal (C) are alternately stored in the odd line area and the even line area. To the YC memory 113
Can output a signal in a progressive signal format.

As described above, in the second embodiment, similarly to the first embodiment, the time required for still image creation can be reduced from the conventional four-field period to the three-field period. Moreover, after that, the luminance signal (Y)
By storing the color signal (C) in the YC memory 113, a signal of a still image in a progressive signal format (non-interlace signal format) can be obtained. Therefore, after that, it is possible to input the data to a recording medium or the like via the progressive signal processing circuit. As the progressive signal processing circuit, a still image signal processing circuit such as J
There is PEG signal processing, and a recording medium includes a memory card and the like.

(Embodiment 3) FIG. 9 is a block diagram of an image pickup apparatus according to Embodiment 3 of the present invention, and portions corresponding to those in Embodiment 1 shown in FIG. Attach.

FIG. 9 differs from FIG. 1 in that a 1H memory 114 is provided in place of the even line memory 109.

The other configuration is the same as that of the first embodiment, and a detailed description is omitted here.

The operation of the imaging apparatus having the above configuration at the time of photographing a still image will be described below with reference to FIGS.

FIG. 10 is an operation timing diagram for generating a still image, FIG. 11 is an explanatory diagram of a signal path, and FIG. 12 is an operational diagram of an image sensor.

In FIG. 10, the same parts as those in FIG. 4 of the first embodiment are denoted by the same reference numerals.

As shown in FIG. 10, assuming that the still image capturing pulse 402 is pressed during the period f2, the stop 1 is set during the period f3.
02 is closed to change from the exposure state to the light shielding state, and the still image creation is started from the period f4.

That is, first, in the period f4, the CCD 103
Are sequentially read out and recorded in the odd-numbered line memory 108.

Next, the signal (B) of the even line of the CCD 103 over two field periods from the period f5 to the period f6.
4) are sequentially read. Then, the signal (B
4) is recorded in the 1H memory 114 line by line. Each time the line switching pulse is input, the selector 110 responds to the output signal of the A / D 107 by 1
One of the output signals from the H memory 114 is alternately selected. In parallel with this operation, the read address control for the odd line memory 108 causes the signal of the odd line stored in the odd line memory 108 to be read.
(A4) is read.

As a result, the vertical addition circuit 111 performs vertical addition on each of vertically adjacent lines as shown in FIG.

First, in the first line, the signal of the (2n + 1) line from the odd line memory 108 and the CCD 103
Is added in the vertical direction with the signal of the (2n + 2) -th line.

In the second line, the odd line memory 10
The vertical addition of the (2n + 3) -line signal from 8 and the (2n + 2) -line signal from the 1H memory 114 is performed.

In the third line, the odd line memory 10
Of odd line (2n + 3) lines from 8 and CCD1
The addition in the vertical direction is performed with the signal of the (2n + 4) line from the line 03.

In the fourth line, the odd line memory 10
The signal of the (2n + 5) line from 8 and the signal of the (2n + 4) line from the 1H memory 114 are added in the vertical direction.

When this is viewed as a signal input to the vertical addition circuit 111, the signal of the (2n + 1) line is initially output from the odd-numbered line memory 108, but thereafter, (2n + 3) and (2n + 3) ), (2n + 5), (2n + 5),
.. Are supplied over two line periods. Also, from the selector 110, (2n +
2), (2n + 2), (2n + 4), (2n + 4), (2n + 6),
(2n + 6),..., A signal of an even-numbered line is given over a two-line period.

Then, the addition signal obtained by the vertical addition circuit 111 is input to the camera section signal processing circuit 112, and the camera section signal processing circuit 112 generates a luminance signal (Y) and a color signal (C).

The CCD 10 for performing the above vertical addition processing
The operation of reading out the charge signal from No. 3 will be described in more detail with reference to FIG.

In FIG. 12, reference numeral 901 denotes an HD signal which is a reference signal in the horizontal direction; 902, a line switching pulse;
Reference numeral 903 denotes a VCCD driving pulse. Note that reference numeral 903 denotes a vertical transfer pulse. 904 is HCC
D drive pulse 905 indicates the output timing of the charge signal in the even line from the CCD 103.

As shown in FIG. 12, when the line switching pulse 902 is "H", the driving pulse 903 for the VCCD 204 is not generated, and the vertical transfer is stopped. Therefore, the signals of the even lines output from the CCD 103 are output at the CCD output timing 9.
As shown in FIG. 05, output is made at two line intervals.

As described above, during the periods f5 and f6, the signal of the even line is output from the CCD 103 at an interval of two lines. Therefore, the selector 110 switches the A / D 107 output signal to the 1H memory 1 by the line switching pulse.
14 and the selector 110
Thus, the same signal on the even-numbered lines of the CCD 103 can be output continuously over a two-line period.

As described above, the odd line memory 1
From 08, a signal of an odd line is output over a period of two lines by read address control.

As a result, in the first line, (2n +
The imaging signal (Ye, Cy) in the 1) region and the imaging signal (Mg, G) in the (2n + 2) region are added in the vertical direction in the vertical addition circuit 111 to become an addition signal (Ye + Mg, Cy + G). Thereafter, the signal is output through the camera signal processing circuit 112.

Subsequently, in the second line, the imaging signal (Mg, G) in the (2n + 2) area and the imaging signal (Y in the (2n + 3) area)
e, Cy) are added in the vertical direction in the vertical addition circuit 111 to become an addition signal (Ye + Mg, Cy + G), which is then output via the camera unit signal processing circuit 112.

Similarly, by changing the combination of the pixels of the vertical addition for each line, the signal of the odd line and the signal of the even line at the time of the interlace driving are alternately generated, and the signal of the camera section is generated. The processing circuit 112 performs signal processing on a frame image in which one frame is composed of 480 lines.

As described above, the luminance signal (Y) and the chrominance signal (C)
Is a progressive signal format (non-interlaced signal format)
Then, the data is input to a recording medium or the like via a progressive signal processing circuit (not shown). As the progressive signal processing circuit, a still image signal processing circuit, for example, J
There is a PEG signal processing circuit, and a recording medium includes a memory card and the like.

As described above, in the third embodiment, the time required to generate a still image is reduced from the conventional four-field period by three.
It can be shortened to the field period, and
A still image signal in a progressive signal format can be obtained. Furthermore, the image memory 1 is different from the first and second embodiments.
It is possible to reduce 14 memory capacities.

(Embodiment 4) FIG. 13 is a block diagram of an image pickup apparatus according to Embodiment 4 of the present invention, and portions corresponding to the configuration of Embodiment 3 shown in FIG. Is attached.

The fourth embodiment differs from the configuration of the third embodiment shown in FIG.
13 is provided.

The other configuration is the same as that of the third embodiment, and the detailed description is omitted here.

The operation of the image pickup apparatus having the above configuration at the time of photographing a still image will be described below with reference to the signal path diagram shown in FIG. The operation timing of the still image creation is the same as that shown in FIGS. 10 and 11 of the third embodiment, and the operation of the CCD 103 is the same as that of FIG. 12 of the third embodiment. Is omitted.

Also in the fourth embodiment, as in the third embodiment, the first line has an image pickup signal (Ye, Cy) in the (2n + 1) area and an image pickup signal (Mn) in the (2n + 2) area.
g, G) are added in the vertical direction in the vertical adder circuit 111, and the added signal (Ye + Mg, Cy + G) is passed through the camera unit signal processing circuit 112 to the (2n + 1) of the YC memory 113.
Recorded in the area.

Subsequently, in the second line, the image pickup signal (Mg, G) in the (2n + 2) area and the image pickup signal (Y in the (2n + 3) area)
e, Cy) are added in the vertical direction by the vertical addition circuit 111, and the addition signal (Ye + Mg, Cy + G) is recorded in the (2n + 2) area of the YC memory 113 via the camera unit signal processing circuit 112.

Similarly, by changing the combination of the pixels of the vertical addition for each line, the signal of the odd line and the signal of the even line at the time of the interlace driving are alternately generated. The circuit 112 performs signal processing on a frame image in which one frame is composed of 480 lines.

As described above, the luminance signal (Y) and the color signal (C)
Is a progressive signal format (non-interlaced signal format)
Then, by storing the luminance signal (Y) and the chrominance signal (C) in the progressive signal format in the YC memory 113, the YC memory 113 can make the interlaced signal format. Therefore, then
The data can be input to a recording medium or the like via an interlace signal processing circuit (not shown). The interlace signal processing circuit includes a moving image signal processing circuit, for example, a DV format recording signal processing, and a recording medium such as a tape.

As described above, in the fourth embodiment, the time required for generating a still image can be reduced from the conventional four-field period to three-field period, and moreover, compared to the first and second embodiments. Thus, the memory capacity of the image memory 114 can be reduced. In addition, the luminance signal
By storing (Y) and the color signal (C) in the YC memory 113, a still image in an interlaced signal format can be obtained.

(Embodiment 5) FIG. 15 is a block diagram of an imaging apparatus according to Embodiment 5 of the present invention, and portions corresponding to those of the configuration of Embodiment 4 shown in FIG. Is attached.

The fifth embodiment differs from the fourth embodiment shown in FIG.
7 and an odd line memory 108, a selector 115 is provided, and a selector 116 for selecting the output of the YC memory 113 and the output of the odd line memory 108 is provided.
Further, the memory capacity of the YC memory 113 is reduced according to the fourth embodiment.
(In this case, memory capacity for 240 lines)
It is set to.

The other configuration is the same as that of the fourth embodiment, and the detailed description is omitted here.

The operation of the imaging apparatus having the above configuration at the time of photographing a still image will be described below with reference to the signal path diagram shown in FIG. The operation timing of the still image creation is the same as that shown in FIGS. 10 and 11 of the third embodiment, and the read operation of the CCD 103 is also the same as that shown in FIG. 12 of the third embodiment. Therefore, detailed description is omitted.

The selector 115 switches the connection so that the output of the A / D 107 is given to the odd line memory 108 during the period f4 shown in FIG.
The signal (A4) of the odd line 03 is sequentially read out and recorded in the odd line memory 108. After that, selector 1
Reference numeral 15 switches the connection so that the output of the camera unit signal processing circuit 112 is provided to the odd line memory 108 until the still image signal processing for one frame is completed.

As in the case of the third embodiment, in both the periods f5 and f6 shown in FIG. 10, the output from the CCD 103 is at two line intervals, and the output signal of the A / D 107 and the output signal of the 1H memory 114 are output. And the selector 110, the signal of the even line of the CCD 103 is changed to 2
Output over the line period.

The odd line memory 108 outputs a signal of an odd line over a two-line period by controlling a read address.

As a result, first, in the first line, the signal (Y) of the (2n + 1) line from the odd line memory 108 is output.
e, Cy) and (2n + 2) line signals from the CCD 103
(Mg, G) are added in the vertical direction in the vertical addition circuit 111 to become an addition signal (Ye + Mg, Cy + G), and this addition signal is converted into a luminance signal (Y) and a color signal (C) by the camera unit signal processing circuit 112. These signals are generated and stored in the selector 115 without being stored in the YC memory 113.
(2n) of the odd line memory 108.
+1) area.

Next, in the second line, the 1H memory 11
4 (2n + 2) line signals (Mg, G) and (2n + 3) line signals (Ye, Cy) from the odd line memory 108.
Are added in the vertical direction in a vertical addition circuit 111 to become an addition signal (Ye + Mg, Cy + G), and this addition signal is generated as a luminance signal (Y) and a chrominance signal (C) by the camera unit signal processing circuit 112. The signal is recorded in the (2n + 2) area of the YC memory 113.

In the third line, the odd line memory 10
8 (2n + 3) line signals (Ye, Cy) and CCD 1
The signal (G, Mg) of the (2n + 4) line from the line 03 is added in the vertical direction in the vertical addition circuit 111, and the added signal is obtained.
(Ye + G, Cy + Mg), and the added signal is output from the camera unit signal processing circuit 112 to the luminance signal (Y) and the chrominance signal.
(C), and these signals are stored in the YC memory 113.
Is fed back to the selector 115 without being stored in the (2n + 3) area of the odd line memory 108.

Next, in the fourth line, the 1H memory 11
4 (2n + 4) line signals (G, Mg) and (2n + 5) line signals (Ye, Cy) from the odd line memory 108.
Are added in the vertical direction in a vertical addition circuit 111 to become an addition signal (Ye + G, Cy + Mg), and this addition signal is generated as a luminance signal (Y) and a chrominance signal (C) by the camera unit signal processing circuit 112. The signal is recorded in the (2n + 4) area of the YC memory 113.

Similarly, after the period of f5 and f6 in FIG. 10 has elapsed, the odd line memory 108 stores one of the odd lines by changing the combination of pixels for vertical addition for each line. For the field (here 2
The luminance signal (Y) and the chrominance signal (C) for 40 lines are stored, and the luminance signal (Y) and the chrominance signal for one field (here, 240 lines) of even lines are stored in the YC memory 113. (C) is stored. Therefore, the YC memory 113 only needs to have a memory capacity equivalent in size to the odd line memory 108.

Thereafter, by switching the selector 116 for each field, for example, the odd line memory 1
After reading the luminance signal (Y) and the chrominance signal (C) for one field of the odd-numbered line from 08, the YC memory 113
If the luminance signal (Y) and the chrominance signal (C) for one field of an even line are read out from the memory, an interlaced signal format can be obtained.

Therefore, it is possible to thereafter input the data to a recording medium or the like via an interlace signal processing circuit (not shown). The interlace signal processing circuit includes a moving image signal processing circuit, for example, a DV format recording signal processing circuit, and a recording medium such as a tape.

As described above, in the fifth embodiment, the time required for creating a still image is reduced from the conventional four-field period to three.
It can be shortened to the field period, and
The memory capacity of the image memory 113 can be further reduced as compared with the case of the fourth embodiment. Furthermore, by storing the luminance signal (Y) and the chrominance signal (C) in the odd-numbered line memory 108 and the YC memory 113, it is possible to obtain a still image in an interlaced signal format.

In the first to fifth embodiments, Ye, Mg, Cy, and G are used as the color filters of the CCD 103 in the field color difference line sequential system.
It is not limited to this.

Also, in the operation timing of the above-described first to fifth embodiments at the time of still image creation, C
The case of reading the signal of the odd number line of the CD 103 has been described. However, the present invention is not limited to this. In the case of a high number of pixels for still image shooting, for example, C having a pixel number of 1280H × 960 V
When processing is performed at approximately the same frequency as that of moving image shooting using the CD 103, each processing requires four times the period (eg, the reading period of the odd-numbered line signal is about four fields). Similarly, the shortening of the time required for photographing has a four-fold effect.

[0121]

As described above, in the case where the image pickup apparatus of the present invention is provided with an interlaced drive type image pickup device for moving image photographing, it is necessary to carry out frame-free image photographing without blur necessary for producing a still image. This can be realized in a reduced time.

Furthermore, it is possible to reduce the memory capacity required for still image shooting while maintaining this effect.

[Brief description of the drawings]

FIG. 1 is a block diagram of an imaging device according to Embodiment 1 of the present invention.

FIG. 2 is an explanatory diagram of a read operation at the time of capturing a moving image of the image sensor in Embodiment 1;

FIG. 3 is an explanatory diagram of a read operation at the time of capturing a still image by the image sensor according to Embodiment 1.

FIG. 4 is an operation timing diagram when a still image is created in the first embodiment.

FIG. 5 is an explanatory diagram of a signal path at the time of creating a still image according to the first embodiment.

FIG. 6 is a block diagram of an imaging device according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a signal path at the time of odd line processing in the second embodiment.

FIG. 8 is an explanatory diagram of a signal path at the time of even-number line processing in the second embodiment.

FIG. 9 is a block diagram of an imaging device according to a third embodiment of the present invention.

FIG. 10 is an operation timing chart when a still image is created in the third embodiment.

FIG. 11 is an explanatory diagram of a signal path at the time of creating a still image according to the third embodiment.

FIG. 12 is an explanatory diagram of a read operation of an even-numbered line of the image sensor in Embodiment 3;

FIG. 13 is a block diagram of an imaging device according to a fourth embodiment of the present invention.

FIG. 14 is an explanatory diagram of a signal path at the time of creating a still image according to the fourth embodiment.

FIG. 15 is a block diagram of an imaging device according to a fifth embodiment of the present invention.

FIG. 16 is an explanatory diagram of a signal path at the time of creating a still image according to the fifth embodiment.

FIG. 17 is an operation timing diagram when a still image is created in a conventional example.

[Explanation of symbols]

 Reference Signs List 101 lens 102 aperture 103 image sensor 104 image sensor drive circuit 105 image sensor drive control circuit 106 analog signal processing unit 107 A / D 108 odd line memory 109 even line memory 110 selector 112 camera unit signal processing circuit 113 YC memory 114 1H memory 115 Selector 116 Selector

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C065 AA01 AA03 BB38 BB48 CC01 CC02 CC03 CC07 CC08 CC09 DD02 DD07 DD13 DD14 DD17 GG14 GG18 GG21 GG30 GG43

Claims (14)

[Claims] 1. A solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix, and electric charges generated in each of the odd-numbered and even-numbered photoelectric conversion elements of the solid-state imaging element are independently provided as an imaging signal. A solid-state imaging device driving circuit for outputting the solid-state imaging device in a time-series manner; a light-shielding unit that shuts off exposure to the solid-state imaging device in response to a still image shooting; A first storage unit that stores an image signal of one of an odd number line and an even number line of the element; and, at a second timing when the light blocking unit is in a closed state, an image signal of the other line of the solid-state image pickup element. Second to memorize
At the second timing, simultaneously obtaining the image signal stored in the first storage device and the output signal of the solid-state image sensor to generate a first video signal; A video signal for generating a second video signal by simultaneously obtaining the imaging signal stored in the first storage means and the imaging signal stored in the second storage means at a third timing following the timing of An imaging apparatus comprising: a generation unit. 2. The imaging apparatus according to claim 1, wherein the first and second video signals generated by the video signal generation means are connected to an interlace signal processing circuit. 3. A video signal storing both the first video signal and the second video signal generated by the video signal generating means, in addition to the configuration of the imaging device according to claim 1 or 2. An imaging device comprising storage means. 4. The video signal storage means for storing both the first video signal and the second video signal is different from the first and second storage means. Imaging device. 5. The imaging device according to claim 3, wherein the first video signal and the second video signal read from the video signal storage unit are connected to a progressive signal processing circuit. apparatus. 6. A solid-state imaging device having a plurality of photoelectric conversion elements arranged in a matrix, and electric charges generated in each of the odd-numbered and even-numbered photoelectric conversion elements of the solid-state imaging element are independently obtained as an imaging signal. A solid-state imaging device driving circuit for outputting the solid-state imaging device in a time-series manner; a light-shielding unit that shuts off exposure to the solid-state imaging device in response to a still image shooting; A first storage unit that stores an image signal of one of an odd number line and an even number line of the element; and, at a second timing when the light blocking unit is in a closed state, an image signal of the other line of the solid-state image pickup element. Second to memorize
And simultaneously obtaining, at the second timing, an imaging signal of the other line of the solid-state imaging device and an imaging signal of one of the lines stored in the first storage means, thereby obtaining a first image. An image pickup apparatus comprising: means for generating a signal; and interpolation means for interpolating the two image pickup signals at the second timing over two line periods. 7. The video signal generated from two image signals obtained simultaneously at the second timing is connected to a progressive signal processing circuit.
An imaging device according to any one of the preceding claims. 8. An image pickup device according to claim 6, further comprising a video signal storage unit for storing a video signal generated from said interpolation unit output signal at said second timing. An imaging device characterized by the above-mentioned. 9. The imaging apparatus according to claim 8, wherein the video signal storage unit shares a memory with the first storage unit. 10. The imaging device according to claim 8, wherein the video signal stored in the video signal storage unit is connected to an interlace signal processing circuit. 11. The imaging device according to claim 6, wherein the output signal from the solid-state imaging device at the second timing is an intermittent signal. 12. The interpolation means for the output signal of the solid-state imaging device has a memory having a capacity of approximately one line, and the interpolation means for the output signal of the first storage means has a memory control means for reading out signals in the same area. The imaging device according to any one of claims 6, 8, and 9, wherein: 13. The apparatus according to claim 2, wherein said means for generating a video signal includes an addition process of a signal of an even-numbered line and a signal of an odd-numbered line adjacent to each other on the solid-state imaging device.
The imaging device according to any one of 7, 8, and 9. 14. The image pickup apparatus according to claim 1, wherein the light blocking means is a stop capable of adjusting a light amount.