JPH04369962A - Solid-state image pickup device and its control method - Google Patents

Abstract

PURPOSE:To operate the photoelectric conversion part of multi picture elements equivalent to the photoelectric conversion part of a small picture element and to improve its flexibility by generating a transfer clock signal varied according to the change request of the resolution and performing the split variable transfer control of the electric charge transfer element part. CONSTITUTION:This device is provided with a photoelectric conversion part 11 converting an image pickup light with (n) picture elements into signal charges S1, S2,... Sn-1, Sn, a charge transfer gate part 12 gate-controlling the signal charge S1, S2,... Sn-1, Sn a charge transfer element part 13 controlling the transfer of the signal charges S1, S2, Sn-1,... Sn, and a transfer clock generation part 14 outputting a plurality of transfer clock signals phi k, k=1,2...k. The transfer clock generation part 14 generates the transfer clock signals ¦, k:1,2...k of 2<n> phase [m=1,2,3,...m] based on an external control signal Sm.

Description

[Detailed description of the invention]

[Table of Contents] Industrial Application Fields Prior Art (Fig. 8) Problems to be Solved by the Invention Means for Solving the Problems (Figs. 1 and 2) Working Examples (1) First Example (FIGS. 3 to 6) (2) Description of the second embodiment (FIG. 7) Effects of the invention

0002

[Field of Industrial Application] The present invention relates to a solid-state imaging device and a control method thereof. More specifically, the present invention relates to a solid-state imaging device and a method for controlling the same. The present invention relates to a solid-state imaging device (line sensor) and a control method thereof.

In recent years, solid-state imaging devices have been used as facsimiles for reading images of objects moving at a constant relative speed. According to this, depending on the specifications of the facsimile, the photoelectric conversion unit is selected from a series with a resolution of 8 [lines/mm] and a series with a resolution of 16 [lines/mm]. In the transfer clock generation section,
Transfer clock signals are generated in a fixed manner as 2-phase, 4-phase, etc. in accordance with the resolution.

[0004] For this reason, when there is a demand for using a solid-state imaging device with a high resolution at a low resolution, it becomes difficult to meet this demand. Therefore, by generating a variable transfer clock signal in response to a resolution change request and performing division variable transfer control of the charge transfer element section, a multi-pixel photoelectric conversion section can operate equivalently to a small-pixel photoelectric conversion section. There is a need for an apparatus and a control method thereof that can improve the versatility of the apparatus.

[0005]

2. Description of the Related Art FIG. 8 shows a configuration diagram of a conventional solid-state imaging device. In FIG. 8, a one-dimensional solid-state imaging device (line sensor) that reads an image of an object moving at a constant relative speed includes a photoelectric conversion section 1, a charge transfer gate section 2,
It consists of a charge transfer element section 3, a transfer clock generation section 4, and an output amplifier 5.

[0006] The function of the device is, for example, one line n=
In the case of 4000 [pixels], the imaging light related to the object to be imaged such as characters or symbols is converted into signal charges S1, S2...S by the photoelectric conversion unit 1.
3999, S4000, the signal charges S1, S2...S399 related to all pixels are converted by the charge transfer gate section 2.
9, S4000 is gate-controlled and transferred to the charge transfer element section 3 all at once.

[0007] Furthermore, signal charges S1, S2...S3999,
S4000 is controlled to be transferred sequentially from charge transfer element section 3 to output amplifier 5 based on two-phase transfer clock signals Φ1 and Φ2. At this time, as shown in FIG. 8(b),
Two-phase transfer clock signals Φ1 and Φ2 fixedly generated by the transfer clock generating section 4 are supplied to the gate electrode of the charge transfer element section 3.

As a result, an image signal SA of an object moving at a constant relative speed is output from the output amplifier 5 (FIG. 8).
(see (c)).

[0009]

[Problems to be Solved by the Invention] According to the conventional example, depending on the application of the solid-state imaging device, for example, specifications for facsimile, etc., the photoelectric conversion section 1 has a resolution of 8 [lines/mm], 16 [lines/mm] of photoelectric conversion units 1 are selected, and thereby, in the transfer clock generation unit 4, the transfer clock signals Φ1, Φ2 are fixedly generated as 2-phase, 4-phase, etc. according to the resolution. Ru.

[0010] Therefore, in a solid-state imaging device equipped with a 4000-pixel photoelectric conversion unit 1 having a high resolution such as 16 lines/mm, if there is a request to use it at a resolution of 8 lines/mm, it is necessary to The problem is that it is difficult to deal with.

This is because, while the productivity of the 4000 pixel photoelectric conversion unit 1 has increased, it is necessary to replace the 2000 pixel photoelectric conversion unit 1 in terms of maintenance management of a solid-state imaging device having a resolution of 8 lines/mm or the like. If necessary, or in a solid-state imaging device having a 4000-pixel photoelectric conversion unit 1, we will make some concessions to the reduction in the resolution of the imaged object and demand a high image acquisition speed. This applies to cases such as

The present invention was created in view of the problems of the conventional example, and generates a transfer clock signal by varying it in accordance with a request for changing the resolution, and performs variable division transfer control of the charge transfer element section. The purpose of the present invention is to provide a solid-state imaging device and its control method, which allows a multi-pixel photoelectric conversion section to operate equivalently to a small-pixel photoelectric conversion section and improves its versatility. .

[0013]

[Means for Solving the Problems] FIG. 1 is a principle diagram (Part 1) of a solid-state imaging device and its control method according to the present invention, and FIGS. A principle diagram (Part 2) of the imaging device and its control method is shown.

As shown in FIG. 1, the first solid-state imaging device of the present invention converts imaging light of n pixels into signal charges S1, S2...Sn-
1, Sn, a charge transfer gate section 12 that controls the gates of the signal charges S1, S2...Sn-1, Sn, and the signal charges S1, S2...Sn.
A charge transfer element section 13 that controls the transfer of n-1 and Sn, and a plurality of transfer clock signals Φ to the charge transfer element section 13.
Transfer clock generator 14 that outputs k, k=1, 2...k
The transfer clock generating section 14 generates transfer clock signals Φk, k=1, 2...k of 2m phases [m=1, 2, 3...m] based on the external control signal Sm. Features.

Note that in the first solid-state imaging device,
Based on the external control signal Sm, the transfer clock signal Φ
It is characterized by being provided with a clock supply control section 15 that controls the supply of clocks k, k=1, 2, . . . k.

[0016] Furthermore, in the first solid-state imaging device,
It is characterized in that the charge transfer gate section 12 is provided in common for the photoelectric conversion sections 11 of n pixels. Furthermore, in the first solid-state imaging device, the charge transfer gate section 12
Also, the charge transfer element section 13 is provided on one side with respect to the photoelectric conversion section 11 of n pixels.

The second solid-state imaging device of the present invention is shown in FIG.
As shown in (a), in the first solid-state imaging device,
The charge transfer gate section 12 and the charge transfer element section 13 are n
It is characterized in that it is provided on both sides of the photoelectric conversion section 11 of the pixel.

Further, a method for controlling a solid-state imaging device according to the present invention is a method for controlling the first and second solid-state imaging devices, comprising:
As shown in the flowchart of FIG. 2(b), first, in step P1, signal charges S1, S2...Sn-1,
Resolution mode Mi for switching the Sn transfer control block
Then, in step P2, a process is performed to generate transfer clock signals Φk, k=1, 2...k of 2m phases [m=1, 2, 3...i] based on the resolution mode Mi. ,
Additionally, in step P3, the transfer clock signal Φk,k
=1, 2...k supply control processing, and then step P
4, the signal charges S1, S2...Sn-1, Sn subjected to photoelectric conversion processing are added and transferred based on the resolution mode Mi.

In the first control method of the solid-state imaging device, signal charges S1,
S2...is characterized by performing addition transfer processing of Sn-1 and Sn.

[0020] Also, a second control method for the solid-state imaging device, in which the signal charges S1, S3, . . .
3, Sn-1 and signal charges S2, S4, .

[0021]

[Operation] According to the first solid-state imaging device of the present invention, as shown in FIG.
, a charge transfer element section 13, and a transfer clock generation section 14, and the transfer clock generation section 14 receives an external control signal Sm.
2m-phase (m=1, 2, 3...m) transfer clock signals Φk, k=1, 2...k are generated based on the following.

For example, the imaging light of n pixels is transmitted to the photoelectric conversion unit 11.
When the signal charges are converted into signal charges S1, S2...Sn-1, Sn, the signal charges S1, S2...S
n-1, Sn are gate-controlled, and the photoelectric conversion unit 11
The charge transfer element section 13 provided on one side of the
Signal charges S1, S2...Sn-1, Sn are transferred to the charge transfer element section 13. At this time, unlike the conventional example, for example, 2m phases [m=
1, 2, 3...m] transfer clock signal Φk, k = 1, 2
...k is output from the clock generating section 14 to the charge transfer element section 13.

[0023] Therefore, 2m phase [m=1, 2, 3...m
] Signal charges S1, S2...S transferred from the photoelectric conversion unit 11 based on the transfer clock signal Φk, k=1, 2...k
It becomes possible to perform addition transfer processing (first control method) for two or more adjacent pixels in n-1 and Sn.

[0024] This makes it possible to perform variable division transfer control of the charge transfer element section in response to a resolution change request. This allows a multi-pixel photoelectric conversion section to operate equivalently to a small-pixel photoelectric conversion section.

Further, according to the second solid-state imaging device of the present invention, as shown in FIG. established in

Therefore, based on the 2m phase (m=1, 2, 3...m) transfer clock signals Φk, k=1, 2...k generated by the transfer clock generator 14, the signals from the photoelectric converter 11 to both sides are In the charge transfer element section 13 provided in the charge transfer element section 13, signal charges S1, S3...Sn-3, Sn-
1 and the signal charges S2, S4...Sn related to the even-numbered pixels
−2 and Sn can be subjected to addition calculation processing (second control method).

[0027] As a result, similarly to the first solid-state imaging device, it is possible to perform division variable transfer control of the charge transfer element section in response to a resolution change request, and to convert a multi-pixel photoelectric conversion section into a small-pixel photoelectric conversion section. It becomes possible to operate equivalently to the converter.

Further, according to the method for controlling a solid-state imaging device of the present invention, as shown in the flowchart of FIG. 2(b), 2m phase [m
= 1, 2, 3...i] transfer clock signal Φk, k = 1,
2...k is generated, and in step P3, supply control processing of transfer clock signals Φk, k=1, 2...k is performed.

Therefore, in step P4, based on the first control method, that is, the resolution mode M, the signal charges S1, S2...Sn-1, transferred from the photoelectric conversion section 11 are
By carrying out addition and transfer processing of two or more adjacent pixels in Sn, it is possible to sufficiently cope with, for example, a request to use a solid-state imaging device with a high resolution at a low resolution. becomes.

[0030] This makes it possible to perform division variable transfer control of the photoelectric conversion section 11 in response to a resolution change request, thereby making it possible to improve the versatility of the solid-state imaging device.

[0031] Note that in step P4, the second control method,
That is, based on the resolution mode M, the photoelectric conversion unit 11
Signal charges S1, S3...Sn-3 related to odd-numbered pixels of
Similarly, the versatility of the solid-state imaging device can be improved by performing addition transfer processing of Sn-1 and signal charges S2, S4...Sn-2, Sn related to even-numbered pixels of the photoelectric conversion unit 11. It becomes possible to achieve this goal.

[0032]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. 3 to 7 are diagrams illustrating a solid-state imaging device and a control method thereof according to an embodiment of the present invention.

(1) Description of the first embodiment FIG. 3 is a block diagram of a solid-state imaging device according to the first embodiment of the present invention, FIG. 4 is a control flowchart thereof, and FIGS. 5 and 6 show its operation. Explanatory diagrams are shown respectively.

For example, a solid-state imaging device that performs division variable transfer control of signal charges according to resolution requirements is shown in FIG. It consists of a clock supply control section 15 and an output amplifier 16.

The photoelectric conversion unit 11 includes, for example, 40 units arranged in a line in a direction perpendicular to the moving direction of the object to be imaged.
Consists of 00 pixel photoelectric conversion elements, and converts the imaging light (black and white level) of characters, symbols, etc. into signal charges S1, S2...S399
9, S4000.

The charge transfer gate section 12 transfers signal charges S1, S
2...Controls the gates of S3999 and S4000. For example, the charge transfer gate unit 12 is provided in common for the photoelectric conversion units 11 of 4000 pixels, and the charge transfer gate unit 12 is connected to the photoelectric conversion units 11 of 4000 pixels based on the gate control signal SG generated by the transfer clock generation unit 14. Part 13
Signal charges S1, S2...S3999, S4000 all at once
It is intended to transfer.

Further, in the first embodiment of the present invention, the charge transfer gate section 12 is provided on one side of the photoelectric conversion section 11 of 4000 pixels. Charge transfer element section (charge transfer element row)
13 is a CCD (Charge Coupled De
vice), etc., and signal charges S1, S2...S3999, S4000 based on pixel control modes M1 to M4.
This is to perform sequential addition and transfer control in the direction of the output amplifier 16. Further, the charge transfer element section 13 is provided on one side of the photoelectric conversion section 11 of 4000 pixels, and it
It consists of n-type field effect transistors (hereinafter simply referred to as transistors T). For example, when using the photoelectric conversion unit 11 with a resolution of 1, the two-phase transfer clock signals Φ1 and Φ2 applied to the transfer gate electrodes of the two transistors T (hereinafter simply referred to as transfer gate electrodes T1 and T2) are Transfer of one pixel is controlled by setting the level to "H" (high) or "L" (low). In addition,
The transfer control method of the charge transfer element section 13 is different from the conventional example, and the control method will be explained in detail with reference to FIGS. 4 to 6.

The transfer clock generating section 14 outputs a plurality of transfer clock signals Φk, k=1, 2 . . . k to the charge transfer element section 13. For example, 2-, 4-, 8-, and 16-phase transfer clock signals, which are an example of the 2m-phase transfer clock signal Φk, are generated based on the pixel control modes M1 to M4 that are the contents of the external control signal Sm. Here, m
is the reciprocal of the resolution, for example, resolution = 1/
In the case of 2, m=2.

The clock supply control unit 15 controls the supply of 2-, 4-, 8-, and 16-phase transfer clock signals Φk, k=1, 2, . . . , based on the pixel control modes M1 to M4. For example, in the case where the photoelectric conversion unit 11 is composed of 4000 pixels, the pixel control mode M1 is used, that is, the photoelectric conversion unit 11 of 4000 pixels is configured with resolution=1 as in the conventional example.
When used as [4000 pixels], the clock supply control unit 15 supplies signal charges S1, S2...S for each pixel.
In order to sequentially transfer signals 3999 and S4000, two-phase transfer clock signals Φ1 and Φ2 are supplied to the charge transfer element section 13, and at the same time, the transfer gate electrodes constituting the charge transfer element section 13 are controlled and divided into two groups. do.

In addition, the pixel control mode M2, that is, the resolution of the photoelectric conversion unit 11 = 1/2 [2000 pixels = 400
0 pixel/2], the clock supply control unit 15 supplies signal charges S1, S2...S39 in units of two pixels.
99, S4000, four-phase transfer clock signals Φ1 to Φ4 are supplied to the charge transfer element section 13,
At the same time, the transfer gate electrodes constituting the charge transfer element section 13 are controlled and divided into four groups.

Furthermore, pixel control mode M3, that is,
Resolution of photoelectric conversion unit 11 = 1/4 [1000 pixels = 40
00 pixels/4], the clock supply control unit 15 supplies signal charges S1, S2...S3 in units of four pixels.
In order to add and transfer 999 and S4000, 8-phase transfer clock signals Φ1 to Φ8 are supplied to the charge transfer element section 13, and at the same time, the 8000 transfer gate electrodes that constitute the charge transfer element section 13 are connected to each other by eight transfer gate electrodes. to control classification.

Note that in pixel control mode M4, that is, the resolution of the photoelectric conversion unit 11 = 1/8 [500 pixels = 400
0 pixel/8], the clock supply control unit 15 supplies signal charges S1, S2...S39 in units of 8 pixels.
99, S4000, 16-phase transfer clock signals Φ1 to Φ16 are supplied to the charge transfer element section 13, and at the same time, the transfer gates constituting the charge transfer element section 13 are controlled in groups of 16 at a time. do.

Table 1 shows pixel control modes M1 to M4.
The number of phases of the transfer clock signal Φk [2m phases], the control section of the photoelectric conversion unit 11, and the resolution are summarized.

[0044]

[Table 1]

In this manner, according to the solid-state imaging device according to the first embodiment of the present invention, as shown in FIG. A transfer clock generating section 14 is provided, and the transfer clock generating section 14 generates 2, 4, 8,
16-phase transfer clock signal [Φ1, Φ2], [Φ1~Φ
4], [Φ1 to Φ8], and [Φ1 to Φ16].

For example, the imaging light of n=4000 pixels is converted into signal charges S1, S2...S3999, S by the photoelectric conversion section 11.
4000, the signal charges S1, S2...S3999, S4000 are gate-controlled by the charge transfer gate section 12 provided in common to the photoelectric conversion section 11, and one side of the signal charges S1, S2...S3999, S4000 are The signal charges S1, S2...S3999,
S4000 is transferred to the charge transfer element section 13. At this time, unlike the conventional example, if the resolution is set to 1/2, for example, four-phase transfer clock signals Φ1 to Φ are generated by the transfer clock generation section 14 based on the external control signal Sm.
4 is output from the clock generating section 14 to the charge transfer element section 13.

Therefore, the four-phase transfer clock signals Φ1 to
Based on Φ4, it becomes possible to perform addition transfer processing (first control method) on two adjacent pixels among the signal charges S1, S2...S3999, S4000 transferred from the photoelectric conversion unit 11.

[0048] This makes it possible to perform variable division transfer control of the charge transfer element section 13 in response to a resolution change request. This allows a multi-pixel photoelectric conversion section to operate equivalently to a small-pixel photoelectric conversion section.

Next, a method of controlling a solid-state imaging device according to an embodiment of the present invention will be explained with supplementary explanation of the operation of the solid-state imaging device. FIG. 4 shows a control flowchart of the solid-state imaging device according to the embodiment of the present invention. For example, 40
The resolution of the photoelectric conversion unit 11 of 00 pixels is set to 1/2,
Signal charges S1, S2,...S3 related to two adjacent pixels
When carrying out addition transfer processing of 999, S4000, in FIG. 4, first, in step P1, input processing of resolution mode M2 is performed to switch the transfer control block of signal charges S1, S2 . . . S3999, S4000 of 4000 pixels. At this time, the user selects mode M2 from among the resolution modes M1 to M4 via the external control signal Sm.

Next, in step P2, four-phase transfer clock signals Φ1 to Φ4 are generated based on the resolution mode M2. At this time, the transfer clock generation section 14 generates four-phase transfer clock signals Φ1 to Φ4 and a gate control signal SG as shown in FIG. Output.

At the same time, in step P3, the charge transfer element section 13 to which the transfer clock signals Φ1 to Φ4 are supplied is controlled. At this time, as shown in FIG. 6, in the clock supply control section 15, the charge transfer element section 13 in which 8000 transfer gate electrodes are lined up is connected to four transistors (transfer gate electrodes) T1 to T4 based on the pixel control mode M2. A set of 2
000 control areas B1 to B2000, and four-phase transfer clock signals Φ1 to B2000 are respectively applied to the transfer gate electrodes.
Φ4 is supplied.

Thereafter, in step P4, the resolution mode M2 is set.
Signal charges S1, S2...S subjected to photoelectric conversion processing based on
3999, performs the addition transfer processing of S4000. At this time, the clock supply control unit 15 selects the pixel control mode M2,
That is, the resolution of the photoelectric conversion unit 11 = 1/2 [2000
pixel = 4000 pixels/2], signal charges S1, S2...S399 transferred from the photoelectric conversion unit 11
9, S4000 is added and transferred in units of two pixels (first control method). In the first embodiment of the present invention, adjacent odd-numbered pixels and even-numbered pixels are added.

For example, control block B as shown in FIG.
To explain the addition transfer operation at 1, first, at time t=2 (t=1), the gate control signal SG=
"H" level is applied to the charge transfer gate section 12, clock signals Φ2, Φ4 = "L" level are applied to the transfer gate electrodes T1, T3, and Φ1, Φ3 = "H" level is applied to the transfer gate electrodes. It is applied to T2 and T4 (see drive timing in FIG. 5).

[0054] As a result, the potential conceptual diagram in Fig. 6 (
As shown in the cross-sectional view of the charge transfer element 13 in the charge transfer direction, the signal charges S1, S2...S3999, S4000 are output to the charge transfer element 13 all at once, and the signal charges S1, S2
...S3999, S4000 are transfer gate electrodes T2, T4
is accumulated in

Next, at time t=3, the clock signals Φ1 to Φ3 are turned on while the gate control signal SG remains at "L" level.
= When "H" level is applied to the charge transfer element section 13,
Signal charges S1, S2...S3999, S4000 are added adjacent to each other for two pixels, and the signal charges are transferred to the transfer gate electrode T.
S1+S2...S3997+S399 under 2-T4
8, S3999+S4000.

Thereafter, at time t=4, the gate control signal SG remains "L" and the clock signals Φ1, Φ4="
When the "L" level is applied to the transfer gate electrodes T1, T2 and the clock signal Φ2, Φ3="H" level is applied to the transfer gate electrodes T3, T4, the transfer gate electrodes T3, T4
At the bottom, signal charges S1+S2...S3997+S399
8, S3999+S4000 are sequentially moved toward the output amplifier 16. Therefore, the signal charge S1+S2 at time t
After =4, the signal is first output to the output amplifier 16.

Furthermore, at time t=5, the clock signals Φ1 and Φ remain at the "L" level of the gate control signal SG.
2. When Φ4 = "L" level and Φ3 = "H" level are applied to the charge transfer element section 13, signal charges S1+S2...S3997+S3998,
S3999+S4000 are sequentially moved toward the output amplifier 16.

Next, at time t=6, the clock signals Φ1 and Φ remain at the "L" level of the gate control signal SG.
When 2 = "L" level and Φ3, Φ4 = "H" level are applied to the charge transfer element section 13, the transfer gate electrodes T1, T
4 below, signal charge S1+S2...S3997+S39
98, S3999+S4000 are sequentially moved toward the output amplifier 16.

Next, at time t=7, the clock signals Φ1 to Φ3 are turned on while the gate control signal SG remains at "L" level.
When the = "L" level and Φ4 = "H" level are applied to the charge transfer element section 13, signal charges S1+S2...S3997+S3998, S399 are generated under the transfer gate electrode T1.
9+S4000 are sequentially moved toward the output amplifier 16.

Thereafter, at time t=8, the clock signals Φ2 and Φ remain at the "L" level of the gate control signal SG.
When 3 = "L" level and Φ1, Φ4 = "H" level are applied to the charge transfer element section 13, the transfer gate electrodes T1, T
2 below, signal charge S1+S2...S3997+S39
98, S3999+S4000 are sequentially moved toward the output amplifier 16.

Furthermore, at time t=9, the clock signals Φ2 to Φ remain at the "L" level of the gate control signal SG.
When 4 = "L" level and Φ1 = "H" level are applied to the charge transfer element section 13, signal charges S1+S2...S3997+S3998, S39 are generated under the transfer gate electrode T2.
99+S4000 are sequentially moved toward the output amplifier 16.

As a result, the signal charges S3999+S4000 transferred all at once to control block B1 are sequentially transferred to control blocks B2 and B3. Next, step P5
Then, an operation is performed to confirm whether or not the charge transfer of the image related to one line has been completed. If the transfer is not completed at this time (
If NO), the charge transfer operation continues until the next gate control signal SG becomes "H" level. If the transfer is completed (YES), the process moves to step P6.

That is, in step P6, a confirmation operation is performed to determine whether or not the control processing of the image pickup apparatus has been completed. At this time, if the control is not completed (NO), the charge transfer operation for the image of the next line is continued. Further, if the transfer operation is completed (YES), the control is ended.

In this manner, according to the method for controlling a solid-state imaging device according to the first embodiment of the present invention, as shown in the control flowchart of FIG. The transfer clock signals Φ1 to Φ4 are generated, and in step P3, the transfer clock signals Φ1 to Φ4 are generated.
4 supply control processing is being performed.

Therefore, in step P4, based on the first control method, that is, the resolution mode M2, the signal charges S1, S2...S3999 transferred from the photoelectric conversion section 11 are
, S4000, there is a demand for using a solid-state imaging device with a high resolution of 8 lines/mm at a low resolution of 4 lines/mm. If this happens, it will be possible to adequately deal with this problem.

[0066] This makes it possible to perform division variable transfer control of the photoelectric conversion section 11 in response to a resolution change request, thereby making it possible to improve the versatility of the solid-state imaging device.

(2) Explanation of Second Embodiment FIG. 7 is a block diagram of a solid-state imaging device according to a second embodiment of the present invention. In FIG. 7, the difference from the first embodiment is that in the second embodiment, the charge transfer gate section 12 and the charge transfer element section 13 are
These are provided on both sides of the photoelectric conversion section 11 of the 00 pixel.

That is, the first charge transfer gate section 12A
constitutes another embodiment of the charge transfer gate section 12, and the signal charges S2,
S4...S3998 and S4000 are controlled to be transferred all at once to the first charge transfer element section 13A based on the gate control signal SG.

The second charge transfer gate section 12B constitutes another embodiment of the charge transfer gate section 12, and is used to transfer signal charges S1, S3, .
997 and S3999 are simultaneously controlled to be transferred to the second charge transfer element section 13B based on the gate control signal SG.

The first charge transfer element section 13A constitutes another embodiment of the charge transfer element section 13, and stores signal charges S2, S4...S399 related to even-numbered pixels of the photoelectric conversion section 11.
8, S4000 are sequentially moved to the charge transfer adder 13C based on four-phase clock signals Φ1 to Φ4.

The second charge transfer element section 13B constitutes another embodiment of the charge transfer element section 13, and stores signal charges S1, S3...S399 related to odd-numbered pixels of the photoelectric conversion section 11.
7, S3999 is sequentially moved to the charge transfer adder 13C based on four-phase clock signals Φ1 to Φ4.

The charge transfer addition section 13C is provided at a portion connecting the first charge transfer element section 13A and the second charge transfer element section 13B, and adds signal charges S2 and S4 related to even pixels.
...S3998, S4000 and signal charge S related to odd-numbered pixels
1, S3...S3997, S3999 are added.

In this way, according to the solid-state imaging device according to the second embodiment of the present invention, as shown in FIG. Charge transfer element sections 13A and 13B are provided on both sides of the photoelectric conversion section 11 of 4000 pixels.

For this reason, based on the four-phase transfer clock signals Φ1 to Φ4 generated by the transfer clock generating section 14, the charge transfer elements 13A and 13B provided on both sides are transferred from the photoelectric conversion section 11. , signal charges S1, S3...S3997, S3999 related to odd-numbered pixels and signal charges S2, S4...S3998, S40 related to even-numbered pixels.
00 separately and sequentially to the charge transfer adder 13C, and the charge transfer adder 13C can add them (second control method).

As a result, similarly to the first solid-state imaging device, it becomes possible to perform division variable transfer control of the charge transfer element section 13 in response to a resolution change request, and to convert a multi-pixel photoelectric conversion section into a small-pixel photoelectric conversion section. It becomes possible to operate the device equivalently to a photoelectric conversion section. Furthermore, it is also possible to similarly improve the versatility of the solid-state imaging device.

In the embodiment of the present invention, the case where a CCD element is used in the charge transfer element section 13 has been explained, but a BBD (Bucket relay element) such as a bucket relay element (delay element) is used.
A similar effect can be obtained even when using a ``ket Brigade Device''.

[0077]

As described above, the first solid-state imaging device of the present invention includes a photoelectric conversion section, a charge transfer gate section, a charge transfer element section, and a transfer clock generation section, and the transfer clock generation section generates a 2m-phase transfer clock signal based on an external control signal that sets the resolution.

Therefore, it is possible to perform addition transfer of two or more adjacent pixels among the signal charges transferred from the photoelectric conversion section based on the 2m phase transfer clock signal. This makes it possible to perform variable division transfer control of the charge transfer element section in response to a resolution change request.

Further, according to the second solid-state imaging device of the present invention, the charge transfer gate section and the charge transfer element section are provided on both sides of the photoelectric conversion section of n pixels. Therefore, based on the 2m-phase transfer clock signal generated by the transfer clock generation section, it is possible to add and transfer the signal charge related to the odd numbered pixels of the photoelectric conversion section and the signal charge related to the even numbered pixels. . This allows a multi-pixel photoelectric conversion section to operate equivalently to a small-pixel photoelectric conversion section.

Furthermore, according to the method for controlling a solid-state imaging device of the present invention, a 2m-phase transfer clock signal is generated based on the resolution mode, and at the same time, the supply of the transfer clock signal is controlled.

For this reason, if there is a request to use a solid-state imaging device with a high resolution at a low resolution based on the resolution mode, this can be equivalently achieved by controlling the divided variable transfer of the charge transfer element section. It becomes possible to make it function.

[0082] This makes it possible to improve the versatility of the solid-state imaging device and reduce its production cost.

[Brief explanation of drawings]

FIG. 1 is a principle diagram (Part 1) of a solid-state imaging device and its control method according to the present invention.

FIG. 2 is a principle diagram (part 2) of the solid-state imaging device and its control method according to the present invention.

FIG. 3 is a configuration diagram of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 4 is a control flowchart of the solid-state imaging device according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram (Part 1) of the operation of the solid-state imaging device according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram (Part 2) of the operation of the solid-state imaging device according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of a solid-state imaging device according to a conventional example.

[Explanation of symbols]

11...Photoelectric conversion section, 12...Charge transfer gate section, 13...charge transfer element section, 14...Transfer clock generation section, 15...Clock supply control section, Sm...external control signal, Φk...Transfer clock signal, S1-Sn...Signal charge.

Claims (7)

[Claims] Claim 1: Imaging light of n pixels is converted into signal charges (S1, S
2...Sn-1, Sn) photoelectric conversion unit (11
) and the signal charges (S1, S2...Sn-1, Sn
), a charge transfer gate section (12) for controlling the gate of the signal charges (S1, S2...Sn-1, Sn), a charge transfer element section (13) for controlling the transfer of the signal charges (S1, S2...Sn-1, Sn), and the charge transfer element section (13). multiple transfer clock signals (Φk, k=1,
2...k), and the transfer clock generating section (14) outputs 2m phases [m=1, 2, 3...m] based on an external control signal (Sm). A solid-state imaging device characterized in that it generates a transfer clock signal (Φk, k=1, 2...k). 2. The solid-state imaging device according to claim 1, further comprising a clock supply control unit ( Φk, k=1, 2...k) that controls supply of transfer clock signals (Φk, k=1, 2...k) based on the external control signal (Sm). 15) A solid-state imaging device. 3. The solid-state imaging device according to claim 1, wherein the charge transfer gate section (12) is provided in common for photoelectric conversion sections (11) of n pixels. 4. The solid-state imaging device according to claim 1, wherein the charge transfer gate section (12) and the charge transfer element section (
13) is provided on both sides or one side of an n-pixel photoelectric conversion unit (11). 5. A method for controlling a solid-state imaging device according to claim 1, wherein the signal charges of n pixels (S1, S2...Sn-1
,Sn) to input the resolution mode (Mi) to switch the transfer control block of the resolution mode (Mi).
), generates a transfer clock signal (Φk, k=1, 2...k) of 2m phases [m=1, 2, 3...i],
In addition, the transfer clock signal (Φk, k=1, 2...k
) and photoelectrically converted signal charges (S1, S2...Sn) based on the resolution mode (Mi).
1. A method for controlling a solid-state imaging device, characterized by performing addition transfer processing of -1, Sn). 6. The method of controlling a solid-state imaging device according to claim 5, wherein signal charges (S1) related to two or more adjacent pixels of the photoelectric conversion unit (11) are , S2...Sn-1, Sn). 7. The method of controlling a solid-state imaging device according to claim 5, wherein signal charges (S1,
S3...Sn-3, Sn-1) and the photoelectric conversion section (
11) Signal charges (S2, S4...Sn-) related to even-numbered pixels
A method for controlling a solid-state imaging device, characterized in that an addition transfer process is performed on a solid-state imaging device.