JP2007129473A - Solid-state imaging apparatus and imaging system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus for imaging an image of high quality by minimizing a variation in potential due to external noise on a signal line. <P>SOLUTION: The solid-state imaging apparatus is provided which includes: a field effect transistor for an amplifier for amplifying photoelectrically converted electric charges; the signal line (2) connected to the source electrode of the field effect transistor for the amplifier; a field effect transistor (10) constituting a load of a current source connected to the signal line; and a capacitor (7) connected to the gate electrode of the field effect transistor constituting the load of the current source. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an imaging system.

  Today, CMOS area sensors, which are image sensors using MOS transistors, are actively developed. Details of the CMOS area sensor are disclosed in Patent Document 1 and the like. Patent Document 2 discloses a signal readout operation of a MOS type image sensor and its circuit configuration.

Japanese Patent Application Laid-Open No. 2004-320592 JP 2003-046864 A (FIGS. 1 and 2)

  In a CMOS area sensor, a vertical signal line disclosed in Patent Document 1 is a particularly important wiring through which an analog signal passes in a pixel region. In order to provide a reliable CMOS sensor, it is necessary to minimize fluctuations in the potential of the vertical signal line due to noise and signal switching. This will be specifically described. In the configuration of FIG. 1 of Patent Document 2, the potentials of the wirings LGCEL and SCEL for supplying a constant current connected to the gate electrode of the load transistor 6 for configuring the source follower circuit together with the pixel amplifier 5 vary. Due to this voltage fluctuation, the potential of the signal output line 10 fluctuates through a parasitic capacitance generated through the interlayer insulating film. It is desired to reduce the potential fluctuation of the signal output line.

  In view of such problems, it is an object of the present invention to provide a solid-state imaging device and an imaging system that can capture a high-quality image while minimizing potential fluctuation caused by external noise of a vertical signal line.

  The solid-state imaging device of the present invention includes an amplifier field effect transistor for amplifying photoelectrically converted charges, a signal line connected to a source electrode of the amplifier field effect transistor, and a current connected to the signal line. And a capacitor connected to the gate electrode of the field effect transistor constituting the load of the current source.

  By providing the capacitor, fluctuations in the potential of the signal line connected to the source electrode of the amplifier field effect transistor can be prevented. It is possible to capture a high-quality image while minimizing the potential fluctuation caused by the external noise of the signal line.

  Although a preferred embodiment will be described below, any combination of the contents of this embodiment is within the scope of the present invention.

(First embodiment)
FIG. 1 is a circuit diagram showing a peripheral circuit region of the solid-state imaging device according to the first embodiment of the present invention. Hereinafter, the field effect transistor is simply referred to as a transistor. In the figure, 1 is a pixel region, 2 is a vertical signal line, 3 is a horizontal scanning circuit, 4 is a current mirror constituting circuit, 5 is a common gate line of a final MOS transistor constituting a load of a current source, and 6 is for a luminance signal. It is a horizontal signal line. 8 is a signal readout circuit, 9 is an FD potential generation circuit, 10 is a final-stage MOS transistor constituting a load of a current source, 12 is a load current source cutoff MOS transistor, 16 is a noise level horizontal signal line, and 17 is a main amplifier. , 19 are external signal terminals. In this embodiment, the capacitor 7 is attached to the gate electrode of the MOS field effect transistor 10 at the final stage of the load current source. The capacitor 7 is connected to the gate electrode of the transistor 10 for each vertical signal line 2.

  In the first embodiment, the capacitor 7 is composed of one electrode connected to the gate electrode of the load current source final stage MOS transistor 10, the other electrode using a semiconductor substrate, and an oxide film therebetween. FIG. 3 is a plan view (a) and a sectional view (b) showing this configuration. The sectional view (b) is a sectional view taken along the line AA 'in the plan view (a). In the figure, 13 is an n-type silicon substrate, 14 is a p-type well, 15 is an n-type impurity region, and 18 is an oxide film. The other reference numerals are the same as those previously described. Hereinafter, the relationship between these components will be described in detail.

  A p-type well 14 is formed on the surface of the n-type silicon substrate 13, and an n-type impurity region 15 is formed in the p-type well 14. Immediately above the portion without the n-type impurity region 15, one electrode forming the capacitor 7, the gate electrode of the load current source final stage MOS transistor 10, and the gate electrode of the load current source cutoff MOS transistor 12 form the oxide film 18. Exists through. It is desirable that one electrode forming the capacitor 7, the gate electrode of the load current source final stage MOS transistor 10, and the gate electrode of the load current source cutoff MOS transistor 12 be formed of polysilicon. The role of the load current source cutoff MOS transistor 12 will be described later. In this configuration, the capacitor 7 is formed by the same process as that of the MOS transistors 10 and 12 and the like, so there is no cost increase factor due to the formation of the capacitor 7. The capacitor 7 has a MOS structure. A desirable capacity of the capacitor 7 is in the range of 1 to 100 fF. In the cross-sectional view of FIG. 3B, the n-type impurity region 15 is not formed in the lower portion of the capacitor 7, but an n-type impurity region is formed by ion implantation before electrode formation. May be. In this configuration, the p-type well 14 is described as being in the n-type silicon substrate 13, but the p-type well 14 may be omitted and the substrate may be a p-type silicon substrate. Although the MOS transistors 10 and 12 have been described as n-channel MOS transistors, the p-type well 14 may be an n-type well or an n-type silicon substrate and may be a p-channel MOS transistor.

  Furthermore, the other electrode of the capacitor 7 may also be formed of polysilicon. At this time, one electrode of the capacitor 7 is also formed of polysilicon, but the other electrode made of polysilicon is formed on the one electrode via an insulating layer. Even in this configuration, the same effect as described above can be obtained.

  FIG. 2 is a circuit diagram showing the pixel region 1 and the vertical scanning circuit 11. In the figure, 11 is a vertical scanning circuit. PD1-1, PD2-1, etc. are photodiodes, FD1, FD2, and FD3 are floating diffusions, M1 and M2 are transfer MOS transistors, M3 and M5 are reset MOS transistors, and M4 is an amplifier MOS transistor. The other reference numerals are the same as those previously described. Hereinafter, the floating diffusion is abbreviated as FD. In the case of the first embodiment, there is one transfer MOS transistor for each pixel (one photodiode), and one FD, reset MOS transistor, and amplifier MOS transistor for every two pixels (two photodiodes). There is. The FD also serves as a pixel capacitor that accumulates charges transferred from the photodiode.

  The photodiode PD1-1 or the like is a photoelectric conversion unit that generates charges by photoelectric conversion. The transfer MOS transistors M1 and M2 are transfer means for transferring the charges of the photodiodes PD1-1 and PD1-2 to the FD1, respectively. In the amplifier MOS transistor M4, the gate electrode is connected to the FD1, the source electrode is connected to the vertical signal line 2, the drain electrode is connected to the power supply voltage (VDD), the charge of the FD1 is amplified, and the vertical signal line 2 is connected. Output.

  The driving method of the first embodiment will be described using the driving timing chart of FIG. ΦRes1, φTX1, φTX2, and φRes2 in the drawing represent the timing of the voltage of the wiring that leads to the pixel region 1 in FIG. 2, and the wiring positions are described in FIG. φRes1 and φRes2 control on / off of reset MOS transistors M3 and M5, respectively. ΦTX1 and φTX2 control the on / off of the transfer MOS transistors M1 and M2, respectively. ΦVR1 and φVR2 represent the timing of the voltage of the wiring leading to the FD potential generation circuit 9 in FIG. 1, and the wiring positions are described in FIG.

  First, scanning of the first row will be described. At timing t1, the reset MOS transistor M3 is turned on by the high level of φRes1, the potential of FD1 is set to VRH, and FD1, FD2, and FD3 are activated. At this time, the FD potential generation circuit 9 supplies the potential VRH to the vertical signal line 2 by the high level of φVR1 and the high level of φVR2. Next, at timing t2, the load current source cutoff MOS transistor 12 is turned on by the low level of φVR1, and the vertical signal line 2 is connected to the load current source configuration circuit 4 and the load current source final stage MOS transistor 10. As a result, the noise levels of FD1, FD2, and FD3 are read to the read circuit 8 through the amplifier MOS transistor M4 and the vertical signal line 2. Next, at the timing t3, the transfer MOS transistor M1 is turned on by the high level of φTX1, and the charge accumulated in the PD1-1 due to light irradiation is transferred to the FD1. At the same time, charges stored in PD2-1 and PD3-1 by light irradiation are transferred to FD2 and FD3, respectively. Next, at timing t4, the transfer MOS transistor M1 is turned off, and the charge generation amount of PD1-1, PD2-1, PD3-1 due to light irradiation is read out as a luminance signal through the amplifier MOS transistor M4 and the vertical signal line 2. 8 is read out. Next, at timing t5, the reset MOS transistor M3 is turned on by the high level of φRes1, the potentials of FD1, FD2, and FD3 are set to the ground (GND), and FD1, FD2, and FD3 are turned off. At this time, the FD potential generation circuit 9 supplies GND to the vertical signal line 2 by the high level of φVR1 and the low level of φVR2.

  Next, at the timing t6, the noise level and the luminance signal stored in the readout circuit 8 are read out by the horizontal scanning circuit 3, and are sent to the main amplifier 17 through the noise level horizontal signal line 16 and the luminance signal horizontal signal line 6, respectively. Sent. At this time, although not shown, pulses are sequentially sent from the horizontal scanning circuit 3 to the plurality of readout circuits 8, and the luminance signal and the noise level are read out sequentially from the left column. The main amplifier 17 subtracts the noise level input from the noise level horizontal signal line 16 from the luminance signal input from the luminance signal horizontal signal line 6 and sends a true luminance signal to the external signal terminal 19 for one row. The eye scan ends.

  The second row is scanned in the same manner as the first row except that the transfer MOS transistor M2 is turned on during the timing period t7. That is, in order to select the second row, the transfer MOS transistor M2 is turned on by the high level of φTX2, and the charge stored in the PD1-2 by light irradiation is transferred to the FD1. At the same time, charges accumulated in PD2-2 and PD3-2 by light irradiation are transferred to FD2 and FD3, respectively.

  In the third row, φRes2 is set to high level at timing t8 to turn on the reset MOS transistor M5 and activate the potentials of the FDs for the third row and the fourth row to VRH. At this time, since φRes1 is at a low level, the reset MOS transistor M3 is off, so that the potentials of the FDs for the first row and the second row remain at GND. Similarly, reset MOS transistors in rows other than those for the third row and the fourth row are off, so that the potential of the FD in these rows remains at GND.

  By repeating these scans for all rows, one frame of luminance signal is read out. In the first embodiment, the capacitor 7 is attached to the gate electrode of the MOS transistor 10 at the final stage of the load current source. The capacitor 7 is provided for each vertical signal line 2 but can be manufactured by the same process as that for forming the MOS transistor, so that the cost is low. In the first embodiment, the FD potential is supplied by the vertical signal line 2. However, since the capacitor 7 is added, the potential fluctuation during signal transfer is small.

  In the present embodiment, a capacitor 7 electrically connected to the gate electrode of the MOS transistor 10 at the final stage of the load current source disposed in the peripheral circuit region is formed. The MOS transistor 10 at the final stage is connected to the vertical signal line 2 from which a signal is output from the pixel region. Accordingly, it is possible to provide a CMOS sensor that can capture a high-quality image while minimizing fluctuations in the potential of the vertical signal line 2.

(Second Embodiment)
FIG. 5 is a circuit diagram showing a peripheral circuit region of the solid-state imaging device according to the second embodiment. In the figure, reference numeral 20 denotes an FD potential supply line, and other reference numerals are the same as those of the parts described previously. In the first embodiment, the FD potential control is performed via the vertical signal line 2. In the second embodiment, the FD potential control is performed via the FD potential supply line 20. In the present embodiment, the FD potential is supplied from the FD potential supply line 20 that runs in the vertical direction. Similarly to the first embodiment, the capacitor 7 is attached to the gate electrode of the MOS transistor 10 at the final stage of the load current source. The capacitor 7 is provided for each vertical signal line 2.

  FIG. 6 is a circuit diagram illustrating a pixel region and a vertical scanning circuit according to the second embodiment. The reference numerals in the figure are the same as the parts described previously. In the second embodiment, the drains of the reset MOS transistors M 3 and M 5 in the pixel region are connected to the FD potential supply line 20. The drain of the amplifier MOS transistor M 4 in the pixel region is connected to the FD potential supply line 20. This is because the FD potential supply line 20 also supplies the power supply voltage (VDD) of the amplifier MOS transistor M4.

  The driving of the second embodiment will be described using the driving timing chart of FIG. ΦRes 1, φTX 1, φTX 2, φRes 2, and φVFD in the drawing represent the timing of the voltage of the wiring that leads to the pixel region 1 in FIG. 6, and the wiring positions are described in FIG. φVFD is the potential of the FD potential supply line 20.

  First, scanning of the first row will be described. At timing t1, the reset MOS transistor M3 is turned on by the high level of φRes1, the potential of FD1 is set to VDD, and FD1, FD2, and FD3 are activated. At this time, φVFD is the power supply voltage (VDD). Next, at timing t2, the noise levels of FD1, FD2, and FD3 are read out to the readout circuit 8 through the amplifier MOS transistor M4 and the vertical signal line 2 by driving in the signal readout circuit 8. Next, at the timing t3, the transfer MOS transistor M1 is turned on by the high level of φTX1, and the charge accumulated in the PD1-1 due to light irradiation is transferred to the FD1. At the same time, charges stored in PD2-1 and PD3-1 by light irradiation are transferred to FD2 and FD3, respectively. Next, at timing t4, the transfer MOS transistor M1 is turned off, and the charge generation amount of PD1-1, PD2-1, PD3-1 due to light irradiation is read out as a luminance signal through the amplifier MOS transistor M4 and the vertical signal line 2. 8 is read out. Next, at timing t5, the reset MOS transistor M3 is turned on by the high level of φRes1, the potentials of FD1, FD2, and FD3 are set to the ground (GND), and FD1, FD2, and FD3 are turned off. At this time, φVFD is the ground (GND).

  Next, at the timing t6, the noise level and the luminance signal stored in the readout circuit 8 are read out by the horizontal scanning circuit 3, and are sent to the main amplifier 17 through the noise level horizontal signal line 16 and the luminance signal horizontal signal line 6, respectively. Sent. At this time, although not shown, pulses are sequentially sent from the horizontal scanning circuit 3 to the plurality of readout circuits 8, and the luminance signal and the noise level are read out sequentially from the left column. The main amplifier 17 subtracts the noise level input from the noise level horizontal signal line 16 from the luminance signal input from the luminance signal horizontal signal line 6 and sends a true luminance signal to the external signal terminal 19 for one row. The eye scan ends.

  The second row is scanned in the same manner as the first row except that the transfer MOS transistor M2 is turned on during the timing period t7. That is, in order to select the second row, the transfer MOS transistor M2 is turned on by the high level of φTX2, and the charge stored in the PD1-2 by light irradiation is transferred to the FD1. At the same time, charges accumulated in PD2-2 and PD3-2 by light irradiation are transferred to FD2 and FD3, respectively.

  In the third row, φRes2 is set to high level at timing t8 to turn on the reset MOS transistor M5 and activate the potentials of the FDs for the third row and the fourth row to the power supply voltage (VDD). . At this time, since φRes1 is at a low level, the reset MOS transistor M3 is off, and the potentials of the FDs for the first row and the fourth row remain at ground (GND). Similarly, reset MOS transistors in rows other than those for the third row and the fourth row are turned off, so that the potential of the FD in these rows remains at the ground (GND).

  By repeating these scans for all rows, one frame of luminance signal is read out.

(Third embodiment)
In the third embodiment of the present invention, the capacitor 7 is attached to the gate electrode of the MOS transistor 10 at the final stage of the load current source. One capacitor 7 is provided for every two vertical signal lines 2. Other circuits and driving methods are the same as those in the first embodiment.

(Fourth embodiment)
In the fourth embodiment of the present invention, the capacitor 7 is attached to the gate electrode of the MOS transistor 10 at the final stage of the load current source. One capacitor 7 is provided for every four vertical signal lines 2. Other circuits and driving methods are the same as those in the first embodiment.

(Fifth embodiment)
In the fifth embodiment of the present invention, there are one FD, reset MOS transistor, and amplifier MOS transistor in four pixels (four photodiodes). Each pixel (each photodiode) has one transfer MOS transistor. For this reason, the number of transistors can be reduced.

(Sixth embodiment)
In the sixth embodiment of the present invention, a switch is added to the load current source of the first embodiment. FIG. 9 is a circuit diagram showing a peripheral circuit region of the sixth embodiment. In the figure, 21 is a load current source switch, 22 is a gate line of the load current source switch, and the other part numbers are as described above. The usage of the load current source switch 21 will be described using the drive timing chart of FIG. The gate line of the load current source switch in FIG. 9 is turned on / off at the timing of φPVL in FIG. That is, the pixel selection time is turned on, but other times are turned off.

  By this driving, it is possible to stabilize the potential of the vertical signal line 2 when necessary by the effect of the capacitor 7 while preventing current from flowing through the load current source final stage MOS transistor 10 when it is not necessary.

(Embodiment applied to a digital camera)
FIG. 8 is a circuit block diagram showing a configuration example when the solid-state imaging device described in the first to sixth embodiments of the present invention is applied to a camera (imaging system). This embodiment shows an example in which the solid-state imaging device of the above-described embodiment is applied to a camera. The solid-state imaging device of the above embodiment corresponds to the solid-state imaging element 54. A shutter 51 is provided in front of the photographic lens (optical system) 52 and controls exposure. The amount of light is controlled by the diaphragm 53 as necessary, and the photographing lens 52 forms an image of light on the solid-state image sensor 54. The imaging signal output from the solid-state imaging device 54 is processed by the signal processing circuit 55 and converted from an analog signal to a digital signal by the A / D converter 56. The output digital signal is further processed by the signal processing unit 57. The processed digital signal is stored in the memory unit 60 or sent to an external device through the external I / F unit 63. The solid-state imaging device 54, the imaging signal processing circuit 55, the A / D conversion unit 56, and the signal processing unit 57 are controlled by a timing generation unit 58, and the entire system is controlled by an overall control unit / calculation unit 59. In order to record an image on the recording medium 62, the output digital signal is recorded through the recording medium control I / F unit 61 controlled by the overall control unit / calculation unit 59.

  As described above, according to the first to sixth embodiments, a vertical signal is applied to the pixel region 1 including the amplifier MOS transistor that amplifies the photoelectrically converted charge and at least the source electrode of the amplifier MOS transistor. In a photoelectric conversion device having a peripheral circuit region including load current sources 4 and 10 electrically connected via a line 2, there is a final-stage MOS transistor 10 constituting a load current source. The gate electrode of the MOS transistor 10 and one electrode of the capacitor 7 are electrically connected to each vertical signal line 2. The other electrode of the capacitor 7 is in the semiconductor substrate.

  By providing the capacitor 7, it is possible to prevent fluctuations in the potential of the vertical signal line 2 connected to the source electrode of the amplifier MOS transistor M4 that amplifies the photoelectrically converted charge in the pixel region 1. That is, it is possible to provide a CMOS sensor that can capture a high-quality image while minimizing potential fluctuations caused by external noise on the vertical signal line 2.

  The photoelectric conversion device of this embodiment can be used as an imaging device for imaging such as a still camera or a video camera.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

1 is a circuit diagram showing a peripheral circuit region of a solid-state imaging device according to a first embodiment of the present invention. 1 is a circuit diagram illustrating a pixel region and a vertical scanning circuit according to a first embodiment of the present invention. 3A and 3B are a plan view and a cross-sectional view of the load power source final stage MOS transistor, the load current source cutoff MOS transistor, and the capacitor according to the first embodiment of the present invention. It is a drive timing chart of the 1st embodiment of the present invention. It is a circuit diagram which shows the peripheral circuit area | region of the solid-state imaging device by the 2nd Embodiment of this invention. It is a circuit diagram which shows the pixel area | region and vertical scanning circuit of the 2nd Embodiment of this invention. It is a drive timing chart of the 2nd Embodiment of this invention. It is a circuit block diagram which shows the structural example of the camera (imaging system) by the 4th Embodiment of this invention. It is a circuit diagram which shows the peripheral circuit area | region of the solid-state imaging device by the 6th Embodiment of this invention. It is a drive timing chart of a 6th embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel region 2 Vertical signal line 3 Horizontal scanning circuit 4 Load current source structure circuit 5 Common gate line 6 of current source final stage MOS transistor Luminance signal horizontal signal line 7 Capacitor 8 Signal readout circuit 9 FD potential generation circuit 10 Load current source Final stage MOS transistor 11 Vertical scanning circuit 12 Load current source cutoff MOS transistor 13 n-type silicon substrate 14 p-type well 15 n-type region 16 noise level horizontal signal line 17 main amplifier 18 oxide film 19 external signal terminal 20 FD potential supply line

Claims (12)

A field effect transistor for an amplifier for amplifying the photoelectrically converted charge;
A signal line connected to a source electrode of the amplifier field effect transistor;
A field effect transistor constituting a load of a current source connected to the signal line;
And a capacitor connected to a gate electrode of a field effect transistor constituting a load of the current source.   The solid-state imaging device according to claim 1, wherein the capacitor is formed of a MOS structure. A plurality of field effect transistors constituting the amplifier field effect transistor, the signal line and the load of the current source are arranged,
3. The solid-state imaging device according to claim 1, wherein the capacitor is connected to a gate electrode of a field effect transistor that constitutes a load of the current source for each signal line.   The solid-state imaging device according to claim 1, wherein the capacitor has a capacitance of 1 to 100 fF.   The solid-state imaging device according to claim 1, wherein a switch is provided between the signal line and a field effect transistor that constitutes a load of the current source. Furthermore, it has a pixel capacitor that accumulates charges and is connected to the gate electrode of the amplifier field effect transistor,
5. The solid-state imaging device according to claim 1, wherein the potential control of the pixel capacitor is performed through the signal line. 6. Furthermore, it has a pixel capacitor that accumulates charges and is connected to the gate electrode of the amplifier field effect transistor,
The solid-state imaging device according to claim 1, wherein the potential control of the pixel capacitor is performed through a supply line connected to a drain electrode of the amplifier field effect transistor. A plurality of field effect transistors constituting the amplifier field effect transistor, the signal line and the load of the current source are arranged,
3. The solid-state imaging device according to claim 1, wherein one capacitor is connected to a gate electrode of a field effect transistor that constitutes a load of the current source for each of the two signal lines. A plurality of field effect transistors constituting the amplifier field effect transistor, the signal line and the load of the current source are arranged,
3. The solid-state imaging device according to claim 1, wherein one capacitor for each of the four signal lines is connected to a gate electrode of a field effect transistor constituting a load of the current source. Furthermore, photoelectric conversion means for generating electric charge by photoelectric conversion,
A pixel capacitor that accumulates charge and is connected to a gate electrode of the amplifier field effect transistor;
The solid-state imaging device according to claim 1, further comprising a transfer unit configured to transfer a charge of the photoelectric conversion unit to the pixel capacitor. The pixel capacitor and the amplifier field effect transistor are provided one for each of the plurality of photoelectric conversion means,
The solid-state imaging device according to claim 10, wherein one transfer unit is provided for each photoelectric conversion unit. The solid-state imaging device according to any one of claims 1 to 11,
An optical system for imaging light onto the solid-state imaging device;
An imaging system comprising: a signal processing circuit that processes an output signal from the solid-state imaging device.

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