JP4946286B2 - Thin film transistor array, image display device using the same, and driving method thereof - Google Patents

Thin film transistor array, image display device using the same, and driving method thereof Download PDF

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JP4946286B2
JP4946286B2 JP2006245316A JP2006245316A JP4946286B2 JP 4946286 B2 JP4946286 B2 JP 4946286B2 JP 2006245316 A JP2006245316 A JP 2006245316A JP 2006245316 A JP2006245316 A JP 2006245316A JP 4946286 B2 JP4946286 B2 JP 4946286B2
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pixel electrode
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transistor array
semiconductor layer
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守 石▲崎▼
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凸版印刷株式会社
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P20/00Technologies relating to chemical industry
    • Y02P20/50Improvements relating to the production of products other than chlorine, adipic acid, caprolactam, or chlorodifluoromethane, e.g. bulk or fine chemicals or pharmaceuticals
    • Y02P20/52Improvements relating to the production of products other than chlorine, adipic acid, caprolactam, or chlorodifluoromethane, e.g. bulk or fine chemicals or pharmaceuticals using catalysts, e.g. selective catalysts

Description

  The present invention relates to a thin film transistor array used in a high-quality image display device, an image display device using the same, and a driving method thereof.

  Based on the transistor and integrated circuit technology based on the semiconductor itself, amorphous silicon (a-Si) and polysilicon (p-Si) thin film transistors (Thin Film Transistors: TFTs) are manufactured on a glass substrate. Has been applied. An example of a conventional thin film transistor array is shown in FIG. The outline of the manufacturing method of the display device will be described. First, the gate electrode 2 and the capacitor electrode 10 are formed on the insulating substrate 1 by metal film formation, photolithography, and etching. Next, the SiNx insulating layer 3 and the semiconductor layer 6 made of amorphous silicon (a-Si) are formed by plasma CVD. A thin n + doping layer 6 'is formed on the top of amorphous silicon (a-Si). Then, the semiconductor layer 6 made of a-Si is patterned into an island shape by photolithography. Subsequently, an ITO (Indium Tin Oxide) film is formed as the pixel electrode 8 and patterned into a predetermined shape by photolithography etching. Further, a metal film for the source electrode 4 and the drain electrode 5 is formed, patterned by photolithography and etching, and further the n + -Si layer in the channel portion is etched. Thus, the current semiconductor manufacturing process makes full use of a vacuum process and a large number of photo processes, and the apparatus becomes large, so that the manufacturing cost is high.

An image display device such as a liquid crystal display or an electrophoretic display is manufactured using such a thin film transistor. As a driving method of these image display devices, the same voltage as that of the counter electrode is applied to the capacitor electrode, and the voltage is set to a value close to the average value of the source voltage waveform, which is lower than the maximum value of the source voltage. The value is higher than the minimum value (see FIGS. 21 and 22, for example, Non-Patent Document 1). Here, Vc is a capacitor voltage, Vcom is a counter electrode voltage, Vs is a source voltage, and Vg is a gate voltage.

  Recently, TFTs using oxide semiconductors and organic semiconductors have appeared, and the formation temperature of the semiconductor layer can be lowered from room temperature to about 200 ° C., so that it is possible to use a plastic substrate, and a lightweight and flexible display. Is expected to be obtained at low cost.

  In general, a semiconductor is patterned only in a channel portion between a source and a drain. However, when an organic semiconductor is used, it is difficult to pattern the semiconductor. This is because an organic semiconductor easily dissolves or swells in an organic solvent and is easily deteriorated by ultraviolet light. Therefore, even if an attempt is made to provide a semiconductor pattern by photolithography, the pattern disappears or the semiconductor is damaged. As a method that does not use photolithography, for example, the dispenser method is simple, but the accuracy is poor, and the semiconductor material ink greatly exceeds the desired semiconductor pattern and spreads in a circular shape. It may reach the electrode. Although various other printing methods are possible, if a large pattern is warned against misalignment, the semiconductor pattern may reach the wiring part of the source electrode or the pixel electrode, or the semiconductor patterns may be connected. May end up. Furthermore, it is strongly desired to form not only an organic semiconductor but also an oxide semiconductor in a process that does not require photolithography in order to simplify the process.

In addition, as described above, when a semiconductor is formed other than the desired channel portion due to poor patterning, the semiconductor extends to the wiring portion of the source electrode and the pixel electrode, or the semiconductor patterns are connected to each other. There is a problem that crosstalk occurs in a display image of an image display device provided with a medium (FIG. 19). Furthermore, there is a problem in that crosstalk occurs in the same manner even in a configuration in which the entire thin film transistor is provided in a semiconductor only in a process that does not require photolithography.

Shoichi Matsumoto: "Liquid Crystal Display Technology—Active Matrix LCD" p. 71 Figure 2.15

  The present invention has been made in view of the state of the related art, and even when the semiconductor is formed larger than a desired pattern, or even in a configuration in which the semiconductor is provided in almost the entire thin film transistor, the crosstalk is achieved. It is an object of the present invention to provide a thin film transistor array, an image display device, and a driving method for obtaining a good display with no problem.

According to a first aspect of the present invention, a gate electrode and a capacitor electrode are provided on an insulating substrate, a source electrode, a drain electrode, and a pixel electrode connected to the drain electrode are disposed through a gate insulating film, and A thin film transistor array in which a semiconductor layer is disposed at least between the source electrode and the drain electrode, and in a planar view, at least in the region where the semiconductor layer is disposed, the capacitor electrode is more than the pixel electrode. And the pixel electrode is included in the capacitor electrode.

The invention described in claim 2, on the TFT array according to claim 1, further wherein an interlayer insulating film having an opening on the pixel electrode, an upper pixel electrode connected to the pixel electrode through the opening The thin film transistor array is provided.

According to a third aspect of the present invention, a gate electrode and a capacitor electrode are provided on an insulating substrate, a source electrode, a drain electrode, and a pixel electrode are disposed via a gate insulating film, and at least a semiconductor layer is the source electrode. wherein disposed between the drain electrode, which and is connected to the interlayer insulating film having an opening on the upper and the pixel electrode of the drain electrode thereon, the pixel electrode and the drain electrode through the opening and A thin film transistor array provided with an upper pixel electrode, wherein the capacitor electrode is larger than the pixel electrode in at least the region where the semiconductor layer is disposed in a planar arrangement, and the pixel electrode is the capacitor The thin film transistor array is included in an electrode.

The invention according to claim 4, and a gate electrode and a capacitor electrode on an insulating substrate, a gate insulating film formed thereon, the semiconductor layer disposed thereon, and on the said semiconductor layer, or A thin film transistor array in which a source electrode, a drain electrode, and a pixel electrode connected to the drain electrode are disposed on the gate insulating film under the semiconductor layer, wherein at least the semiconductor layer is arranged in a plan view In the arranged region, the capacitor electrode is larger than the pixel electrode, and the pixel electrode is included in the capacitor electrode.

According to a fifth aspect of the invention, on the thin film transistor array according to the fourth aspect, an interlayer insulating film having an opening on the pixel electrode, and an upper pixel electrode connected to the pixel electrode through the opening The thin film transistor array is provided.

The invention according to claim 6, and a gate electrode and a capacitor electrode on an insulating substrate, a gate insulating film formed thereon, the semiconductor layer disposed thereon, and on the said semiconductor layer, or the source electrode and the drain electrode and the pixel electrode on the gate insulating film under the semiconductor layer is disposed, and an interlayer insulating film having an opening over the pixel electrode and on said drain electrode thereon, the A thin film transistor array provided with an upper pixel electrode connected to the drain electrode and the pixel electrode through an opening , wherein, in a planar view, at least in the region where the semiconductor layer is disposed, the capacitor electrode is The thin film transistor array is larger than the pixel electrode, and the pixel electrode is included in the capacitor electrode.

The invention according to claim 7 has a source electrode, a drain electrode, and a pixel electrode connected to the drain electrode on an insulating substrate, and a semiconductor layer is disposed at least between the source electrode and the drain electrode. It is, and through the gate insulating film having an opening over the pixel electrode, is disposed the gate electrode and the capacitor electrode, and an interlayer insulating film having an opening over the pixel electrode thereon, via said opening wherein a thin-film transistor array pixel electrode and connected to the upper pixel electrode is provided Te, in a plan view arrangement, at least the semiconductor layer is disposed area, larger than the capacitor electrode is the pixel electrode, The thin film transistor array is characterized in that the pixel electrode is included in the capacitor electrode.

The invention according to claim 8, and a source electrode and a drain electrode and a pixel electrode on an insulating substrate, and the semiconductor layer is disposed between the drain electrode and at least the source electrode and the drain electrode via a gate insulating film having an opening on the upper and the pixel electrode, is disposed the gate electrode and the capacitor electrode, and an interlayer insulating film having an opening on the upper and the pixel electrode of the drain electrode thereon A thin film transistor array provided with an upper pixel electrode in which the drain electrode and the pixel electrode are connected via the opening , and in a planar view, at least in the region where the semiconductor layer is disposed, A thin film transistor, wherein a capacitor electrode is larger than the pixel electrode, and the pixel electrode is included in the capacitor electrode. It is an array.

According to a ninth aspect of the present invention, a semiconductor layer is provided over an insulating substrate, and the source electrode, the drain electrode, and the drain electrode are formed on the semiconductor layer or on the gate insulating film below the semiconductor layer. are arranged pixel electrodes connected, and through the gate insulating film having an opening over the pixel electrode, is disposed the gate electrode and the capacitor electrode, an interlayer insulating film having an opening and on the pixel electrode, A thin film transistor array provided with an upper pixel electrode connected to the pixel electrode through the opening, wherein the capacitor electrode is disposed in the pixel electrode at least in a region where the semiconductor layer is disposed in a plan view. A thin film transistor array, wherein the pixel electrode is included in the capacitor electrode.

The invention described in claim 10 has a semiconductor layer on an insulating substrate, and the semiconductor layer on or source electrode and the drain electrode and the pixel electrode under are arranged, and the pixel electrode and on said drain electrode via a gate insulating film having an opening on the top, is disposed the gate electrode and the capacitor electrode, and an interlayer insulating film having an opening on the upper and the pixel electrode of the drain electrode thereon, the opening a thin film transistor array in which the upper pixel electrode is provided which is connected to the pixel electrode and the drain electrode through, in a plan view arrangement, at least the semiconductor layer is disposed region, said capacitor electrode is the pixel The thin film transistor array is larger than an electrode and the pixel electrode is included in the capacitor electrode.

An eleventh aspect of the invention is an image display device in which a display medium is provided between the thin film transistor array according to any of the first to tenth aspects and a counter substrate having a counter electrode.

A twelfth aspect of the present invention is the image display device driving method according to the eleventh aspect , wherein a semiconductor of the thin film transistor array is an n-channel, and a voltage applied to the capacitor electrode is applied to the source electrode. The driving method is characterized by being lower than the lowest value of the voltage waveform to be generated.

A thirteenth aspect of the present invention is the image display device driving method according to the eleventh aspect , wherein a semiconductor of the thin film transistor array is a p-channel, and a voltage applied to the capacitor electrode is applied to the source electrode. The driving method is characterized by being higher than the maximum value of the voltage waveform to be generated.

According to the present invention, in a thin film transistor array having a structure in which a capacitor electrode includes a pixel electrode in a planar view, a voltage that prevents current flowing from the source electrode to the pixel electrode is applied to the capacitor electrode. An image display device capable of reducing the current and suppressing crosstalk can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings used below, the scale is not accurately drawn for easy understanding.

  As a result of intensive studies on the above-described crosstalk (FIG. 19), the semiconductor layer 6 is in contact with the source electrode 4 and the pixel electrode 8 in a portion where the gate electrode 2 does not exist in the planar arrangement. Found what happens when. In this portion, a current (off current) that cannot be controlled by the gate voltage flows from the source electrode 4 to the pixel electrode 8, so that crosstalk occurs. For example, as shown in FIG. 18, the semiconductor layer 6 is formed by a dispenser method or the like, and the semiconductor layer 6 extends not only in the vicinity between the desired source electrode 4 and drain electrode 5, but also greatly extends in a circular shape, This corresponds to the case where the semiconductor layer 6 is in contact with the source electrode 4 and the pixel electrode 8 as in the cross section of I ″ -I ′ ′ ′ in the portion where the gate electrode 2 does not exist.

  Therefore, we conceived that the capacitor electrode 10 has a role similar to that of the gate electrode 2 and completed the present invention. That is, in a planar arrangement, the capacitor electrode 10 is made larger than the pixel electrode 8 and includes the pixel electrode 8 in at least the region where the semiconductor layer 6 is arranged (FIGS. 1 and 3). . Here, including means that the pixel electrode does not protrude from the capacitor electrode in a plan view arrangement, that is, when viewed from above the thin film transistor. Using the thin film transistor having this structure, the capacitor voltage is set to a voltage lower than the minimum value of the source voltage waveform if the thin film transistor is n-channel, and to a voltage higher than the maximum value of the source voltage waveform if the thin film transistor is p-channel. To do. By doing so, the voltage waveform of the pixel electrode 8 is a waveform close to the source voltage waveform, so that the potential of the capacitor electrode 10 causes the current to flow into and out of the pixel electrode 8 by the same action as the potential of the gate electrode 2. The state is limited, and the off-state current can be kept small.

That is, in the same manner as the carrier in the semiconductor connecting the source electrode 4 and the drain electrode 5 is controlled by the potential of the gate electrode 2, the pixel on the capacitor electrode 10 is arranged in plan view by the potential of the capacitor electrode 10. The semiconductor carriers in the portion corresponding to the portion larger than the electrode 8 are controlled, so that the current flowing from the source electrode 4 to the pixel electrode 8 is restricted, and the off-current can be kept small. Note that the sealing layer 12 may be provided on the semiconductor layer 6 formed between the source electrode 4 and the drain electrode 5.

  For example, in the case of n-channel, it is not necessarily better that the capacitor voltage is lower than the lowest value of the source voltage waveform. Since (the maximum value of the source voltage waveform−capacitor voltage) is the maximum voltage applied to the capacitor, this must be equal to or lower than the withstand voltage of the capacitor. The same applies to the p-channel, and the higher the capacitor voltage is than the highest value of the source voltage waveform, the better. Since (capacitor voltage-minimum value of the source voltage waveform) is the maximum voltage applied to the capacitor, this must be equal to or lower than the withstand voltage of the capacitor.

  In order to increase the aperture ratio of the pixel (the area in which display can be changed divided by the pixel area (vertical pitch of pixel × horizontal pitch)), an interlayer insulating film having an opening in the pixel electrode portion on the thin film transistor 7 and an upper pixel electrode 11 connected to the pixel electrode in the opening can be provided (FIGS. 2 and 15). Alternatively, the upper pixel electrode 11 may be connected to the pixel electrode 8 and the drain electrode 5 via the opening of the interlayer insulating film 7, and the pixel electrode 8 may be connected to the drain electrode 5 via the upper pixel electrode 11. (FIGS. 4 and 14). Note that a sealing layer 12 may be provided between the interlayer insulating film 7 and the semiconductor layer 6.

  The image display device 60 of the present invention has a structure in which a display medium 41 is sandwiched between the thin film transistor array 50 and the counter substrate 21 having the counter electrode 22 (FIG. 9). Examples of the display medium 41 include a liquid crystal and an electrophoretic medium. That is, as the image display device 60, a liquid crystal display, an electrophoretic display, or the like can be configured.

  According to the driving method of the present invention, the capacitor voltage (Vc) is set to a voltage lower than the minimum value of the source voltage waveform (Vs) if the thin film transistor is n-channel (FIG. 11), and the source voltage waveform if the thin film transistor is p-channel. A characteristic is that the voltage is higher than the maximum value of (Fig. 12). Usually, since the counter voltage (Vcom) is a voltage between the maximum value and the minimum value of the source voltage waveform, a voltage different from that of the counter electrode 22 is necessarily applied to the capacitor electrode 10.

  In the thin film transistor array of the present invention, the semiconductor layer 6 is preferably made of an oxide semiconductor or an organic semiconductor. Oxide semiconductors and organic semiconductors do not require the doping process required for silicon, and the process is simple. In addition, since low temperature film formation is possible, a thin film transistor can be formed over a plastic substrate.

  In the thin film transistor array according to the present invention, a gate / capacitor electrode, a gate insulating film, a source / drain / pixel electrode, and a bottom gate / bottom contact structure in which a semiconductor layer is laminated in this order (FIG. 1). , A gate insulating film, a semiconductor layer, and a bottom gate / top contact structure (FIG. 3) in which source / drain / pixel electrodes are laminated in this order. Further, the structure in which the upper pixel electrode is provided through the interlayer insulating film may be a structure in which the interlayer insulating film and the upper pixel electrode are stacked on the two structures (FIGS. 2, 4, 14, and 15). A top gate / bottom contact structure in which a source / drain / pixel electrode, a semiconductor layer, a gate insulating film, a gate / capacitor electrode, an interlayer insulating film, and an upper pixel electrode are sequentially stacked on the substrate may be used. Alternatively, a top gate / top contact structure (FIG. 17) in which a semiconductor layer, a source / drain / pixel electrode, a gate insulating film, a gate / capacitor electrode, an interlayer insulating film, and an upper pixel electrode are stacked in this order. However, in the case of the bottom gate, an opening may be formed in the interlayer insulating film in order to connect the upper pixel electrode to the pixel electrode, but in the case of the top gate, an opening is also required in the gate insulating film.

  In the thin film transistor array of the present invention, as the insulating substrate 1, in addition to quartz and glass, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polyimide (PI), polyetherimide (PEI) ), Polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE), polypropylene (PP), nylon (Ny), and other plastics. These plastic substrates have the advantage of being strong even in the form of a thin film, light and not easily broken.

  The gate electrode 2, the capacitor electrode 10, the source electrode 4, the drain electrode 5, the pixel electrode 8, and the upper pixel electrode 11 have good conductivity such as Al, Cr, Au, Ag, Cu, Ti, Ni, Pd, and Pt. A metal film or a transparent conductive film such as ITO can be used. These conductive films can be formed by sputtering or vapor deposition, but can also be formed by printing and baking metal ink.

  Here, the drain electrode and the pixel electrode may be directly connected or indirectly connected via the upper pixel electrode. In the case where the drain electrode and the pixel electrode are directly connected, the drain electrode refers to a portion protruding so as to face the source electrode. The source electrode refers to a portion including a portion protruding so as to face the drain electrode and a wiring portion continuous therewith.

As the gate insulating film 3, an inorganic material such as SiO 2 , Al 2 O 3 , SiN, or SiON, or an organic material such as polyvinyl phenol, epoxy, polyimide, or acrylic can be used. Usually, a film of an inorganic material can be formed using a sputtering method or a vapor deposition method, and an organic material can be formed using a spin coating method or a printing method. As a method of forming an opening in the gate insulating film, a method by photolithography + etching, a method of patterning by exposure / development using a photosensitive resin for the gate insulating film itself, a method of forming the gate insulating film by printing, and the like are possible. It is.

Examples of the semiconductor constituting the semiconductor layer 6 include InGaZnO-based, InZnO-based, ZnGaO-based, InGaO-based, In 2 O 3 , ZnO, SnO 2 , oxide semiconductors such as mixtures thereof, polythiophene derivatives, polyphenylene vinylene derivatives, Organic semiconductors such as polythienylene vinylene derivatives, polyallylamine derivatives, polyacetylene derivatives, acene derivatives, oligothiophene derivatives, and the like can be used.

The oxide semiconductor layer can be obtained by sputtering or laser ablation. The organic semiconductor layer can be obtained by vapor deposition as well as by applying and baking the raw materials. A printing method is effective as a method for efficiently using raw materials. Specifically, formation by an ink jet or a dispenser is suitable.

  The interlayer insulating film 7 can directly form a pattern with an opening by a method of forming by exposure / development using a photosensitive resin itself or a method of forming by screen printing.

  In the present invention, among the source / drain electrodes of the thin film transistor, the one to which a voltage is to be applied from the outside is called the source electrode 4 and the one connected to the pixel electrode 8 is called the drain electrode 5. Is for convenience and can be called in reverse.

Example 1
A thin film transistor array having the structure shown in FIG. 1 was fabricated according to the process diagram shown in FIG. As the insulating substrate 1, polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and after depositing Al with a thickness of 50 nm, a gate electrode 2 and a capacitor electrode 10 were formed by photolithography and etching (see FIG. 5A). Although only one pixel is shown in FIG. 1, it is actually an array in which a large number are arranged in a matrix.

  Next, SiON was formed by reactive sputtering to form the gate insulating film 3 (see FIG. 5B). The thickness was 500 nm. Subsequently, Cr and Pd were continuously sputtered as the source electrode 4, the drain electrode 5, and the pixel electrode 11, and formed by photolithography and etching (see FIG. 5C). The channel length is 30 μm and the channel width is 1000 μm.

  Then, a chloroform solution of pentacene was applied by a dispenser in the vicinity of the gap (channel portion) between the source electrode 4 and the drain electrode 5, and the semiconductor layer 6 was formed by drying (see FIG. 5D). Finally, CYTOP, which is a fluororesin, was screen-printed as the sealing layer 12 in the vicinity of the gap between the source electrode 4 and the gate electrode 5 (FIG. 5E).

  Thus, the thin film transistor array shown in FIG. 1 was obtained. This thin film transistor is a p-channel. By keeping the potential of the capacitor electrode at +5 V, which is higher than the source voltage and the drain voltage, the off-state current of the thin film transistor array could be suppressed to 10 pA or less. However, the measurement conditions were a source voltage = 0V, a drain voltage = −40V, and a gate voltage = + 20V to −40V.

(Example 2)
6 was continuously performed on the thin film transistor array produced in Example 1 to produce the thin film transistor array in FIG. First, a photosensitive resin was formed on the entire surface, and an interlayer insulating film 7 was formed by exposure and development (see FIG. 6F). The thickness was 10 μm and the opening diameter was 100 μm. Next, Al was vapor-deposited, photolithography, and etched as the upper pixel electrode 8 (see FIG. 6G). Through these steps, the characteristics of the thin film transistor were hardly changed from the state of Example 1.

(Example 3)
An image display device 60 shown in FIG. 9 was produced using the thin film transistor array 50 produced in Example 1 and liquid crystal as the display medium 41. The details are shown in FIG. First, the counter electrode 22 (ITO) was formed on the PET to form the counter substrate 21. Next, JSR optomer AL was applied as the alignment film 31 to the thin film transistor array 50 and the counter substrate 21, and a rubbing process was performed. Then, Sekisui Chemical Photorec S was dispensed around the thin film transistor array as a sealant 32, glass beads 33 and TN liquid crystal 34 were dropped, and the counter substrate 21 was laminated and bonded together in a vacuum. Thereafter, UV irradiation was performed from the counter substrate 21 side in the atmosphere to cure the sealing agent 32, heat treatment was performed, and then the polarizing plate 35 was bonded. When the image display device thus manufactured was driven with the drive waveform shown in FIG. 12, a good image without crosstalk was obtained as shown in FIG. In addition, when the drive waveform of FIG. 22 was used, crosstalk was observed.

Example 4
Using the thin film transistor 50 of Example 2, an image display device 60 was manufactured by the same process as that of Example 3. When driven with the drive waveform of FIG. 12, a display without crosstalk was obtained as in Example 3. In addition, when the drive waveform of FIG. 22 was used, crosstalk was observed.

(Example 5)
A thin film transistor array having the structure shown in FIG. 3 was fabricated according to the process diagram shown in FIG. As the insulating substrate 1, polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and after depositing Al with a thickness of 50 nm, a gate electrode 2 and a capacitor electrode 10 were formed by photolithography and etching (see FIG. 7A). Although only one pixel is shown in FIG. 3, it is actually an array in which a large number are arranged in a matrix.

Next, SiON was formed by reactive sputtering to form the gate insulating film 3 (see FIG. 7B). The thickness was 500 nm. Further, InGaZnO was formed by sputtering as the semiconductor layer 6. The thickness is 50 nm (see FIG. 7C).
Subsequently, Cr and Pd were continuously sputtered as the source electrode 4, the drain electrode 5, and the pixel electrode 11, and formed by photolithography and etching (see FIG. 7D). The channel length is 30 μm and the channel width is 100 μm.

 Finally, CYTOP, which is a fluororesin, was screen-printed as the sealing layer 12 in the vicinity of the gap between the source electrode 4 and the gate electrode 5 (FIG. 7E).

 In this way, the thin film transistor array shown in FIG. 3 was obtained. This thin film transistor is n-channel. By keeping the potential of the capacitor electrode at -5 V, which is lower than the source voltage and the drain voltage, the off-state current of this thin film transistor array could be suppressed to 10 pA or less. However, the measurement conditions were set such that the source voltage = 0V, the drain voltage = + 40V, and the gate voltage = −20V to + 40V.

(Example 6)
A thin film transistor array having the structure shown in FIG. 4 was fabricated according to the process chart shown in FIG. As the insulating substrate 1, polyethylene naphthalate (PEN) having a thickness of 125 μm was prepared, and after depositing Al with a thickness of 50 nm, a gate electrode 2 and a capacitor electrode 10 were formed by photolithography and etching (see FIG. 8A). Although only one pixel is shown in FIG. 4, it is actually an array in which a large number are arranged in a matrix.

Next, SiON was formed by reactive sputtering to form the gate insulating film 3 (see FIG. 8B). The thickness was 500 nm. Further, InGaZnO was formed by sputtering as the semiconductor layer 6. The thickness is 50 nm (see FIG. 8C).
Subsequently, Cr and Pd were continuously sputtered as the source electrode 4, the drain electrode 5, and the pixel electrode 11, and formed by photolithography and etching (see FIG. 8D). The channel length is 30 μm and the channel width is 100 μm.

 Further, CYTOP, which is a fluororesin, was screen-printed as the sealing layer 12 in the vicinity of the gap between the source electrode 4 and the gate electrode 5 (FIG. 8E).

  Then, a photosensitive resin was formed on the entire surface, and exposed and developed to form an interlayer insulating film 7 (see FIG. 8F). The thickness was 10 μm and the opening diameter was 100 μm. Next, Al was vapor-deposited, photolithography, and etched as the upper pixel electrode 8 (see FIG. 8G). The characteristics of the thin film transistor thus fabricated were the same as in Example 5.

(Example 7)
An image display device 60 shown in FIG. 9 was manufactured using the thin film transistor array 50 manufactured in Example 5 and liquid crystal as the display medium 41. The details are shown in FIG. First, the counter electrode 22 (ITO) was formed on the PET to form the counter substrate 21. Next, JSR optomer AL was applied as the alignment film 31 to the thin film transistor array 50 and the counter substrate 21, and a rubbing process was performed. Then, Sekisui Chemical Photorec S was dispensed around the thin film transistor array as a sealant 32, glass beads 33 and TN liquid crystal 34 were dropped, and the counter substrate 21 was laminated and bonded together in a vacuum. Thereafter, UV irradiation was performed from the counter substrate 21 side in the atmosphere to cure the sealing agent 32, heat treatment was performed, and then the polarizing plate 35 was bonded. When the image display device thus manufactured was driven with the drive waveform shown in FIG. 11, an image without crosstalk was obtained as in Example 3. Incidentally, when the drive waveform of FIG. 21 was used, crosstalk was observed.

(Example 8)
Using the thin film transistor 50 of Example 6, an image display device 60 was fabricated by the same process as in Example 7. When driven with the drive waveform of FIG. 11, a display without crosstalk was obtained as in Example 3. When driving with the driving waveform of FIG. 21, crosstalk was observed.

(Comparative Example 1)
The thin film transistor array shown in FIG. 18 was fabricated by the same process as in Example 1. In this case, since the pixel electrode 8 is larger than the capacitor electrode 10 in a plan view arrangement, the semiconductor layer 6 is in contact with both the source electrode 4 and the pixel electrode 8 in a portion where the gate electrode 2 is not provided. There is no means for preventing current flowing into the pixel electrode 8. Actually, the off current showed a large value of about 1 μA regardless of the voltage of the capacitor electrode 10. Further, in the liquid crystal display manufactured by using the same process as in Example 3, crosstalk was observed not only with the drive waveform of FIG. 22 but also with the drive waveform of FIG. 12 (FIG. 19).

It is a figure which shows an example of the thin-film transistor array concerning embodiment of this invention. It is a figure which shows the other example of the thin-film transistor array concerning embodiment of this invention. It is a figure which shows the other example of the thin-film transistor array concerning embodiment of this invention. It is a figure which shows the other example of the thin-film transistor array concerning embodiment of this invention. It is process drawing which shows the manufacturing process of the thin-film transistor array of FIG. FIG. 3 is a process diagram illustrating a manufacturing process of the thin film transistor array of FIG. 2. It is process drawing which shows the manufacturing process of the thin-film transistor array of FIG. FIG. 5 is a process diagram illustrating a manufacturing process of the thin film transistor array of FIG. 4. It is a figure which shows an example of the image display apparatus of this invention. It is a figure which shows the detail of the image display apparatus of this invention. It is a voltage waveform diagram which shows an example (in the case of n channel) of the drive method of this invention. It is a voltage waveform diagram which shows an example (in the case of p channel) of the drive method of this invention. It is a schematic diagram which shows the display state of the image display apparatus of this invention. It is a figure which shows the other structure of the thin-film transistor array of this invention. It is a figure which shows the other structure of the thin-film transistor array of this invention. It is a figure which shows the other structure of the thin-film transistor array of this invention. It is a figure which shows the other structure of the thin-film transistor array of this invention. It is a figure which shows the structure of the thin-film transistor array of a comparative example. It is a schematic diagram which shows the display state of the image display apparatus of a comparative example. It is a figure which shows the structure of the conventional thin-film transistor array. It is a voltage waveform diagram which shows an example (in the case of n channel) of the conventional drive method. It is a voltage waveform diagram which shows an example (in the case of p channel) of the conventional drive method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Gate electrode, 3 ... Gate insulating film, 4 ... Source electrode, 5 ... Drain electrode, 6 ... Semiconductor layer, 7 ... Interlayer insulating film , 8 ... Pixel electrode, 9 ... Interlayer insulating film, 10 ... Capacitor electrode, 11 ... Upper pixel electrode, 12 ... Sealing layer, 21 ... Counter substrate, 22 ... Counter electrode, 31 ... Alignment film, 32 ... Sealing agent, 33 ... Glass beads, 34 ... Liquid crystal, 35 ... Polarizing plate, 41 ... Display medium, 50 ... Thin film transistor array 60 ... Image display device

Claims (13)

  1.   A gate electrode and a capacitor electrode are provided on an insulating substrate, a source electrode, a drain electrode, and a pixel electrode connected to the drain electrode are disposed via a gate insulating film, and a semiconductor layer is at least the source electrode and the capacitor electrode A thin film transistor array disposed between the drain electrode and the drain electrode, wherein the capacitor electrode is larger than the pixel electrode in at least a region where the semiconductor layer is disposed in a plan view; A thin film transistor array comprising a capacitor electrode.
  2. On the thin-film transistor array according to claim 1, further an interlayer insulating film having an opening over the pixel electrode, and characterized in that the upper pixel electrode connected to the pixel electrode through the opening is provided Thin film transistor array.
  3. A gate electrode and a capacitor electrode are provided on an insulating substrate, a source electrode, a drain electrode, and a pixel electrode are disposed via a gate insulating film, and a semiconductor layer is disposed at least between the source electrode and the drain electrode. It is, and and an interlayer insulating film having an opening over the pixel electrode and on said drain electrode thereon, the connected upper pixel electrode is provided on the pixel electrode and the drain electrode through the opening A thin film transistor array, wherein the capacitor electrode is larger than the pixel electrode and is included in the capacitor electrode in at least a region where the semiconductor layer is disposed in a planar view. A thin film transistor array.
  4. And a gate electrode and a capacitor electrode on an insulating substrate, a gate insulating film formed thereon, the semiconductor layer disposed thereon, and said gate insulation under the top of the semiconductor layer, or the semiconductor layer a thin film transistor array the pixel electrode connected to the drain electrode and the source electrode and the drain electrode is disposed on the film, in a plan view arrangement, at least the semiconductor layer is disposed region, said capacitor electrode A thin film transistor array, wherein is larger than the pixel electrode, and the pixel electrode is included in the capacitor electrode.
  5. On the thin-film transistor array according to claim 4, further an interlayer insulating film having an opening over the pixel electrode, and characterized in that the upper pixel electrode connected to the pixel electrode through the opening is provided Thin film transistor array.
  6. And a gate electrode and a capacitor electrode on an insulating substrate, a gate insulating film formed thereon, the semiconductor layer disposed thereon, and said gate insulation under the top of the semiconductor layer, or the semiconductor layer It is disposed a source electrode and a drain electrode and a pixel electrode on the film, and the interlayer insulating film having an opening over the pixel electrode and on said drain electrode thereon, and the drain electrode through the opening A thin film transistor array provided with an upper pixel electrode connected to a pixel electrode, wherein the capacitor electrode is larger than the pixel electrode in at least a region where the semiconductor layer is arranged in a planar arrangement, and A thin film transistor array, wherein a pixel electrode is included in the capacitor electrode.
  7. A source electrode, a drain electrode, and a pixel electrode connected to the drain electrode on an insulating substrate; and a semiconductor layer disposed at least between the source electrode and the drain electrode; and on the pixel electrode A gate electrode and a capacitor electrode are disposed through a gate insulating film having an opening, and an interlayer insulating film having an opening on the pixel electrode thereon and an upper portion connected to the pixel electrode through the opening A thin film transistor array provided with a pixel electrode, wherein the capacitor electrode is larger than the pixel electrode and the pixel electrode serves as the capacitor electrode at least in a region where the semiconductor layer is disposed in a planar arrangement. A thin film transistor array comprising:
  8. And a source electrode and a drain electrode and a pixel electrode on an insulating substrate, and the semiconductor layer is disposed at least between the source electrode and the drain electrode, and an opening on the pixel electrode and on said drain electrode via a gate insulating film having, disposed gate electrode and the capacitor electrode, and an interlayer insulating film having an opening over the pixel electrode and on said drain electrode thereon, the drain electrode through the opening And an upper pixel electrode connected to the pixel electrode, wherein the capacitor electrode is larger than the pixel electrode in a planar arrangement at least in a region where the semiconductor layer is arranged The pixel electrode is included in the capacitor electrode.
  9. A pixel electrode connected to the source electrode, the drain electrode, and the drain electrode is disposed on the gate insulating film on the insulating substrate, and on the gate insulating film under the semiconductor layer . In addition, a gate electrode and a capacitor electrode are arranged through a gate insulating film having an opening on the pixel electrode, and an interlayer insulating film having an opening on the pixel electrode, and the pixel electrode through the opening A thin film transistor array provided with a connected upper pixel electrode, wherein, in a plan view arrangement, at least in the region where the semiconductor layer is arranged, the capacitor electrode is larger than the pixel electrode, and the pixel electrode is A thin film transistor array included in the capacitor electrode.
  10. Having a semiconductor layer on an insulating substrate, and the source electrode and the drain electrode and the pixel electrode above or below the semiconductor layer is disposed, the gate insulating and having an opening in the upper of the upper and the pixel electrode of the drain electrode through the membrane, it is arranged a gate electrode and the capacitor electrode, and an interlayer insulating film having an opening over the pixel electrode and on said drain electrode thereon, the pixel electrode and the drain electrode through the opening A thin film transistor array provided with an upper pixel electrode connected to the capacitor electrode, wherein the capacitor electrode is larger than the pixel electrode in at least a region where the semiconductor layer is disposed in a planar arrangement, and the pixel electrode Is included in the capacitor electrode.
  11.   An image display device in which a display medium is provided between the thin film transistor array according to claim 1 and a counter substrate having a counter electrode.
  12. 12. The method for driving an image display device according to claim 11 , wherein the semiconductor of the thin film transistor array is an n-channel, and a voltage applied to the capacitor electrode is lower than a minimum value of a voltage waveform applied to the source electrode. A driving method characterized by being low.
  13. 12. The method of driving an image display device according to claim 11 , wherein the semiconductor of the thin film transistor array is a p-channel, and a voltage applied to the capacitor electrode is higher than a maximum value of a voltage waveform applied to the source electrode. A driving method characterized by being expensive.
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5376826B2 (en) * 2008-04-04 2013-12-25 富士フイルム株式会社 Semiconductor device, semiconductor device manufacturing method, and display device
JP2010062276A (en) * 2008-09-03 2010-03-18 Brother Ind Ltd Oxide thin-film transistor and method of manufacturing the same
CN102160104B (en) 2008-09-19 2013-11-06 株式会社半导体能源研究所 Semiconductor device
JP5442234B2 (en) 2008-10-24 2014-03-12 株式会社半導体エネルギー研究所 Semiconductor device and display device
JP5607349B2 (en) * 2008-12-26 2014-10-15 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP4656262B2 (en) * 2009-02-23 2011-03-23 コニカミノルタホールディングス株式会社 Thin film transistor manufacturing method
CN106200185A (en) * 2009-10-16 2016-12-07 株式会社半导体能源研究所 Display device
KR101501420B1 (en) * 2009-12-04 2015-03-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Display device
CN102652356B (en) * 2009-12-18 2016-02-17 株式会社半导体能源研究所 Semiconductor device
CN105957481B (en) 2009-12-18 2019-12-31 株式会社半导体能源研究所 Display device
WO2011081041A1 (en) * 2009-12-28 2011-07-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the semiconductor device
US8780629B2 (en) * 2010-01-15 2014-07-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
KR20180102702A (en) 2010-01-20 2018-09-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Display device
CN102714029B (en) 2010-01-20 2016-03-23 株式会社半导体能源研究所 The display packing of display device
WO2011102248A1 (en) * 2010-02-19 2011-08-25 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic device
KR20130050914A (en) * 2010-03-30 2013-05-16 도판 인사츠 가부시키가이샤 Method for producing thin film transistor, and thin film transistor and image display device
KR101884798B1 (en) * 2010-04-09 2018-08-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
US20110279427A1 (en) * 2010-05-14 2011-11-17 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic appliance
US8698852B2 (en) * 2010-05-20 2014-04-15 Semiconductor Energy Laboratory Co., Ltd. Display device and method for driving the same
JP5133468B2 (en) * 2010-05-24 2013-01-30 シャープ株式会社 Thin film transistor substrate and manufacturing method thereof
US8603841B2 (en) * 2010-08-27 2013-12-10 Semiconductor Energy Laboratory Co., Ltd. Manufacturing methods of semiconductor device and light-emitting display device
JP5763474B2 (en) * 2010-08-27 2015-08-12 株式会社半導体エネルギー研究所 Optical sensor
JPWO2018038107A1 (en) * 2016-08-23 2019-06-24 凸版印刷株式会社 Organic thin film transistor, method of manufacturing the same and image display device
JP6294429B2 (en) * 2016-10-26 2018-03-14 株式会社半導体エネルギー研究所 Liquid crystal display

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3210437B2 (en) * 1991-09-24 2001-09-17 株式会社東芝 Liquid Crystal Display
JPH07152048A (en) * 1993-11-30 1995-06-16 Sanyo Electric Co Ltd Liquid crystal display device
JPH09269503A (en) * 1996-03-29 1997-10-14 Toshiba Corp Liquid crystal display device
JPH1096949A (en) * 1996-09-24 1998-04-14 Toshiba Corp Active matrix liquid crystal display device
JP4282219B2 (en) * 2000-11-28 2009-06-17 三洋電機株式会社 Pixel darkening method

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