JP2010003723A - Thin-film transistor, thin-film transistor array and image display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor array for which the parasitic capacitance of a thin-film transistor is reduced, and an image display provided with the thin-film transistor array. <P>SOLUTION: The thin-film transistor includes a semiconductor layer, a gate electrode, a source electrode and a drain electrode, and one of the gate electrode, the source electrode and the drain electrode has a shape with an opening. The opening has a circular, triangular or square shape, and the semiconductor layer is an organic semiconductor or an oxide semiconductor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor, a thin film transistor array, and an image display device, and more particularly to a thin film transistor, a thin film transistor array, and an image display device with reduced parasitic capacitance.

  Based on semiconductor-based transistors and integrated circuit technology, amorphous silicon (a-Si) or polysilicon (poly-Si) thin film transistors (Thin Film Transistors, hereinafter referred to as “TFTs”) are manufactured on glass substrates. ing. The TFT is applied to an image display device such as a liquid crystal display (for details, see, for example, Shoichi Matsumoto, “Liquid Crystal Display Technology—Active Matrix LCD” industrial book).

  Conventionally, for example, a TFT array as shown in FIG. 14 has been used. FIG. 14 shows one pixel of the TFT array. The TFT plays a role of a switch. When the TFT is turned on by a selection voltage applied to the gate wiring 53, the signal voltage applied to the source wiring 55 is applied to the pixel electrode 58 connected to the drain electrode 56. Write. The written voltage is held in a storage capacitor including the pixel electrode 58, a gate insulating film (not shown), and a capacitor electrode 59.

  In recent years, organic semiconductors and oxide semiconductors have appeared, and it has been shown that TFTs can be manufactured at a low temperature of 200 ° C. or lower, and expectations for flexible displays using plastic substrates are increasing. In addition to the feature of flexibility, it is also expected to be light, hard to break, and thin. In addition, an inexpensive and large-area display is expected by forming TFTs in a matrix using printing technology.

  By the way, in order to increase the area of the display, it is necessary not only to pattern the large area but also to increase the on-current. When the channel width is W and the channel length is L, the on-current is proportional to W / L. When it is desired to obtain a large on-current, as shown in FIG. 13, a comb-type electrode in which linear comb teeth are alternately arranged is often used as the source electrode 54 and the drain electrode 56. This is because the comb-shaped electrode has a large W and a small L.

  In order to make the display flexible, it is necessary to use a plastic substrate, and since the shrinkage of the base material is large, the electrodes are enlarged for the purpose of increasing the alignment margin.

  However, in the case of a comb-type electrode TFT array as shown in FIG. 13 or in the case of a conventional TFT array as shown in FIG. 14, the electrode overlap area between the gate electrode 52 and the drain electrode 56 is increased. There was a problem that the feedthrough was large.

Here, the feed-through, when changing from ON to OFF gate voltage V _g is as shown in FIG. 15, a phenomenon that the potential V _p of the pixel changes, the capacitance between the gate electrode 52 and drain electrode 56 Responsible.

Further, the capacitance between the gate electrode 52 and the source electrode 54 and the capacitance between the gate electrode 52 and the drain electrode 56 have caused the gate voltage response to deteriorate.
Shoichi Matsumoto, "Liquid Crystal Display Technology-Active Matrix LCD-" Industrial Books

  The present invention provides a thin film transistor array in which the parasitic capacitance of the thin film transistor is reduced.

  The invention according to claim 1 of the present invention includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and any one of the gate electrode, the source electrode, and the drain electrode has an opening. This is a thin film transistor.

  The invention according to claim 2 of the present invention is the thin film transistor according to claim 1, wherein the opening has a shape of one of a circle, a triangle, and a square.

  The invention according to claim 3 of the present invention is the thin film transistor according to claim 1, wherein the semiconductor layer is an organic semiconductor or an oxide semiconductor.

  According to a fourth aspect of the present invention, there is provided a substrate, a plurality of gate wirings formed on the substrate, a plurality of gate electrodes connected to the plurality of gate wirings, a plurality of gate wirings and a plurality of gate electrodes. Covering a plurality of capacitor wires formed in isolation on the same layer, a plurality of capacitor electrodes connected to the plurality of capacitor wires, a plurality of gate wires, a plurality of gate electrodes, a plurality of capacitor wires, and a plurality of capacitor electrodes A plurality of source wirings formed on the gate insulating film, a plurality of source electrodes connected to the plurality of source wirings, and a same layer of the plurality of source wirings and the plurality of source electrodes A plurality of pixel electrodes formed in isolation, a plurality of drain electrodes connected to the plurality of pixel electrodes, and a plurality of half electrodes formed in a gap between the plurality of source electrodes and the plurality of drain electrodes. Comprising a body layer, a drain electrode, in which any one of the source electrode or the gate electrode has a thin film transistor array which is a shape having an opening.

  The invention according to claim 5 of the present invention is the thin film transistor array according to claim 4, wherein the opening has a circular, triangular, or square shape.

  The invention according to claim 6 of the present invention is the thin film transistor array according to claim 4, wherein the plurality of semiconductor layers are organic semiconductors or oxide semiconductors.

  According to a seventh aspect of the present invention, there is provided a substrate, a plurality of source wires formed on the substrate, a plurality of source electrodes connected to the plurality of source wires, a plurality of source wires and a plurality of source electrodes. A plurality of pixel electrodes formed in isolation in the same layer, a plurality of drain electrodes connected to the plurality of pixel electrodes, a plurality of semiconductor layers formed in gaps between the plurality of source electrodes and the plurality of drain electrodes, A gate insulating film having an opening formed to cover the plurality of source wirings, the plurality of source electrodes, the plurality of semiconductor layers, the plurality of pixel electrodes, and the plurality of drain electrodes; and a plurality of gate insulating films formed on the gate insulating film A plurality of gate wirings connected to the plurality of gate wirings, and a plurality of capacitor wirings formed in isolation on the same layer of the plurality of gate wirings and the plurality of gate electrodes, and the plurality of capacitor wirings. A plurality of capacitor electrodes, an interlayer insulating film having an opening formed to cover the plurality of gate wirings, the plurality of gate electrodes, the plurality of capacitor wirings, and the plurality of capacitor electrodes, and formed on the interlayer insulating film A plurality of upper pixel electrodes electrically connected to the plurality of pixel electrodes, wherein one of the drain electrode, the source electrode, and the gate electrode has an opening. It is.

  The invention according to claim 8 of the present invention is the thin film transistor array according to claim 7, wherein the opening has any one of a circle, a triangle, and a square.

  The invention according to claim 9 of the present invention is the thin film transistor array according to claim 7, wherein the plurality of semiconductor layers are organic semiconductors or oxide semiconductors.

  The invention according to claim 10 of the present invention is the thin film transistor array according to any one of claims 4 to 9, wherein the substrate is a plastic substrate.

  According to an eleventh aspect of the present invention, there is provided an image display device comprising the thin film transistor array according to any one of the fourth to ninth aspects.

  The invention according to claim 12 of the present invention is the image display apparatus according to claim 11, wherein the image display apparatus is any one of a liquid crystal display, organic EL, and electronic paper.

  According to the present invention, it is possible to provide a thin film transistor array in which the parasitic capacitance of the thin film transistor is reduced.

  Embodiments of the present invention will be described with reference to the drawings. In the following, the drawings to be referred to are not drawn to scale for ease of explanation. Note that, in the embodiments, the same components are denoted by the same reference numerals, and redundant description among the embodiments is omitted.

  As shown in FIG. 1, a thin film transistor array (hereinafter referred to as “TFT array”) according to an embodiment of the present invention includes a substrate 1, a gate electrode 2, a gate wiring 3, a gate insulating film 4, a source electrode 5, and a source. A wiring 6, a drain electrode 7, a semiconductor layer 8, a sealing layer 9, a pixel electrode 10, a capacitor electrode 12, and a capacitor wiring 13 are provided. Further, although not shown here, an interlayer insulating film 11 and an upper pixel electrode 14 are provided. FIG. 1 shows one pixel region of the TFT array, but in reality, a plurality of TFT arrays arranged in a matrix form is the TFT array according to the embodiment of the present invention.

  Here, in the TFT array according to the embodiment of the present invention, the function of the source electrode 5 and the drain electrode 7 varies depending on the polarity of the voltage to be written, so the name cannot be determined by the operation. Therefore, for convenience, one is called the source electrode 5 and the other is called the drain electrode 7, and the names are unified. In the TFT array according to the embodiment of the present invention, the one connected to the wiring is called the source electrode 5, and the one connected to the pixel electrode 10 is called the drain electrode 7.

  As shown in FIG. 1, the TFT array according to the embodiment of the present invention has an opening in at least a portion of the source electrode 5 and the drain electrode 7 that overlaps the gate electrode 2. As shown in FIG. 1, by providing an opening in the drain electrode 7 at the overlapping portion between the drain electrode 7 and the gate electrode 2, the overlapping area between the gate electrode 2 and the drain electrode 7 can be reduced. 2 and the drain electrode 7 can be reduced in capacitance. Since the capacitance can be reduced, feedthrough can be reduced. Further, by providing an opening in the source electrode 5 at the overlapping portion between the source electrode 5 and the gate electrode 2, the overlapping area between the gate electrode 2 and the source electrode 5 can be reduced, and the gap between the gate electrode 2 and the source electrode 5 can be reduced. The capacitance can be reduced. This is because the capacitance is almost proportional to the overlapping area. Furthermore, by making one or both of the source electrode 5 and the drain electrode 7 into a shape having an opening, the adhesion between the source electrode 5, the drain electrode 7 and the semiconductor layer 8 is improved. Note that the source electrode 5 and the drain electrode 7 do not have to be comb-shaped.

  As shown in FIG. 2, the TFT array according to the embodiment of the present invention has openings in the source electrode 5, the drain electrode 7, and the gate electrode 2. By providing an opening in the drain electrode 7 and the gate electrode 2 at the overlapping portion of the drain electrode 7 and the gate electrode 2, the overlapping area of the gate electrode 2 and the drain electrode 7 can be reduced. The capacitance between 7 can be reduced. In addition, by providing openings in the source electrode 5 and the gate electrode 2 at the overlapping portion between the source electrode 5 and the gate electrode 2, the overlapping area between the gate electrode 2 and the source electrode 5 can be reduced. The capacitance between them can be reduced. The source electrode 5 and the drain electrode 7 may have a comb shape.

  As shown in FIG. 3, the TFT array according to the embodiment of the present invention has an opening in the gate electrode 2 overlapping the source electrode 5 and the drain electrode 7. By providing an opening in the gate electrode 2 at the overlapping portion between the drain electrode 7 and the gate electrode 2, the overlapping area between the gate electrode 2 and the drain electrode 7 can be reduced. The capacitance between them can be reduced. Further, by providing an opening in the gate electrode 2 at the overlapping portion between the source electrode 5 and the gate electrode 2, the overlapping area between the gate electrode 2 and the source electrode 5 can be reduced, and the capacitance between the gate electrode 2 and the source electrode 5 can be reduced. Can be small. The source electrode 5 and the drain electrode 7 may have a comb shape.

  As shown in FIGS. 1 and 2, the shape of the openings of the source electrode 5 and the drain electrode 7 is not limited to a circle as shown in FIG. 4C, but for example as shown in FIG. Thus, it can be formed in a triangular shape as shown in FIG. 4B. The shapes of the openings of the drain electrode 7 and the source electrode 5 are not limited to the above-described shapes, but can reduce the parasitic capacitance between the gate electrode 2 and the drain electrode 7 and between the gate electrode 2 and the source electrode 5. If it is.

  As shown in FIG. 5, when one or both of the source electrode 5 and the drain electrode 7 has a shape having an opening, a plurality of current paths are formed, and therefore, a disconnection occurs in a part of the opening. Since the disconnection stops at a part of the openings, it is difficult to achieve complete disconnection, so the influence can be reduced. In addition, when the TFT structure is a bottom contact type, the semiconductor layer 8 has a concavo-convex shape that bites into the openings of the source electrode 5 and the drain electrode 7, so that the adhesion between the source electrode 5 and the drain electrode 7 and the semiconductor layer 8 is improved. Will improve.

  The thin film transistor array according to the embodiment of the present invention has openings in the source electrode 5 and the drain electrode 7, but can also have openings in other portions. That is, other than the source electrode 5, the drain electrode 7, and the gate electrode 2, for example, the source wiring 6, the pixel electrode 10, the gate wiring 3, the capacitor electrode 12, the capacitor wiring 13, and the like may have openings.

  Further, the opening of the gate electrode 2 may be located not only in the overlapping portion between the source electrode 5 and the drain electrode 7 but also in the channel portion. In that case, since the induction of carriers is reduced by the amount corresponding to the opening of the gate electrode 2, it is necessary to make the channel width larger than when there is no opening. In order to prevent the positional relationship between the opening of the gate electrode 2 and the semiconductor layer 8 from affecting the on-current, the channel width should be an integral multiple of the pitch of the opening of the gate electrode 2 (perpendicular to the channel). desirable. The channel length is preferably an integral multiple of the opening pitch (channel direction) of the gate electrode 2.

  As the semiconductor layer 8 of the TFT array according to the embodiment of the present invention, an organic semiconductor or an oxide semiconductor can be used. By using an organic semiconductor or an oxide semiconductor as the semiconductor layer 8, the TFT array can be manufactured at a low temperature of 200 ° C. or lower, a heat-sensitive plastic substrate can be used, and a flexible display can be manufactured.

  Examples of the organic semiconductor material used for the semiconductor layer 8 include polythiophene derivatives, polyphenylene vinylene derivatives, polythienylene vinylene derivatives, polyallylamine derivatives, polyacetylene derivatives, acene derivatives, oligothiophene derivatives, and the like. As a method for forming an organic semiconductor, a solution can be formed at a low temperature of 200 ° C. or lower by applying and baking a solution using a spin coating method, a die coating method, a flexographic printing method, an inkjet printing method, or the like.

  As a material of an oxide semiconductor used for the semiconductor layer 8, an InGaZnO-based material, a ZnGaO-based material, an InZnO-based material, an InO-based material, a GaO-based material, a SnO-based material, or a mixture thereof can be used. As a method for forming the oxide semiconductor, a film can be formed at a low temperature of 200 ° C. or lower by using a sputtering method, a vacuum evaporation method, a laser ablation method, or the like.

  The substrate 1 of the TFT array according to the embodiment of the present invention can use plastic because the semiconductor layer 8 can be formed at a low temperature of 200 ° C. or lower. Examples of the material of the substrate 1 include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS), and polyvinyl chloride (PVC). ), Polyethylene (PE), polypropylene (PP), nylon (Ny), and the like.

  As a material of the gate electrode 2 and the capacitor electrode 12 of the TFT array according to the embodiment of the present invention, a metal such as Al, Cr, Au, Ag, Ni, Cu, and Mo, or a transparent conductive film such as ITO is used. Can do. As a method for forming the gate electrode 2 and the capacitor electrode 12, a film can be formed using a vacuum deposition method, a sputtering method, or the like, and can be formed using photolithography and etching after the film formation. In cases other than the above-described forming methods, screen printing methods, flexographic printing methods, gravure printing methods, offset printing methods, reverse printing methods, and the like, which are printing methods, can be used. Ag ink, Ni ink, Cu ink, or the like can be used as a material when the printing method is used. The ink is preferably a conductive ink containing metal particles having an average particle diameter of 50 nm or less, a water-soluble solvent, and a water-soluble resin.

Examples of the material for the gate insulating film 4 of the TFT array according to the embodiment of the present invention include organic insulating films such as polyvinylphenol, epoxy, and polyimide, and inorganic insulating films such as SiO ₂ , SiN, SiON, and Al ₂ O _3. Can be used. As a method for forming the gate insulating film 3, in the case of a solvent-soluble organic substance, a spin coating method, a die coating method, an ink jet method, or the like can be used. In cases other than the above-described forming methods, a sputtering method, a vacuum evaporation method, a laser ablation method, or the like can be used. For example, in the case where the gate insulating film 3 needs to be patterned such that the TFT structure is a top gate type, patterning is performed by photolithography, etching, lift-off, etc., or a printing method such as an ink jet method or a photosensitive organic material is used as the gate insulating film. Patterning can be performed directly by exposing and developing as the material No. 4.

  The semiconductor layer 8 of the TFT array according to the embodiment of the present invention is formed in a region where the source electrode 5 and the drain electrode 7 are close to each other, and overlaps the gate electrode 2 with the gate insulating film 4 interposed therebetween. The electric charge at the interface between the semiconductor layer 8 and the gate insulating film 4 can be controlled by the potential of the gate electrode 2, and the current of the drain electrode 7 can be controlled.

  The structure of the TFT according to the embodiment of the present invention may be a bottom gate type or a top gate type. Moreover, a bottom contact may be sufficient and a top contact may be sufficient. As shown in FIG. 6A, in the bottom gate type / bottom contact, the stacking order is the substrate 1, the gate electrode 2, the gate insulating film 4, the source electrode 5 and the drain electrode 7, and the semiconductor layer 8. As shown in FIG. 6B, in the bottom gate type / top contact, the stacking order is the substrate 1, the gate electrode 2, the gate insulating film 4, the semiconductor layer 8, the source electrode 5, and the drain electrode 7. Further, a gate wiring 3 is provided in the same layer as the gate electrode 2, and a source wiring 6 and a pixel electrode 10 are provided in the same layer as the source electrode 5 and the drain electrode 7. Further, the capacitor electrode 12 and the capacitor wiring 13 may be provided in the same layer as the gate electrode 2 or in a different layer. In the case of the bottom gate type, the sealing layer 9 may be provided on the semiconductor layer 8.

  As shown in FIG. 6C, in the top gate type / bottom contact, the stacking order is the substrate 1, the source electrode 5 and the drain electrode 7, the semiconductor layer 8, the gate insulating film 4, and the gate electrode 2. As shown in FIG. 6D, in the top gate type / top contact, the stacking order is the substrate 1, the semiconductor layer 8, the source electrode 5 and the drain electrode 7, the gate insulating film 4, and the gate electrode 2. Further, the gate wiring 3 is provided in the same layer as the gate electrode 2, and the source wiring 6 and the pixel electrode 10 are provided in the same layer as the source electrode 5 and the drain electrode 7. Further, the capacitor electrode 12 and the capacitor wiring 13 may be provided in the same layer as the gate electrode 2 or in a different layer. In the case of the top gate type, it is desirable to have the interlayer insulating film 11 and the upper pixel electrode 14.

Although the TFT can be operated even when the semiconductor layer 8 is formed over the entire surface, it is preferable that the semiconductor layer 8 be patterned because the off-current can be reduced. The semiconductor layer 8 is patterned by spin-coating, die-coating, sputtering, vacuum deposition, laser ablation, etc., and then patterned using photolithography or a similar method after film formation, or film formation and patterning are performed simultaneously. Or a lift-off method in which a resist pattern is formed in advance and the resist is removed after film formation on the entire surface. Or the case of using an organic semiconductor in the semiconductor layer 8, after forming a sealing layer 9 described later, 0 ₂ plasma sealing layer 9 as a mask, N ₂ plasma, or performing etching with Ar plasma, dissolved sealing layer 9 Without patterning, the semiconductor layer 8 may be patterned by a method such as rinsing with a liquid that dissolves the semiconductor layer 8.

  As the source electrode 5, the source wiring 6, the drain electrode 7, and the pixel electrode 10 of the TFT array according to the embodiment of the present invention, the same material and the same method as the gate electrode 2 can be used. The most suitable method is reverse printing.

  By forming the source electrode 5 and the drain electrode 7 using a reverse printing method, a highly accurate thin film transistor can be easily manufactured.

  The sealing layer 9 of the TFT array according to the embodiment of the present invention can be used to prevent the characteristic change of the semiconductor layer 8. As a material of the sealing layer 9, a fluorinated resin is suitable. As a method for forming the sealing layer 7, a screen printing method is suitable.

  As a material for the interlayer insulating film 11 of the TFT array according to the embodiment of the present invention, polyvinylphenol (PVP), acrylic, epoxy, polyimide, or the like can be used. As a method for forming the interlayer insulating film 11, a screen printing method is suitable, but it may be formed by exposure / development after forming a photosensitive film.

  As a material of the upper pixel electrode 14 of the TFT array according to the embodiment of the present invention, a metal such as Al, Cr, Au, Ag, Ni, Cu, a transparent conductive film such as ITO, or the like can be used. As a method for forming the upper pixel electrode 14, a method such as photolithography and etching after formation using a vacuum deposition method, a sputtering method, or the like can be used. However, Ag ink, Ni ink, Cu ink, etc. are screen printed. It is preferable to form using a method.

  The TFT array according to the embodiment of the present invention may include the interlayer insulating film 11 and the upper pixel electrode 14, and the upper pixel electrode 14 may be connected to the pixel electrode 10. In particular, in the top gate type, it is desirable to have the interlayer insulating film 11 and the upper pixel electrode 14. In order to connect the upper pixel electrode 14 to the pixel electrode 10, the bottom gate type requires an opening in the interlayer insulating film 11, and the top gate type requires an opening in the gate insulating film 3 and the interlayer insulating film 11.

  7 (a) to 8 (d), 9 (a) to 10 (c), and 11 (a) to 12 (c) show the TFT array manufacturing method according to the embodiment of the present invention. Yes, a cross-sectional view and a plan view are shown. 9 (a) to 10 (c) and FIGS. 11 (a) to 12 (c) are the same methods, although the shapes are different from those of FIGS. 7 (a) to 8 (d). Description is omitted.

  First, as shown in FIG. 7A, the gate electrode 2 and the capacitor electrode 10 are formed on the substrate 1. Next, as shown in FIG. 7B, a gate insulating film 3 is formed on the entire surface. Next, as shown in FIG. 7C, the source electrode 5, the source wiring 6, the drain electrode 7, and the pixel electrode 10 are formed. Next, as shown in FIG. 8A, the semiconductor layer 8 is formed. Next, as shown in FIG. 8B, the sealing layer 9 is formed. Next, as shown in FIG. 8C, an interlayer insulating film 11 is formed. Next, as shown in FIG. 8D, the upper pixel electrode 14 is formed.

  The above is the procedure for the bottom gate type / bottom contact, but in the case of the bottom gate type / top contact, top gate type / bottom contact, top gate type / top contact, the layer order may be changed.

  The TFT array according to the embodiment of the present invention can be used for an image display device. As an image display device, for example, it can be used for an electrophoretic display, a liquid crystal display, an organic electroluminescence display, or the like.

  A TFT array shown in FIG. 1 as Example 1 was produced by the steps of FIGS. 7A to 8D. First, as shown in FIG. 7A, a 50 nm Al film is formed on the PEN substrate 1 by vacuum deposition, and the gate electrode 2 and the capacitor electrode 12 are formed by photolithography and wet etching. did.

  Next, as shown in FIG. 7B, as the gate insulating film 4, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol.

  Next, as shown in FIG. 7C, the thickness of the source electrode 5, the source wiring 6, the drain electrode 7, and the pixel electrode 10 is obtained by printing Ag ink using a reverse printing method and baking it at 180 ° C. A pattern with a thickness of 50 nm was formed. As shown in FIG. 1, the shape of the source electrode 5 and the drain electrode 7 at that time is such that the width of the source electrode 5 and the drain electrode 7 is 10 μm, the overlapping length of the gate electrode 2 and the drain electrode 7 is 120 μm, and the number of the drain electrodes 7 , The openings of the source electrode 5 and the drain electrode 7 are circular with a diameter of 5 μm, the pitch is 10 μm, the channel length is 5 μm, and the channel width is 800 μm.

  Next, as shown in FIG. 8A, the polythiophene solution was printed using a flexographic printing method and baked at 100 ° C., thereby forming the semiconductor layer 8.

  Next, as shown in FIG. 8B, Cytop, which is a fluorinated resin, was printed and baked using a screen printing method to form a sealing layer 9. Next, as shown in FIG. 8C, an epoxy resin was printed and baked using a screen printing method to form an interlayer insulating film 11. Next, as shown in FIG. 8D, the upper pixel electrode 14 was formed by printing and baking the upper Ag paste using a screen printing method.

  An electrophoretic display having a structure in which an electrophoretic display body was sandwiched between the thin film transistor array shown in FIG. 1 and the substrate with the counter electrode was manufactured, and it was confirmed that it operated as expected.

  Here, to operate as expected, a predetermined write operation (predetermined source voltage, gate voltage, gate pulse width, write cycle, write count) calculated from the characteristics of the electrophoretic display and the transistor characteristics was performed. However, this means that it has been operated with the expected number of writes.

  A TFT array shown in FIG. 2 as Example 2 was produced by the steps of FIGS. 9A to 10C. First, as shown in FIG. 9A, a 50 nm Al film is formed on the PEN substrate 1 by vacuum deposition, and the gate electrode 2 and the capacitor electrode 12 are formed by photolithography and wet etching. did. The opening of the gate electrode 2 is a circle having a diameter of 4 μm and a pitch of 12 μm.

Next, as shown in FIG. 9B, SiN was used as a target, Ar, O ₂ , and N ₂ were flowed, and an RF sputtering method was used to form 500 nm of SiON as the gate insulating film 4.

Next, as shown in FIG. 9 (c), InGaZnO ₄ is used as a target, Ar and O ₂ are flowed and RF sputtering is used to form an InGaZnO film of 50 nm as the semiconductor layer 8, and photolithography and hydrochloric acid are used. Patterning was performed by wet etching.

  Next, as shown in FIG. 9D, a resist pattern is formed in advance as the source electrode 5, the source wiring 6, the drain electrode 7, and the pixel electrode 10, and a pattern with a thickness of 50 nm is formed by lift-off after depositing Al. Formed. At that time, the width of the source electrode 5 and the drain electrode 7 is 48 μm, the overlapping length with the gate electrode 2 is 24 μm, the opening of the source electrode 5 and the drain electrode 7 is a square of 6 μm square, the pitch is 12 μm, and the channel length is 24 μm. The channel width is 8 μm.

  Next, as shown in FIG. 10A, Cytop, which is a fluorinated resin, was printed and baked using a screen printing method to form a sealing layer 9. Next, as shown in FIG. 10B, an epoxy resin was printed and baked using a screen printing method to form an interlayer insulating film 11. Next, as shown in FIG. 10C, the upper pixel electrode 14 was formed by printing and baking Ag paste using a screen printing method.

  An electrophoretic display having a structure in which the electrophoretic display body is sandwiched between the thin film transistor array shown in FIG. 2 and the substrate with the counter electrode was manufactured, and it was confirmed that the electrophoretic display operated as expected.

  A TFT array shown in FIG. 3 as Example 3 was produced by the steps of FIGS. 11 (a) to 12 (c). First, as shown in FIG. 11A, a 50 nm Al film is formed on the PEN substrate 1 by vacuum deposition, and the gate electrode 2 and the capacitor electrode 12 are formed by photolithography and wet etching. did. The openings of the gate electrode 2 are circular with a diameter of 4 μm and the pitch is 10 μm.

Next, as shown in FIG. 11B, SiN was used as a target, Ar, O ₂ , and N ₂ were flowed and RF sputtering was used to form SiON having a thickness of 500 nm as the gate insulating film 4.

Next, as shown in FIG. 11C, using InGaZnO ₄ as a target, flowing Ar and O ₂ and using RF sputtering, an InGaZnO film having a thickness of 50 nm is formed as the semiconductor layer 8, and photolithography and hydrochloric acid are used. Patterning was performed by wet etching.

  Next, as shown in FIG. 11D, a resist pattern is formed in advance as the source electrode 5, the source wiring 6, the drain electrode 7, and the pixel electrode 10, and a pattern with a thickness of 50 nm is formed by lift-off after depositing Al. Formed. At this time, the width of the source electrode 5 and the drain electrode 7 is 48 μm, the overlap length with the gate electrode 2 is 24 μm, the channel length is 24 μm, and the channel width is 8 μm.

  Next, as shown in FIG. 12A, Cytop, which is a fluorinated resin, was printed and baked using a screen printing method to form a sealing layer 9. Next, as shown in FIG. 12B, an epoxy resin was printed and baked using a screen printing method to form an interlayer insulating film 11. Next, as shown in FIG. 12C, the upper pixel electrode 14 was formed by printing and baking an Ag paste using a screen printing method.

  An electrophoretic display having a structure in which an electrophoretic display body is sandwiched between the thin film transistor array shown in FIG. 3 and the substrate with the counter electrode manufactured as described above was manufactured, and it was confirmed that the electrophoretic display operates with 1.5 times the number of writings as expected.

[Comparative Example 1]
The TFT array shown in FIG. 1 was produced in the same manner as in Example 1, but the source electrode 5 and the drain electrode 7 were not provided with openings. When the source electrode 5 and the drain electrode 7 of Comparative Example 1 are not provided with openings, the overlapping area of the drain electrode 7 and the gate electrode 2 and the overlapping area of the source electrode 5 and the gate electrode 2 are 1.25 times that of Example 1. Increased to. Therefore, it is considered that each capacity has also increased by 1.25 times. When the TFT array of Comparative Example 1 was actually produced as electronic paper and writing was performed, it took 1.5 times as many times as expected. In Example 1, since the opening of the drain electrode 7 has a diameter of 5 μm, in Comparative Example 1, the opening area is added to the area of the drain electrode 7 by 19.625 μm ² × 48. Feedthrough V _p is increased with increase in parasitic capacitance overlap area of the gate electrode 2 and the drain electrode 7 is increased.

[Comparative Example 2]
When there is no hole in Example 2 and Example 3, the overlapping area of the drain electrode 7 and the gate electrode 2 and the overlapping area of the source electrode 5 and the gate electrode 2 are 1.25 times that of Example 2, Increased 67 times. Therefore, each capacity seems to have increased accordingly. When the TFT array of Comparative Example 2 was actually fabricated as electronic paper and writing was performed, the number of times of writing twice as expected was required.

It is a top view which shows 1 pixel of the thin-film transistor array which concerns on embodiment of this invention. It is a top view which shows 1 pixel of the thin-film transistor array which concerns on embodiment of this invention. It is a top view which shows 1 pixel of the thin-film transistor array which concerns on embodiment of this invention. It is sectional drawing which shows the laminated structure of the thin-film transistor array which concerns on embodiment of this invention. It is a figure which shows the pattern of the opening part of the source electrode / drain electrode which concerns on embodiment of this invention. It is a figure which shows when the source electrode / drain electrode which concerns on embodiment of this invention raise | generates disconnection. (A)-(c) is sectional drawing and top view which show the manufacturing process of 1 pixel of the thin-film transistor which concerns on embodiment of this invention. (A)-(d) is sectional drawing and top view which show the manufacturing process of 1 pixel of the thin-film transistor which concerns on embodiment of this invention. (A)-(d) is sectional drawing and top view which show the manufacturing process of 1 pixel of the thin-film transistor which concerns on embodiment of this invention. (A)-(c) is sectional drawing and top view which show the manufacturing process of 1 pixel of the thin-film transistor which concerns on embodiment of this invention. (A)-(d) is sectional drawing and top view which show the manufacturing process of 1 pixel of the thin-film transistor which concerns on embodiment of this invention. (A)-(c) is sectional drawing and top view which show the manufacturing process of 1 pixel of the thin-film transistor which concerns on embodiment of this invention. It is a top view which shows the structure of 1 pixel of the thin-film transistor array which has the conventional comb-type electrode. It is a top view which shows the structure of 1 pixel of the conventional thin-film transistor array. It is a voltage waveform of an example (in the case of n channel) of a drive method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Gate electrode 3 ... Gate wiring 4 ... Gate insulating film 5 ... Source electrode 6 ... Source wiring 7 ... Drain electrode 8 ... Semiconductor layer 9 ... Sealing layer 10 ... Pixel electrode 11 ... Interlayer insulating film 12 ... Capacitor electrode DESCRIPTION OF SYMBOLS 13 ... Capacitor wiring 14 ... Upper pixel electrode 52 ... Gate electrode 53 ... Gate wiring 54 ... Source electrode 55 ... Source wiring 56 ... Drain electrode 57 ... Semiconductor layer 58 ... Pixel electrode 59 ... Capacitor electrode 60 ... Capacitor wiring

Claims (12)

A semiconductor layer, a gate electrode, a source electrode, and a drain electrode;
A thin film transistor, wherein any one of the gate electrode, the source electrode, and the drain electrode has an opening.   The thin film transistor according to claim 1, wherein the opening has a shape of any one of a circle, a triangle, and a square.   The thin film transistor according to claim 1, wherein the semiconductor layer is an organic semiconductor or an oxide semiconductor. A substrate,
A plurality of gate wirings formed on the substrate and a plurality of gate electrodes connected to the plurality of gate wirings;
A plurality of capacitor wires formed in the same layer of the plurality of gate wires and the plurality of gate electrodes, and a plurality of capacitor electrodes connected to the plurality of capacitor wires;
A gate insulating film formed to cover the plurality of gate wirings, the plurality of gate electrodes, the plurality of capacitor wirings, and the plurality of capacitor electrodes;
A plurality of source wirings formed on the gate insulating film and a plurality of source electrodes connected to the plurality of source wirings;
A plurality of pixel electrodes formed on the same layer of the plurality of source lines and the plurality of source electrodes, and a plurality of drain electrodes connected to the plurality of pixel electrodes;
A plurality of semiconductor layers formed in gaps between the plurality of source electrodes and the plurality of drain electrodes,
A thin film transistor array, wherein any one of the drain electrode, the source electrode, and the gate electrode has an opening.   The thin film transistor array according to claim 4, wherein the opening has a circular, triangular, or square shape.   The thin film transistor array according to claim 4, wherein the plurality of semiconductor layers are organic semiconductors or oxide semiconductors. A substrate,
A plurality of source lines formed on the substrate and a plurality of source electrodes connected to the plurality of source lines;
A plurality of pixel electrodes formed on the same layer of the plurality of source lines and the plurality of source electrodes, and a plurality of drain electrodes connected to the plurality of pixel electrodes;
A plurality of semiconductor layers formed in gaps between the plurality of source electrodes and the plurality of drain electrodes;
A gate insulating film having an opening formed to cover the plurality of source wirings, the plurality of source electrodes, the plurality of semiconductor layers, the plurality of pixel electrodes, and the plurality of drain electrodes;
A plurality of gate wirings formed on the gate insulating film and a plurality of gate electrodes connected to the plurality of gate wirings;
A plurality of capacitor wirings formed in the same layer of the plurality of gate wirings and the plurality of gate electrodes, and a plurality of capacitor electrodes connected to the plurality of capacitor wirings;
An interlayer insulating film having an opening formed to cover the plurality of gate wirings, the plurality of gate electrodes, the plurality of capacitor wirings, and the plurality of capacitor electrodes;
A plurality of upper pixel electrodes formed on the interlayer insulating film and conducted to the plurality of pixel electrodes;
A thin film transistor array, wherein any one of the drain electrode, the source electrode, and the gate electrode has an opening.   The thin film transistor array according to claim 7, wherein the opening has a circular, triangular, or square shape.   The thin film transistor array according to claim 7, wherein the plurality of semiconductor layers are organic semiconductors or oxide semiconductors.   The thin film transistor array according to claim 4, wherein the substrate is a plastic substrate.   An image display device comprising the thin film transistor array according to claim 4.   The image display device according to claim 11, wherein the image display device is a liquid crystal display, an organic EL, or an electronic paper.